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From: Nick Clifton <nickc@redhat.com>
To: echristo@apple.com, richard@codesourcery.com
Cc: gcc-patches@gcc.gnu.org
Subject: RFA/RFC: GCC has an incorrect length for the ldc1 instruction
Date: Tue, 07 Aug 2007 08:07:00 -0000	[thread overview]
Message-ID: <m37io7g46h.fsf@redhat.com> (raw)

[-- Attachment #1: Type: text/plain, Size: 2368 bytes --]

Hi Eric, Hi Richard,

  Another customer bug report has pointed out a problem with the MIPS
  compiler.  Compile the attached test case with:

    mips64vrel-elf-gcc -mgp32 -mlong64 -march=vr5000 -O2 128195.c -S -dp

  (I presume that this problem exists with other MIPS targets apart
  from the mips64vrel-elf.  It just so happens that this is the
  toolchain that the customer is using).
  
  Look at the assembler output.  In particular:

    ldc1  $f2,0($4)	 # 6	*movdf_hardfloat_32bit/3	[length = 8]

  Note the assumed length of the ldc1 instruction.  In the original
  bug report this was a problem because the ldc1 instruction was
  between an mfhi and a mult instruction, and gcc thought that this
  was sufficient to act as a hilo interlock.  This does not appear to
  happen with the current mainline gcc sources, but I still think that
  the incorrect length is a bug.

  Tracking the problem through the code, I found that
  mips_address_insns() was saying that it takes 2 instructions to
  implement this rtl:

    (mem:DF (reg:SI $4))

  when in fact it only takes one.  The patch below fixes this, in what
  I hope is the correct way.  I checked the patch by recompiling a
  mips64vrel-elf toolchain and running a gcc testsuite regression test
  for the default multilib and the vr5000/long64/gp32 multilib.
  - There were no regressions.  I am not sure if this covers all
  eventualities though.

  What do you think, should I apply the patch ?

Cheers
  Nick

gcc/ChangeLog
2007-08-06  Nick Clifton  <nickc@redhat.com>

	* config/mips/mips.c (mips_address_insns): DFmode loads and
	stores only take one instruction when hardware doubles are
	supported.

Index: gcc/config/mips/mips.c
===================================================================
--- gcc/config/mips/mips.c	(revision 127178)
+++ gcc/config/mips/mips.c	(working copy)
@@ -1963,6 +1963,9 @@ mips_address_insns (rtx x, enum machine_
   if (mode == BLKmode)
     /* BLKmode is used for single unaligned loads and stores.  */
     factor = 1;
+  else if (mode == DFmode && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT)
+    /* Doubles can be accessed by a single instruction when the hardware supports it.  */
+    factor = 1;
   else
     /* Each word of a multi-word value will be accessed individually.  */
     factor = (GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD;


[-- Attachment #2: 128195.c --]
[-- Type: application/octet-stream, Size: 276 bytes --]

#include <stdio.h>

extern void func (int, int, int);

int
main (void)
{
  static long     long1;
  long            long3;
  static long     long4;
  static double * pd2;
  static double * pd4;

  func (1, (((! *pd2) >= *pd4) * ((long3 * long1) && long4)), 0);

  return 0;
}

             reply	other threads:[~2007-08-07  8:07 UTC|newest]

Thread overview: 6+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2007-08-07  8:07 Nick Clifton [this message]
2007-08-07  9:54 ` Richard Sandiford
2007-08-07 15:03   ` Nick Clifton
2007-08-10  7:15   ` Nick Clifton
2007-08-10  7:58     ` Richard Sandiford
2007-08-10 15:41       ` Richard Sandiford

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