From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 115067 invoked by alias); 5 Sep 2019 20:56:12 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Received: (qmail 115059 invoked by uid 89); 5 Sep 2019 20:56:12 -0000 Authentication-Results: sourceware.org; auth=none X-Spam-SWARE-Status: No, score=-14.4 required=5.0 tests=AWL,BAYES_00,GIT_PATCH_0,GIT_PATCH_1,GIT_PATCH_2,GIT_PATCH_3,SPF_PASS autolearn=ham version=3.3.1 spammy= X-HELO: sam.airs.com Received: from sam.airs.com (HELO sam.airs.com) (64.13.145.90) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Thu, 05 Sep 2019 20:56:09 +0000 Received: (qmail 28713 invoked by uid 10); 5 Sep 2019 20:56:07 -0000 Received: (qmail 5745 invoked by uid 500); 5 Sep 2019 20:55:36 -0000 From: Ian Lance Taylor To: Christophe Lyon Cc: Kyrill Tkachov , Christophe Lyon , "gcc-patches@gcc.gnu.org" Subject: Re: [ARM/FDPIC v5 13/21] [ARM] FDPIC: Force LSB bit for PC in Cortex-M architecture References: <20190515124006.25840-1-christophe.lyon@st.com> <20190515124006.25840-14-christophe.lyon@st.com> <19a091e0-c1fe-c4f7-5eab-5e09ab1de3fd@foss.arm.com> Date: Thu, 05 Sep 2019 20:56:00 -0000 In-Reply-To: (Christophe Lyon's message of "Thu, 5 Sep 2019 10:31:51 +0200") Message-ID: User-Agent: Gnus/5.13 (Gnus v5.13) Emacs/26.2 (gnu/linux) MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable X-SW-Source: 2019-09/txt/msg00321.txt.bz2 Christophe Lyon writes: > Sorry, I forgot again to cc: Ian. As far as I'm concerned, it's fine for architecture maintainers to approve changes to architecture-specific files in libgcc. Ian > On Thu, 5 Sep 2019 at 10:30, Christophe Lyon = wrote: >> >> On Thu, 29 Aug 2019 at 17:32, Kyrill Tkachov >> wrote: >> > >> > Hi Christophe, >> > >> > On 5/15/19 1:39 PM, Christophe Lyon wrote: >> > > Without this, when we are unwinding across a signal frame we can jump >> > > to an even address which leads to an exception. >> > > >> > > This is needed in __gnu_persnality_sigframe_fdpic() when restoring t= he >> > > PC from the signal frame since the PC saved by the kernel has the LSB >> > > bit set to zero. >> > > >> > > 2019-XX-XX Christophe Lyon >> > > Micka=C3=ABl Gu=C3=AAn=C3=A9 >> > > >> > > libgcc/ >> > > * config/arm/unwind-arm.c (_Unwind_VRS_Set): Handle v7m >> > > architecture. >> > > >> > > Change-Id: Ie84de548226bcf1751e19a09e8f091fb3013ccea >> > > >> > > diff --git a/libgcc/config/arm/unwind-arm.c >> > > b/libgcc/config/arm/unwind-arm.c >> > > index 9ba73e7..ba47150 100644 >> > > --- a/libgcc/config/arm/unwind-arm.c >> > > +++ b/libgcc/config/arm/unwind-arm.c >> > > @@ -199,6 +199,11 @@ _Unwind_VRS_Result _Unwind_VRS_Set >> > > (_Unwind_Context *context, >> > > return _UVRSR_FAILED; >> > > >> > > vrs->core.r[regno] =3D *(_uw *) valuep; >> > > +#if defined(__ARM_ARCH_7M__) >> > > + /* Force LSB bit since we always run thumb code. */ >> > > + if (regno =3D=3D 15) >> > > + vrs->core.r[regno] |=3D 1; >> > > +#endif >> > >> > Hmm, this looks quite specific. There are other architectures that are >> > thumb-only too (6-M, 7E-M etc). >> > >> > Would checking for __thumb__ be better? >> > >> Right. >> The attached updated patch also uses R_PC instead of 15. >> >> Christophe >> >> > Thanks, >> > >> > Kyrill >> > >> > >> > > return _UVRSR_OK; >> > > >> > > case _UVRSC_VFP: >> > > -- >> > > 2.6.3 >> > >