Commit: RX: Add peepholes for move followed by compare

Commit: RX: Add peepholes for move followed by compare

[Nick Clifton]

Hi Guys,

  I am applying the patch below to add a peephole optimization to the RX
  backend.  It was suggested by Kazuhio Inaoka at Renesas Japan, and
  adapted by me to use peephole2 system.  It finds a register move
  followed by a comparison of the moved register against zero and
  replaces the two instructions with a single addition instruction.  The
  addition does not actually do anything since the value being added is
  zero, but as a side effect it moves the register and performs the
  comparison.

Cheers
  Nick

gcc/ChangeLog
2011-05-17  Kazuhio Inaoka  <kazuhiro.inaoka.ud@renesas.com>
	    Nick Clifton  <nickc@redhat.com>

	* config/rx/rx.md: Add peepholes to match a register move followed
	by a comparison of the moved register.  Replace these with an
	addition of zero that does both actions in one instruction.

Index: gcc/config/rx/rx.md
===================================================================
--- gcc/config/rx/rx.md	(revision 173815)
+++ gcc/config/rx/rx.md	(working copy)
@@ -904,6 +904,39 @@
    (set_attr "length"   "3,4,5,6,7,6")]
 )
 
+;; Peepholes to match:
+;;   (set (reg A) (reg B))
+;;   (set (CC) (compare:CC (reg A/reg B) (const_int 0)))
+;; and replace them with the addsi3_flags pattern, using an add
+;; of zero to copy the register and set the condition code bits.
+(define_peephole2
+  [(set (match_operand:SI 0 "register_operand")
+        (match_operand:SI 1 "register_operand"))
+   (set (reg:CC CC_REG)
+        (compare:CC (match_dup 0)
+                    (const_int 0)))]
+  ""
+  [(parallel [(set (match_dup 0)
+		   (plus:SI (match_dup 1) (const_int 0)))
+	      (set (reg:CC_ZSC CC_REG)
+		   (compare:CC_ZSC (plus:SI (match_dup 1) (const_int 0))
+				   (const_int 0)))])]
+)
+
+(define_peephole2
+  [(set (match_operand:SI 0 "register_operand")
+        (match_operand:SI 1 "register_operand"))
+   (set (reg:CC CC_REG)
+        (compare:CC (match_dup 1)
+                    (const_int 0)))]
+  ""
+  [(parallel [(set (match_dup 0)
+		   (plus:SI (match_dup 1) (const_int 0)))
+	      (set (reg:CC_ZSC CC_REG)
+		   (compare:CC_ZSC (plus:SI (match_dup 1) (const_int 0))
+				   (const_int 0)))])]
+)
+
 (define_expand "adddi3"
   [(set (match_operand:DI          0 "register_operand")
 	(plus:DI (match_operand:DI 1 "register_operand")