From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-pl1-x630.google.com (mail-pl1-x630.google.com [IPv6:2607:f8b0:4864:20::630]) by sourceware.org (Postfix) with ESMTPS id B96C23861894 for ; Tue, 19 Dec 2023 16:09:10 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org B96C23861894 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=dabbelt.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=dabbelt.com ARC-Filter: OpenARC Filter v1.0.0 sourceware.org B96C23861894 Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=2607:f8b0:4864:20::630 ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1703002153; cv=none; b=i/0Q4+AIv3ykVK2f/UnApQdla38cTjMoUbxVN9myj0g4aGzttS1gp6hoJuIzhNm+XIQrPmY5zOLmrZny3g73ZspX/Fuerxp/fQn8Nzz+EbLW6AIGZnNK/soUtWfeq9JM9OKQNKEbstHy+VAhzVX5pnmx7TMwAqiftBl934Q3Muo= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1703002153; c=relaxed/simple; bh=0kykf7bT2RYhjaBQNq76rqRvbc99k++rwnfTJd0WnaQ=; h=DKIM-Signature:Date:Subject:From:To:Message-ID:Mime-Version; b=KX4JKeI5ZCItX6hPDe+tvFRHCsWRZd/j8IDnRhiNs/e1x5P+iL7OSX2wEinCQWxejT9yHyhkW2y3RKwJceOBMFw8wbCgH50EfIg78v1DOzKDLUxeqAhfPA68GPoY9ZlErgElwO9tHzIFV0PQGglkbUy6AZ1L6wwXqod/0Qt1reg= ARC-Authentication-Results: i=1; server2.sourceware.org Received: by mail-pl1-x630.google.com with SMTP id d9443c01a7336-1d3e2972f65so4077945ad.3 for ; Tue, 19 Dec 2023 08:09:10 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=dabbelt-com.20230601.gappssmtp.com; s=20230601; t=1703002149; x=1703606949; darn=gcc.gnu.org; h=content-transfer-encoding:mime-version:message-id:to:from:cc :in-reply-to:subject:date:from:to:cc:subject:date:message-id :reply-to; bh=OutxsO8taTX4AYZlxG4ITZfptOo66L1xNugoPYp+Px4=; b=Y350cl63y1rVXm/bfG4/hOdzwKwvr9rnTDXP1ZU9eF7QGtuigcWCI3gCOaE3KRISiU 2oiVxKyKCL7GLS33/9T2rKpIikW4tVMhUoSjMLabRjDids++ngZoGoSlD2vTDbNt+cI/ Lr7UYABVnlAxm+6KNoMJUhNT7bGsZEDAjBQkIL0K3/N8i/Qutt6G6IpYWWz6pPc6PpDj u6I88FKNz7LZb9wYbNpR4b14PyGUK8zrxA3AEtcj7pE+HnkiHW8GKAVbgGOHYiPH405g 8rIl9R2CmEUZZ1DheiiZI1OLxk4ziWGjcN13PG7ERy8Gl7isMeBEx7lD3Hm9itOWqSSc 2CPg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1703002149; x=1703606949; h=content-transfer-encoding:mime-version:message-id:to:from:cc :in-reply-to:subject:date:x-gm-message-state:from:to:cc:subject:date :message-id:reply-to; bh=OutxsO8taTX4AYZlxG4ITZfptOo66L1xNugoPYp+Px4=; b=to9jqoNl0By7DJLwV/D4bTnBlZThHb6p0UP8EpqSCp72yxvVEnro/akfpnZJmIAoJ3 Ajf532QXNOhrAfnKZrxTfCE94UIMBdwblrnE9FH63r6elGbA3X0pWd5ACeskLUr3ZKC6 ViFqt6q5b9G2PVLpFAfg95KHZSUksuuHanMwNzI06lV5TI6kj/0NUy8G1f/mpqgzoJsn yJ1eKygHiVzYIE5gfpWLUjlhC0xePPFL9wUAC0/dg5OaOtIVJb4DPdt8Sp9RWkteHNrI EmzVREs5J61f6WOKttOWC7fDMBjAEpPz4nqS7PSl7ydOmsmmm5rwgfUhmXESU3+bNdCy DwRA== X-Gm-Message-State: AOJu0Yw2ANwRtUtVblla/N1ODYmbS/2puImPqyvm3qE9isag6QK39i0/ nqyKOMfnxyy2NO/fy6FZdzolZF7yDd3YChRAP+s= X-Google-Smtp-Source: AGHT+IFBahWe3Uu5E24vwvnLnnaMBQ46giWqWuuS9QY59aOznGeeKC+guR/hi7yKGQb+39Ze5HEw7g== X-Received: by 2002:a17:903:124b:b0:1d3:34cb:2324 with SMTP id u11-20020a170903124b00b001d334cb2324mr8852629plh.88.1703002148804; Tue, 19 Dec 2023 08:09:08 -0800 (PST) Received: from localhost ([12.44.203.122]) by smtp.gmail.com with ESMTPSA id k10-20020a170902694a00b001cca8a01e68sm21131791plt.278.2023.12.19.08.09.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 19 Dec 2023 08:09:08 -0800 (PST) Date: Tue, 19 Dec 2023 08:09:08 -0800 (PST) X-Google-Original-Date: Tue, 19 Dec 2023 08:09:06 PST (-0800) Subject: Re: [PATCH v2] RISC-V: Supports RISC-V Profiles in '-march' option. In-Reply-To: <20231212120809.13996-1-jiawei@iscas.ac.cn> CC: gcc-patches@gcc.gnu.org, kito.cheng@sifive.com, jeffreyalaw@gmail.com, christoph.muellner@vrull.eu, jiawei@iscas.ac.cn From: Palmer Dabbelt To: jiawei@iscas.ac.cn Message-ID: Mime-Version: 1.0 (MHng) Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 8bit X-Spam-Status: No, score=-10.2 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,GIT_PATCH_0,KAM_SHORT,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,TXREP,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: On Tue, 12 Dec 2023 04:08:09 PST (-0800), jiawei@iscas.ac.cn wrote: > Supports RISC-V profiles[1] in -march option. > > Default input set the profile is before other formal extensions. > > V2: Fixes some format errors and adds code comments for parse function > Thanks for Jeff Law's review and comments. > > [1]https://github.com/riscv/riscv-profiles/blob/main/profiles.adoc IMO we should wait on the profiles. They're all minor releases so it's not like there's any value for users. Between the churn still in profiles and all these barely-defined extensions this all looks to have been very rushed, and I just don't trust RISC-V's stance on compatibility enough to try and support this sort of thing -- we've gotten burned enough times trying to do that. > gcc/ChangeLog: > > * common/config/riscv/riscv-common.cc (struct riscv_profiles): > New struct. > (riscv_subset_list::parse_profiles): New function. > (riscv_subset_list::parse): New table. > * config/riscv/riscv-subset.h: New protype. > > gcc/testsuite/ChangeLog: > > * gcc.target/riscv/arch-31.c: New test. > * gcc.target/riscv/arch-32.c: New test. > * gcc.target/riscv/arch-33.c: New test. > * gcc.target/riscv/arch-34.c: New test. > > --- > gcc/common/config/riscv/riscv-common.cc | 83 +++++++++++++++++++++++- > gcc/config/riscv/riscv-subset.h | 2 + > gcc/testsuite/gcc.target/riscv/arch-31.c | 5 ++ > gcc/testsuite/gcc.target/riscv/arch-32.c | 5 ++ > gcc/testsuite/gcc.target/riscv/arch-33.c | 5 ++ > gcc/testsuite/gcc.target/riscv/arch-34.c | 7 ++ > 6 files changed, 106 insertions(+), 1 deletion(-) > create mode 100644 gcc/testsuite/gcc.target/riscv/arch-31.c > create mode 100644 gcc/testsuite/gcc.target/riscv/arch-32.c > create mode 100644 gcc/testsuite/gcc.target/riscv/arch-33.c > create mode 100644 gcc/testsuite/gcc.target/riscv/arch-34.c > > diff --git a/gcc/common/config/riscv/riscv-common.cc b/gcc/common/config/riscv/riscv-common.cc > index 4d5a2f874a2..8b674a4a280 100644 > --- a/gcc/common/config/riscv/riscv-common.cc > +++ b/gcc/common/config/riscv/riscv-common.cc > @@ -195,6 +195,12 @@ struct riscv_ext_version > int minor_version; > }; > > +struct riscv_profiles > +{ > + const char *profile_name; > + const char *profile_string; > +}; > + > /* All standard extensions defined in all supported ISA spec. */ > static const struct riscv_ext_version riscv_ext_version_table[] = > { > @@ -379,6 +385,42 @@ static const struct riscv_ext_version riscv_combine_info[] = > {NULL, ISA_SPEC_CLASS_NONE, 0, 0} > }; > > +/* This table records the mapping form RISC-V Profiles into march string. */ > +static const riscv_profiles riscv_profiles_table[] = > +{ > + /* RVI20U only contains the base extesnion 'i' as mandatory extension. */ > + {"RVI20U64", "rv64i"}, > + {"RVI20U32", "rv32i"}, > + > + /* RVA20U contains the 'i,m,a,f,d,c,zicsr' as mandatory extensions. > + Currently we don't have zicntr,ziccif,ziccrse,ziccamoa, > + zicclsm,za128rs yet. */ > + {"RVA20U64", "rv64imafdc_zicsr"}, > + > + /* RVA20S64 mandatory include all the extensions in RVA20U64 and > + additonal 'zifencei' as mandatory extensions. > + Notes that ss1p11, svbare, sv39, svade, sscptr, ssvecd, sstvala should > + control by binutils. */ > + {"RVA20S64", "rv64imafdc_zicsr_zifencei"}, > + > + /* RVA22U contains the 'i,m,a,f,d,c,zicsr,zihintpause,zba,zbb,zbs, > + zicbom,zicbop,zicboz,zfhmin,zkt' as mandatory extensions. > + Currently we don't have zicntr,zihpm,ziccif,ziccrse,ziccamoa, > + zicclsm,zic64b,za64rs yet. */ > + {"RVA22U64", "rv64imafdc_zicsr_zihintpause_zba_zbb_zbs" \ > + "_zicbom_zicbop_zicboz_zfhmin_zkt"}, > + > + /* RVA22S64 mandatory include all the extensions in RVA22U64 and > + additonal 'zifencei,svpbmt,svinval' as mandatory extensions. > + Notes that ss1p12, svbare, sv39, svade, sscptr, ssvecd, sstvala, > + scounterenw extentions should control by binutils. */ > + {"RVA22S64","rv64imafdc_zicsr_zifencei_zihintpause" \ > + "_zba_zbb_zbs_zicbom_zicbop_zicboz_zfhmin_zkt_svpbmt_svinval"}, > + > + /* Terminate the list. */ > + {NULL, NULL} > +}; > + > static const riscv_cpu_info riscv_cpu_tables[] = > { > #define RISCV_CORE(CORE_NAME, ARCH, TUNE) \ > @@ -958,6 +1000,42 @@ riscv_subset_list::parsing_subset_version (const char *ext, > return p; > } > > +/* Parsing RISC-V Profiles in -march string. > + Return string with mandatory extensions of Profiles. */ > +const char * > +riscv_subset_list::parse_profiles (const char * p){ > + /* Checking if input string contains a Profiles. > + There are two cases use Proifles in -march option > + > + 1. Only use Proifles as -march input > + 2. Mixed Profiles with other extensions > + > + use '+' to split Profiles and other extension. */ > + for (int i = 0; riscv_profiles_table[i].profile_name != NULL; ++i) { > + const char* match = strstr(p, riscv_profiles_table[i].profile_name); > + const char* plus_ext = strchr(p, '+'); > + /* Find profile at the begin. */ > + if (match != NULL && match == p) { > + /* If there's no '+' sign, return the profile_string directly. */ > + if(!plus_ext) > + return riscv_profiles_table[i].profile_string; > + /* If there's a '+' sign, need to add profiles with other ext. */ > + else { > + size_t arch_len = strlen(riscv_profiles_table[i].profile_string)+ > + strlen(plus_ext); > + /* Reset the input string with Profiles mandatory extensions, > + end with '_' to connect other additional extensions. */ > + static char* result = new char[arch_len + 2]; > + strcpy(result, riscv_profiles_table[i].profile_string); > + strcat(result, "_"); > + strcat(result, plus_ext + 1); /* skip the '+'. */ > + return result; > + } > + } > + } > + return p; > +} > + > /* Parsing function for standard extensions. > > Return Value: > @@ -1486,7 +1564,10 @@ riscv_subset_list::parse (const char *arch, location_t loc) > > riscv_subset_list *subset_list = new riscv_subset_list (arch, loc); > riscv_subset_t *itr; > + > const char *p = arch; > + p = subset_list->parse_profiles(p); > + > if (startswith (p, "rv32")) > { > subset_list->m_xlen = 32; > @@ -1499,7 +1580,7 @@ riscv_subset_list::parse (const char *arch, location_t loc) > } > else > { > - error_at (loc, "%<-march=%s%>: ISA string must begin with rv32 or rv64", > + error_at (loc, "%<-march=%s%>: ISA string must begin with rv32, rv64 or a profile", > arch); > goto fail; > } > diff --git a/gcc/config/riscv/riscv-subset.h b/gcc/config/riscv/riscv-subset.h > index ad1cab2aa24..ba991f67014 100644 > --- a/gcc/config/riscv/riscv-subset.h > +++ b/gcc/config/riscv/riscv-subset.h > @@ -76,6 +76,8 @@ private: > const char *parse_single_multiletter_ext (const char *, const char *, > const char *); > > + const char *parse_profiles (const char*); > + > void handle_implied_ext (const char *); > bool check_implied_ext (); > void handle_combine_ext (); > diff --git a/gcc/testsuite/gcc.target/riscv/arch-31.c b/gcc/testsuite/gcc.target/riscv/arch-31.c > new file mode 100644 > index 00000000000..eb24abe4153 > --- /dev/null > +++ b/gcc/testsuite/gcc.target/riscv/arch-31.c > @@ -0,0 +1,5 @@ > +/* { dg-do compile } */ > +/* { dg-options "-march=RVI20U64 -mabi=lp64" } */ > +int foo() > +{ > +} > diff --git a/gcc/testsuite/gcc.target/riscv/arch-32.c b/gcc/testsuite/gcc.target/riscv/arch-32.c > new file mode 100644 > index 00000000000..bc556a3e717 > --- /dev/null > +++ b/gcc/testsuite/gcc.target/riscv/arch-32.c > @@ -0,0 +1,5 @@ > +/* { dg-do compile } */ > +/* { dg-options "-march=RVI20U64+mafdc -mabi=lp64d" } */ > +int foo() > +{ > +} > diff --git a/gcc/testsuite/gcc.target/riscv/arch-33.c b/gcc/testsuite/gcc.target/riscv/arch-33.c > new file mode 100644 > index 00000000000..a7b80a5ad43 > --- /dev/null > +++ b/gcc/testsuite/gcc.target/riscv/arch-33.c > @@ -0,0 +1,5 @@ > +/* { dg-do compile } */ > +/* { dg-options "-march=RVA22S64 -mabi=lp64d" } */ > +int foo() > +{ > +} > diff --git a/gcc/testsuite/gcc.target/riscv/arch-34.c b/gcc/testsuite/gcc.target/riscv/arch-34.c > new file mode 100644 > index 00000000000..d077aba4fc2 > --- /dev/null > +++ b/gcc/testsuite/gcc.target/riscv/arch-34.c > @@ -0,0 +1,7 @@ > +/* { dg-do compile } */ > +/* { dg-options "-march=rv64gcRVA22S64 -mabi=lp64d" } */ > +int foo() > +{ > +} > + > +/* { dg-error "ISA string must begin with rv32, rv64 or a profile" "" { target *-*-* } 0 } */