From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-pl1-x635.google.com (mail-pl1-x635.google.com [IPv6:2607:f8b0:4864:20::635]) by sourceware.org (Postfix) with ESMTPS id 17AF43858D35 for ; Wed, 24 May 2023 01:38:50 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 17AF43858D35 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=rivosinc.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=rivosinc.com Received: by mail-pl1-x635.google.com with SMTP id d9443c01a7336-1ae4c5e1388so3746605ad.1 for ; Tue, 23 May 2023 18:38:50 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20221208.gappssmtp.com; s=20221208; t=1684892329; x=1687484329; h=content-transfer-encoding:mime-version:message-id:to:from:cc :in-reply-to:subject:date:from:to:cc:subject:date:message-id :reply-to; bh=rfau7KzXLftsn6/2Y8MIO70Mit8v7xd1I9XZu98SRCA=; b=2bORypTUrxjO4konh67GP4TiI36eLqg8ztlZGXXC57n5X5AT4xUiSKG0qkZj1I2XFO C2SvMba2QngO8DvgAp2heHS6cpNFrA7priPvES61QRIelWxwcOpBVPU9DuM4b10LbWxg KM0WrJj6ZN3lhmYK/iy3IFIdRPS2K4+KATalFCRumSFiHsZ7VSYALLa+wVw7mtMV0rQv llvTw/U0esWlL7nOpRGWM/HJJ/B8OxDasJRvWDjxv5YXcoZHff+sQjLN3IjxPKPntZ8Q MutsnL2him7x9zSWgT8P9kCNnNCvFfd7rsJugsCclvnhzd4XyF0sNGn35hlACp5BLrLm brhA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1684892329; x=1687484329; h=content-transfer-encoding:mime-version:message-id:to:from:cc :in-reply-to:subject:date:x-gm-message-state:from:to:cc:subject:date :message-id:reply-to; bh=rfau7KzXLftsn6/2Y8MIO70Mit8v7xd1I9XZu98SRCA=; b=ZEhcseVuWnqCBaVel55jPKvzzQ4aN42gct55V7lBbBJvp0hHscfOGP/3Mk2f1nMDF3 4t0oNp/kD6lZvZyg1+VPaKmdOl+LJ+BOhm0cF/80DbQw5wVD775fNWYdezEYdDpaHOkc xExja+JC63RxCkGqOqWgr5dAAKXX8SyZ7Cvap5sZ0MjEn8U/wPWBUJe/4qV5fDtcWPBp AMabAqsGHPdDjNbhW+g8cWVI51EYYbKmp7HqljMotaj+wkatwVjxkzIH4lMObh8t3ZnH fZpcG+5fG5id1I8iNQfEWAddIuadm7hSD0C6ovGxzim6lH0tqO2XggCjF3thjIAIO/kK qL6Q== X-Gm-Message-State: AC+VfDxRCS8ZsVpNcEXWvhh+ChgT1ZhyOE1ch/Lfzfzon0nO+T+F2X6P c+np6wradOt2RQGa1KCEBZgPeFcfv/Yr8YfTJ04= X-Google-Smtp-Source: ACHHUZ7oJKxKn2n0HzqJI8aUGCyvSI2YttHT6wZi8kzcdlbu1UC8sR28erpGuu9JRQb/La/eDCL/cw== X-Received: by 2002:a17:902:d04a:b0:1ac:5b6b:df4c with SMTP id l10-20020a170902d04a00b001ac5b6bdf4cmr12799104pll.69.1684892328762; Tue, 23 May 2023 18:38:48 -0700 (PDT) Received: from localhost ([50.221.140.188]) by smtp.gmail.com with ESMTPSA id f18-20020a170902ce9200b001ae46ccd19esm7405725plg.63.2023.05.23.18.38.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 23 May 2023 18:38:48 -0700 (PDT) Date: Tue, 23 May 2023 18:38:48 -0700 (PDT) X-Google-Original-Date: Tue, 23 May 2023 18:38:23 PDT (-0700) Subject: Re: Re: [PATCH V2] RISC-V: Fix magic number of RVV auto-vectorization expander In-Reply-To: <144D08A81764AA5D+20230524093738744453181@rivai.ai> CC: gcc-patches@gcc.gnu.org, Kito Cheng , kito.cheng@sifive.com, jeffreyalaw@gmail.com, rdapp.gcc@gmail.com From: Palmer Dabbelt To: juzhe.zhong@rivai.ai Message-ID: Mime-Version: 1.0 (MHng) Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 8bit X-Spam-Status: No, score=-10.5 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,GIT_PATCH_0,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,TXREP,T_SCC_BODY_TEXT_LINE,URIBL_BLACK autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: On Tue, 23 May 2023 18:37:39 PDT (-0700), juzhe.zhong@rivai.ai wrote: > Yes, I built it and regression has passed. OK, thanks! > > > > juzhe.zhong@rivai.ai > > From: Palmer Dabbelt > Date: 2023-05-24 09:37 > To: juzhe.zhong > CC: gcc-patches; Kito Cheng; kito.cheng; jeffreyalaw; rdapp.gcc > Subject: Re: Re: [PATCH V2] RISC-V: Fix magic number of RVV auto-vectorization expander > On Tue, 23 May 2023 18:34:00 PDT (-0700), juzhe.zhong@rivai.ai wrote: >> Yeah. Can I merge it? > > You built it? Then I'm fine with merging it. > >> >> >> >> juzhe.zhong@rivai.ai >> >> From: Palmer Dabbelt >> Date: 2023-05-24 09:32 >> To: juzhe.zhong >> CC: gcc-patches; Kito Cheng; kito.cheng; jeffreyalaw; rdapp.gcc; juzhe.zhong >> Subject: Re: [PATCH V2] RISC-V: Fix magic number of RVV auto-vectorization expander >> On Tue, 23 May 2023 18:28:48 PDT (-0700), juzhe.zhong@rivai.ai wrote: >>> From: Juzhe-Zhong >>> >>> This simple patch fixes the magic number, remove magic number make codes more reasonable. >>> >>> Ok for trunk ? >>> >>> gcc/ChangeLog: >>> >>> * config/riscv/riscv-v.cc (expand_vec_series): Remove magic number. >>> (expand_const_vector): Ditto. >>> (legitimize_move): Ditto. >>> (sew64_scalar_helper): Ditto. >>> (expand_tuple_move): Ditto. >>> (expand_vector_init_insert_elems): Ditto. >>> * config/riscv/riscv.cc (vector_zero_call_used_regs): Ditto. >>> >>> --- >>> gcc/config/riscv/riscv-v.cc | 53 +++++++++++++++++-------------------- >>> gcc/config/riscv/riscv.cc | 2 +- >>> 2 files changed, 26 insertions(+), 29 deletions(-) >>> >>> diff --git a/gcc/config/riscv/riscv-v.cc b/gcc/config/riscv/riscv-v.cc >>> index 478a052a779..fa61a850a22 100644 >>> --- a/gcc/config/riscv/riscv-v.cc >>> +++ b/gcc/config/riscv/riscv-v.cc >>> @@ -406,14 +406,14 @@ expand_vec_series (rtx dest, rtx base, rtx step) >>> int shift = exact_log2 (INTVAL (step)); >>> rtx shift_amount = gen_int_mode (shift, Pmode); >>> insn_code icode = code_for_pred_scalar (ASHIFT, mode); >>> - rtx ops[3] = {step_adj, vid, shift_amount}; >>> - emit_vlmax_insn (icode, riscv_vector::RVV_BINOP, ops); >>> + rtx ops[] = {step_adj, vid, shift_amount}; >>> + emit_vlmax_insn (icode, RVV_BINOP, ops); >> >> Looks like it also removes the "riscv_vector" namespace from some of the >> constants? No big deal, it's just a different cleanup (assuming it >> still builds and such). >> >>> } >>> else >>> { >>> insn_code icode = code_for_pred_scalar (MULT, mode); >>> - rtx ops[3] = {step_adj, vid, step}; >>> - emit_vlmax_insn (icode, riscv_vector::RVV_BINOP, ops); >>> + rtx ops[] = {step_adj, vid, step}; >>> + emit_vlmax_insn (icode, RVV_BINOP, ops); >>> } >>> } >>> >>> @@ -428,8 +428,8 @@ expand_vec_series (rtx dest, rtx base, rtx step) >>> { >>> rtx result = gen_reg_rtx (mode); >>> insn_code icode = code_for_pred_scalar (PLUS, mode); >>> - rtx ops[3] = {result, step_adj, base}; >>> - emit_vlmax_insn (icode, riscv_vector::RVV_BINOP, ops); >>> + rtx ops[] = {result, step_adj, base}; >>> + emit_vlmax_insn (icode, RVV_BINOP, ops); >>> emit_move_insn (dest, result); >>> } >>> } >>> @@ -445,8 +445,8 @@ expand_const_vector (rtx target, rtx src) >>> gcc_assert ( >>> const_vec_duplicate_p (src, &elt) >>> && (rtx_equal_p (elt, const0_rtx) || rtx_equal_p (elt, const1_rtx))); >>> - rtx ops[2] = {target, src}; >>> - emit_vlmax_insn (code_for_pred_mov (mode), riscv_vector::RVV_UNOP, ops); >>> + rtx ops[] = {target, src}; >>> + emit_vlmax_insn (code_for_pred_mov (mode), RVV_UNOP, ops); >>> return; >>> } >>> >>> @@ -458,16 +458,14 @@ expand_const_vector (rtx target, rtx src) >>> we use vmv.v.i instruction. */ >>> if (satisfies_constraint_vi (src) || satisfies_constraint_Wc0 (src)) >>> { >>> - rtx ops[2] = {tmp, src}; >>> - emit_vlmax_insn (code_for_pred_mov (mode), riscv_vector::RVV_UNOP, >>> - ops); >>> + rtx ops[] = {tmp, src}; >>> + emit_vlmax_insn (code_for_pred_mov (mode), RVV_UNOP, ops); >>> } >>> else >>> { >>> elt = force_reg (elt_mode, elt); >>> - rtx ops[2] = {tmp, elt}; >>> - emit_vlmax_insn (code_for_pred_broadcast (mode), >>> - riscv_vector::RVV_UNOP, ops); >>> + rtx ops[] = {tmp, elt}; >>> + emit_vlmax_insn (code_for_pred_broadcast (mode), RVV_UNOP, ops); >>> } >>> >>> if (tmp != target) >>> @@ -536,9 +534,8 @@ legitimize_move (rtx dest, rtx src) >>> rtx tmp = gen_reg_rtx (mode); >>> if (MEM_P (src)) >>> { >>> - rtx ops[2] = {tmp, src}; >>> - emit_vlmax_insn (code_for_pred_mov (mode), riscv_vector::RVV_UNOP, >>> - ops); >>> + rtx ops[] = {tmp, src}; >>> + emit_vlmax_insn (code_for_pred_mov (mode), RVV_UNOP, ops); >>> } >>> else >>> emit_move_insn (tmp, src); >>> @@ -548,8 +545,8 @@ legitimize_move (rtx dest, rtx src) >>> if (satisfies_constraint_vu (src)) >>> return false; >>> >>> - rtx ops[2] = {dest, src}; >>> - emit_vlmax_insn (code_for_pred_mov (mode), riscv_vector::RVV_UNOP, ops); >>> + rtx ops[] = {dest, src}; >>> + emit_vlmax_insn (code_for_pred_mov (mode), RVV_UNOP, ops); >>> return true; >>> } >>> >>> @@ -813,7 +810,7 @@ sew64_scalar_helper (rtx *operands, rtx *scalar_op, rtx vl, >>> *scalar_op = force_reg (scalar_mode, *scalar_op); >>> >>> rtx tmp = gen_reg_rtx (vector_mode); >>> - rtx ops[3] = {tmp, *scalar_op, vl}; >>> + rtx ops[] = {tmp, *scalar_op, vl}; >>> riscv_vector::emit_nonvlmax_insn (code_for_pred_broadcast (vector_mode), >>> riscv_vector::RVV_UNOP, ops); >>> emit_vector_func (operands, tmp); >>> @@ -1122,9 +1119,9 @@ expand_tuple_move (rtx *ops) >>> >>> if (fractional_p) >>> { >>> - rtx operands[3] = {subreg, mem, ops[4]}; >>> - emit_vlmax_insn (code_for_pred_mov (subpart_mode), >>> - riscv_vector::RVV_UNOP, operands); >>> + rtx operands[] = {subreg, mem, ops[4]}; >>> + emit_vlmax_insn (code_for_pred_mov (subpart_mode), RVV_UNOP, >>> + operands); >>> } >>> else >>> emit_move_insn (subreg, mem); >>> @@ -1147,9 +1144,9 @@ expand_tuple_move (rtx *ops) >>> >>> if (fractional_p) >>> { >>> - rtx operands[3] = {mem, subreg, ops[4]}; >>> - emit_vlmax_insn (code_for_pred_mov (subpart_mode), >>> - riscv_vector::RVV_UNOP, operands); >>> + rtx operands[] = {mem, subreg, ops[4]}; >>> + emit_vlmax_insn (code_for_pred_mov (subpart_mode), RVV_UNOP, >>> + operands); >>> } >>> else >>> emit_move_insn (mem, subreg); >>> @@ -1281,8 +1278,8 @@ expand_vector_init_insert_elems (rtx target, const rvv_builder &builder, >>> unsigned int unspec >>> = FLOAT_MODE_P (mode) ? UNSPEC_VFSLIDE1DOWN : UNSPEC_VSLIDE1DOWN; >>> insn_code icode = code_for_pred_slide (unspec, mode); >>> - rtx ops[3] = {target, target, builder.elt (i)}; >>> - emit_vlmax_insn (icode, riscv_vector::RVV_BINOP, ops); >>> + rtx ops[] = {target, target, builder.elt (i)}; >>> + emit_vlmax_insn (icode, RVV_BINOP, ops); >>> } >>> } >>> >>> diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc >>> index e7300b2e97c..09fc9e5d95e 100644 >>> --- a/gcc/config/riscv/riscv.cc >>> +++ b/gcc/config/riscv/riscv.cc >>> @@ -7396,7 +7396,7 @@ vector_zero_call_used_regs (HARD_REG_SET need_zeroed_hardregs) >>> emitted_vlmax_vsetvl = true; >>> } >>> >>> - rtx ops[3] = {target, CONST0_RTX (mode), vl}; >>> + rtx ops[] = {target, CONST0_RTX (mode), vl}; >>> riscv_vector::emit_vlmax_insn (code_for_pred_mov (mode), >>> riscv_vector::RVV_UNOP, ops); >> >> Reviewed-by: Palmer Dabbelt >> >> as both cleanups look better to me. Thanks! >> >