From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-pj1-x102e.google.com (mail-pj1-x102e.google.com [IPv6:2607:f8b0:4864:20::102e]) by sourceware.org (Postfix) with ESMTPS id 35EB6384F6DC for ; Fri, 18 Nov 2022 04:58:54 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 35EB6384F6DC Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=dabbelt.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=dabbelt.com Received: by mail-pj1-x102e.google.com with SMTP id r61-20020a17090a43c300b00212f4e9cccdso7273801pjg.5 for ; Thu, 17 Nov 2022 20:58:54 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=dabbelt-com.20210112.gappssmtp.com; s=20210112; h=content-transfer-encoding:mime-version:message-id:to:from:cc :in-reply-to:subject:date:from:to:cc:subject:date:message-id :reply-to; bh=5SWBaAaJFqNuxskEobGPB0g/KH40DiXhncWKMLwQWuQ=; b=J3bRxTsVhYQ6g7uWiW16mI7FR0uJbunQ5lPoVxik66fe9Y+dCbxVYhBKwGxXTCPCcS zOceK9rJzEiKuEHRv6ffk0KEV4Feik82b63JM5xzxsXCOj7+CLgg0uCCPzgqr5hreChV UKzdCMsHFNVFJYHybjflHYP+PSvmp+dZxVkUKQ/H0KdRMZRX31S5UpAYrVcG98xG1OIY yy2x5cEXXHTGhNeiipzmtYWIzrjzMuIllGHr1YUP80dd2MDR83++XZ+9nZ8RtV8XHLXc Aeeh1G/D62tVUTJYG1jpLu98uaptxPtrZTOJuVLwBVJEu57buEnSwUGOB8/aMq/BXRGX hJRA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:message-id:to:from:cc :in-reply-to:subject:date:x-gm-message-state:from:to:cc:subject:date :message-id:reply-to; bh=5SWBaAaJFqNuxskEobGPB0g/KH40DiXhncWKMLwQWuQ=; b=St/u1I8DMd6BmcQPrCa6ujcDxx76JoIbEB3VbnactUrybp+4L4r9Q9kDCSG7imB0wS zYQ2Qbd0ogau0PIqALQQhHieBfFHejxHGO+n2LqgQZUU7zuME3BB18bAp0QRH5rBbFZ7 E/8wuWf6CCwhqPFqvmty76pXc+0LF0ZhUoAAE73O5CgIRnVWqhENktcAqleopHzWpu7b TL1TZRDn8aslyELbceJ+xqRkDglJWul7t8+v/Jyl3fO1vxKXRcfjqrHKRQrb8FxSWGIv fiiOMaclLed3quv4Zj3/WBVQVhPQreyoLrzEQHGkUd6ndN59C6Kz9Rz6vqg808i2f8Jg Zs5A== X-Gm-Message-State: ANoB5pl/F/gNWxWHMp5kpzZSS1xBbHeXQke/eXmhW1FVrgGIbumiecYr Bxre7/5KRSebdx0FJCEGLQ03aw== X-Google-Smtp-Source: AA0mqf6u4LPsHMfkvDTT9Ep9tqmvjzqgiRPuyoVs/cOjuGDZwg3+xKHo5MF8+kEDn4eACCZ3gzG0Mg== X-Received: by 2002:a17:902:9b89:b0:186:b46d:da5e with SMTP id y9-20020a1709029b8900b00186b46dda5emr6028035plp.92.1668747532940; Thu, 17 Nov 2022 20:58:52 -0800 (PST) Received: from localhost ([50.221.140.188]) by smtp.gmail.com with ESMTPSA id u7-20020a17090341c700b0017f74cab9eesm2410592ple.128.2022.11.17.20.58.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 17 Nov 2022 20:58:52 -0800 (PST) Date: Thu, 17 Nov 2022 20:58:52 -0800 (PST) X-Google-Original-Date: Thu, 17 Nov 2022 20:58:47 PST (-0800) Subject: Re: [PATCH 2/7] riscv: riscv-cores.def: Add T-Head XuanTie C906 In-Reply-To: <20221118045019.GC12452@L-PF1ZESZG-1136.hz.ali.com> CC: christoph.muellner@vrull.eu, gcc-patches@gcc.gnu.org From: Palmer Dabbelt To: gcc-patches@gcc.gnu.org Message-ID: Mime-Version: 1.0 (MHng) Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 8bit X-Spam-Status: No, score=-10.6 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,GIT_PATCH_0,KAM_NUMSUBJECT,KAM_SHORT,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: On Thu, 17 Nov 2022 20:50:19 PST (-0800), gcc-patches@gcc.gnu.org wrote: > On Sun, Nov 13, 2022 at 10:46:31PM +0100, Christoph Muellner wrote: >> From: Christoph Müllner >> >> This adds T-Head's XuanTie C906 to the list of known cores as "thead-c906". >> The C906 is shipped for quite some time (it is the core of the Allwinner D1). >> Note, that the tuning struct for the C906 is already part of GCC (it is >> also name "thead-c906"). >> >> gcc/ChangeLog: >> >> * config/riscv/riscv-cores.def (RISCV_CORE): Add "thead-c906". >> >> gcc/testsuite/ChangeLog: >> >> * gcc.target/riscv/mcpu-thead-c906.c: New test. >> >> Signed-off-by: Christoph Müllner >> --- >> gcc/config/riscv/riscv-cores.def | 2 ++ >> .../gcc.target/riscv/mcpu-thead-c906.c | 18 ++++++++++++++++++ >> 2 files changed, 20 insertions(+) >> create mode 100644 gcc/testsuite/gcc.target/riscv/mcpu-thead-c906.c >> >> diff --git a/gcc/config/riscv/riscv-cores.def b/gcc/config/riscv/riscv-cores.def >> index 31ad34682c5..648a010e09b 100644 >> --- a/gcc/config/riscv/riscv-cores.def >> +++ b/gcc/config/riscv/riscv-cores.def >> @@ -73,4 +73,6 @@ RISCV_CORE("sifive-s76", "rv64imafdc", "sifive-7-series") >> RISCV_CORE("sifive-u54", "rv64imafdc", "sifive-5-series") >> RISCV_CORE("sifive-u74", "rv64imafdc", "sifive-7-series") >> >> +RISCV_CORE("thead-c906", "rv64imafdc", "thead-c906") >> + > > I think it makes more sense that thead-906 includes extended instructions by default. Seems reasonable to me, but Kito understands this stuff better than I do. IMO `-mtune=thead-c906` should leave the ISA targets alone and just set the tune info, and `-mcpu=thead-c906` should do that and also set the ISA to whatever's implemented on that core. That said, I was playing around with some B-extension multilib stuff recently and am pretty sure this stuff is all a bit broken. Maybe we should punt on enabling all these extensions for `-mcpu` until we have that sorted out? IMO we're at the point where having ISA-dependent multilib paths on Linux makes sense, but that risks throwing another wrench into distro folks. Maybe it doesn't matter, though? IIUC distros aren't shipping multilib right now so the bugs won't manifest for users.