From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-pj1-x1032.google.com (mail-pj1-x1032.google.com [IPv6:2607:f8b0:4864:20::1032]) by sourceware.org (Postfix) with ESMTPS id CF3F93858C2D for ; Mon, 17 Apr 2023 19:26:29 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org CF3F93858C2D Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=rivosinc.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=rivosinc.com Received: by mail-pj1-x1032.google.com with SMTP id k65-20020a17090a3ec700b00247131783f7so95776pjc.0 for ; Mon, 17 Apr 2023 12:26:29 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20221208.gappssmtp.com; s=20221208; t=1681759588; x=1684351588; h=content-transfer-encoding:mime-version:message-id:to:from:cc :in-reply-to:subject:date:from:to:cc:subject:date:message-id :reply-to; bh=cpGNmeLcW73Tw8KbaGz/lBRdZji/wgR4wwN9yE4jr8g=; b=Euvg6o45VTj6LLVJNmWZ5sc1hsQjyJihEYmZPJJam4vx6RTsbvXEuvn7kTWq9urhyW Zw+XwFc83Pm2fFN3Qct2GBCWxcBoMaxlf6kW2VL4DxW9GAiRjg+Tf784aBgbiKwPNFqa ckyJ94TQFtXiTqI7vfw0QJRIDG/2YZCpIuW4yedLfrh6qWaKSl1UEIvs6NKCNAwxNd48 CUd2gxxb9Dl4KOKXmLwELkGLyOndliIVzp2Uni6FQ+oNKXqnr9XjhYAmoF8xnqPtZ0+B p959M2tKIbMnTmNkQfsX2WAEzSAXvrEuHDymhPpsRaeh4t5lElg1mZ9FGCZ3SKPzDLnE NYEw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1681759588; x=1684351588; h=content-transfer-encoding:mime-version:message-id:to:from:cc :in-reply-to:subject:date:x-gm-message-state:from:to:cc:subject:date :message-id:reply-to; bh=cpGNmeLcW73Tw8KbaGz/lBRdZji/wgR4wwN9yE4jr8g=; b=a31PuBIwUCXLUMajpI7l5LWktQyRqugf7zi5iPnc2/84Ui6L+XXnTHNJNotlEeFa67 3uHiHNUQufvMPqQUkLo9EyGcuZVAQbhQ8kUN3woZ9BAqPX+JOqjKjsjLHbMCHgx3Uhaz WuQYfqLWeHvaTe419yQbEbcfvSEmhyPPRxVHza7cTvus/w4ytMXRTJr+U3gfnnBb2vgO hgBSGt7wVZ6IKZm2QMEBcq3BW3Io733a9JeQZyYe4EkgfhvrIrNmplyfzoqmoeoZPmsD OM103kiBH4flB+Tqk13C4BHOprFaESiAJvTY8HPBkcjAUn25kwPWaQ5XEEgc7zSs/7m3 1fKA== X-Gm-Message-State: AAQBX9ftcP9toEXFgHDq0sbQ+WhYNhe1v3z29L9MFpQsyIMU3AI2Kk60 qSWPMKhwU834sXa9S6O3gjWC5b20sLbM18YpWrw= X-Google-Smtp-Source: AKy350bqC8oSqlmoKhNheVKaUy75XWBqHyQ9q6qfASICbD7erZGjXlNw0TyAlFpaeOYSJM949Qc9dA== X-Received: by 2002:a17:902:dacf:b0:1a1:a727:a802 with SMTP id q15-20020a170902dacf00b001a1a727a802mr15085096plx.19.1681759588317; Mon, 17 Apr 2023 12:26:28 -0700 (PDT) Received: from localhost ([50.221.140.188]) by smtp.gmail.com with ESMTPSA id ev7-20020a17090aeac700b00246b1b4a3ffsm7341086pjb.0.2023.04.17.12.26.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 17 Apr 2023 12:26:27 -0700 (PDT) Date: Mon, 17 Apr 2023 12:26:27 -0700 (PDT) X-Google-Original-Date: Mon, 17 Apr 2023 12:26:16 PDT (-0700) Subject: Re: [PATCH v4 00/10] RISC-V: Add autovec support In-Reply-To: <20230417183701.2249183-1-collison@rivosinc.com> CC: gcc-patches@gcc.gnu.org From: Palmer Dabbelt To: collison@rivosinc.com Message-ID: Mime-Version: 1.0 (MHng) Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 8bit X-Spam-Status: No, score=-5.5 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,KAM_SHORT,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,TXREP,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: On Mon, 17 Apr 2023 11:36:51 PDT (-0700), collison@rivosinc.com wrote: > This series of patches adds foundational support for RISC-V auto-vectorization support. These patches are based on the current upstream rvv vector intrinsic support and is not a new implementation. Most of the implementation consists of adding the new vector cost model, the autovectorization patterns themselves and target hooks. This implementation only provides support for integer addition and subtraction as a proof of concept. This patch set should not be construed to be feature complete. Based on conversations with the community these patches are intended to lay the groundwork for feature completion and collaboration within the RISC-V community. > > These patches are largely based off the work of Juzhe Zhong (juzhe.zhong@rivai.ai) of RiVAI. More specifically the rvv-next branch at: https://github.com/riscv-collab/riscv-gcc.git is the foundation of this patch set. > > As discussed on this list, if these patches are approved they will be merged into a "auto-vectorization" branch once gcc-13 branches for release. There are two known issues related to crashes (assert failures) associated with tree vectorization; one of which I have sent a patch for and have received feedback. > > Changes in v4: > > - Added support for binary integer operations and test cases > - Fixed bug to support 8-bit integer vectorization > - Fixed several assert errors related to non-multiple of two vector modes > > Changes in v3: > > - Removed the cost model and cost hooks based on feedback from Richard Biener > - Used RVV_VUNDEF macro to fix failing patterns > > Changes in v2 > > - Updated ChangeLog entry to include RiVAI contributions > - Fixed ChangeLog email formatting > - Fixed gnu formatting issues in the code > > Kevin Lee (2): > This patch adds a guard for VNx1 vectors that are present in ports > like riscv. > This patch supports 8 bit auto-vectorization in riscv. > > Michael Collison (8): > RISC-V: Add new predicates and function prototypes > RISC-V: autovec: Export policy functions to global scope > RISC-V:autovec: Add auto-vectorization support functions > RISC-V:autovec: Add target vectorization hooks > RISC-V:autovec: Add autovectorization patterns for binary integer > operations > RISC-V:autovec: Add autovectorization tests for add & sub > vect: Verify that GET_MODE_NUNITS is a multiple of 2. > RISC-V:autovec: Add autovectorization tests for binary integer > > gcc/config/riscv/predicates.md | 13 ++ > gcc/config/riscv/riscv-opts.h | 40 ++++ > gcc/config/riscv/riscv-protos.h | 14 ++ > gcc/config/riscv/riscv-v.cc | 176 ++++++++++++++++++ > gcc/config/riscv/riscv-vector-builtins.cc | 4 +- > gcc/config/riscv/riscv-vector-builtins.h | 3 + > gcc/config/riscv/riscv.cc | 157 ++++++++++++++++ > gcc/config/riscv/riscv.md | 1 + > gcc/config/riscv/riscv.opt | 20 ++ > gcc/config/riscv/vector-auto.md | 79 ++++++++ > gcc/config/riscv/vector-iterators.md | 2 + > gcc/config/riscv/vector.md | 4 +- > .../riscv/rvv/autovec/loop-add-rv32.c | 25 +++ > .../gcc.target/riscv/rvv/autovec/loop-add.c | 25 +++ > .../riscv/rvv/autovec/loop-and-rv32.c | 25 +++ > .../gcc.target/riscv/rvv/autovec/loop-and.c | 25 +++ > .../riscv/rvv/autovec/loop-div-rv32.c | 27 +++ > .../gcc.target/riscv/rvv/autovec/loop-div.c | 27 +++ > .../riscv/rvv/autovec/loop-max-rv32.c | 26 +++ > .../gcc.target/riscv/rvv/autovec/loop-max.c | 26 +++ > .../riscv/rvv/autovec/loop-min-rv32.c | 26 +++ > .../gcc.target/riscv/rvv/autovec/loop-min.c | 26 +++ > .../riscv/rvv/autovec/loop-mod-rv32.c | 27 +++ > .../gcc.target/riscv/rvv/autovec/loop-mod.c | 27 +++ > .../riscv/rvv/autovec/loop-mul-rv32.c | 25 +++ > .../gcc.target/riscv/rvv/autovec/loop-mul.c | 25 +++ > .../riscv/rvv/autovec/loop-or-rv32.c | 25 +++ > .../gcc.target/riscv/rvv/autovec/loop-or.c | 25 +++ > .../riscv/rvv/autovec/loop-sub-rv32.c | 25 +++ > .../gcc.target/riscv/rvv/autovec/loop-sub.c | 25 +++ > .../riscv/rvv/autovec/loop-xor-rv32.c | 25 +++ > .../gcc.target/riscv/rvv/autovec/loop-xor.c | 25 +++ > gcc/testsuite/gcc.target/riscv/rvv/rvv.exp | 3 + > gcc/tree-vect-data-refs.cc | 2 + > gcc/tree-vect-slp.cc | 7 +- > 35 files changed, 1031 insertions(+), 6 deletions(-) > create mode 100644 gcc/config/riscv/vector-auto.md > create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-add-rv32.c > create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-add.c > create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-and-rv32.c > create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-and.c > create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-div-rv32.c > create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-div.c > create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-max-rv32.c > create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-max.c > create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-min-rv32.c > create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-min.c > create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-mod-rv32.c > create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-mod.c > create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-mul-rv32.c > create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-mul.c > create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-or-rv32.c > create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-or.c > create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-sub-rv32.c > create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-sub.c > create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-xor-rv32.c > create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-xor.c Thanks for re-spinning these. I haven't looked at the actual code yet, but I think there's still a bigger question as to which way we go here: Juzhe has talked about wanting to make some larger changes, but as per some IRC discussions at least the type widening (and possible some of the other bigger generic changes) aren't suitable for trunk yet as we're still waiting for the test failures to calm down. So I think that leaves us with the option of either taking something like this now, or waiting. I'd prefer to just get things committed to trunk so we can all work in the same place, but happy to hear if other folks have comments. I certainly don't intend on committing any of this until it's at least reviewed and folks are OK with the approach. There's still some testsuite failures to track down for 13 so no big rush on actually committing things, but a bunch of folks are spinning up on autovec now so I'd at least like to get agreement as to which direction we're headed sooner rather than later.