From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-pf1-x432.google.com (mail-pf1-x432.google.com [IPv6:2607:f8b0:4864:20::432]) by sourceware.org (Postfix) with ESMTPS id 48CE7385771A for ; Wed, 10 May 2023 19:19:06 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 48CE7385771A Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=dabbelt.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=dabbelt.com Received: by mail-pf1-x432.google.com with SMTP id d2e1a72fcca58-6439e6f5a33so4430962b3a.2 for ; Wed, 10 May 2023 12:19:06 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=dabbelt-com.20221208.gappssmtp.com; s=20221208; t=1683746345; x=1686338345; h=content-transfer-encoding:mime-version:message-id:to:from:cc :in-reply-to:subject:date:from:to:cc:subject:date:message-id :reply-to; bh=wJmIe2zzVdA0WrItpnQcCMYka5L3aGIhF3UPgM5yXUA=; b=HR6R2eiS1LEsBogO2Co3molz7jSfk13pqQn0r0Rr6a2oE2D4FTCh6aV/lw8C6W4EEj O2y4+yD/GCm4sB3AqAJHAMo1LTpdjJpbn6IKg5jO0QBMFRaKDCKSLAn33ayKvybidgYE nrl6RIc2BsH1XkK6RC7z34O90dDrx7u43SP1ejC4B0gG6X5uGfm24D2WMJF179bt4kdN bvxcEOA9FjlaFRu9VhMIonREzCn6YDokqXyazSfZfljluC1a++y4E5JN1Oe/k+u2P+RN y54jdmRtt/EQf+guLoQsA9ehUF0vLrGUnPlLGUPwjEdtbdIBIChaGNfSOKDldwaTXGaF FKoQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1683746345; x=1686338345; h=content-transfer-encoding:mime-version:message-id:to:from:cc :in-reply-to:subject:date:x-gm-message-state:from:to:cc:subject:date :message-id:reply-to; bh=wJmIe2zzVdA0WrItpnQcCMYka5L3aGIhF3UPgM5yXUA=; b=TlxX1ctE8tJCo5j+Ejj7XNSRhgqrLDVmCXOeomDVrisQ8V1MkcQ5yH5oeRkqgtljMR Du+rplNCeY4XOLmsIxnO/n8Uinscmy2JzlA7Y4j633Sq4x9UtG6sgcy4ccJQmf/0riYd ifkTZ3m1t/XK7ulYdzK983XLggmM0M7u4toiA0WSXAVsom3WjDxt5zX8+yYZhQ/SKzIK AXVFxbdMY5fNtkRYHSVe8SzyimsKFvmcskaL6QBJ5EKuQyfDIs3qmuU9Vum9YWa0o2Xq pU7D8c0lx6JBRBkvn+01ArwjNFyRWgsrlcrhV2qkkyrTgKdbfK9VVSKWLPWQ5e4Vrxi0 WITg== X-Gm-Message-State: AC+VfDyHvVbFrD0A1RIofmY9NdWL9zkBJugS77DS7Yd1S+QF3OiE22R6 LyUkS+rkoucTytC66PNfZwfZjN7LzoR6HzxKTr8= X-Google-Smtp-Source: ACHHUZ4qy2Zm17NgBuz8lBfPnAtAlULkbAGcLeZv/5tL7w1Tb6sNVqhTqCHhGtDtjqufz4JiZSIRUg== X-Received: by 2002:a05:6a21:3299:b0:100:6863:8be7 with SMTP id yt25-20020a056a21329900b0010068638be7mr14717582pzb.62.1683746341401; Wed, 10 May 2023 12:19:01 -0700 (PDT) Received: from localhost ([50.221.140.188]) by smtp.gmail.com with ESMTPSA id a14-20020a630b4e000000b0051b460fd90fsm3533282pgl.8.2023.05.10.12.19.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 10 May 2023 12:19:00 -0700 (PDT) Date: Wed, 10 May 2023 12:19:00 -0700 (PDT) X-Google-Original-Date: Wed, 10 May 2023 12:15:05 PDT (-0700) Subject: Re: [PATCH] riscv: Split off shift patterns for autovectorization. In-Reply-To: <75805840-7b6b-7194-cae1-02eea3ea181c@gmail.com> CC: gcc-patches@gcc.gnu.org, juzhe.zhong@rivai.ai, Kito Cheng , collison@rivosinc.com, jeffreyalaw@gmail.com, rdapp.gcc@gmail.com From: Palmer Dabbelt To: rdapp.gcc@gmail.com Message-ID: Mime-Version: 1.0 (MHng) Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: 8bit X-Spam-Status: No, score=-9.0 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,GIT_PATCH_0,KAM_ASCII_DIVIDERS,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,TXREP,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: On Wed, 10 May 2023 08:24:50 PDT (-0700), rdapp.gcc@gmail.com wrote: > Hi, > > this patch splits off the shift patterns of the binop patterns. > This is necessary as the scalar shifts require a Pmode operand > as shift count. To this end, a new iterator any_int_binop_no_shift > is introduced. At a later point when the binops are split up > further in commutative and non-commutative patterns (which both > do not include the shift patterns) we might not need this anymore. > > Bootstrapped and regtested. > > Regards > Robin > > -- > > gcc/ChangeLog: > > * config/riscv/autovec.md (3): Add scalar shift > pattern. > (v3): Add vector shift pattern. > * config/riscv/vector-iterators.md: New iterator. > --- > gcc/config/riscv/autovec.md | 40 +++++++++++++++++++++++++++- > gcc/config/riscv/vector-iterators.md | 4 +++ > 2 files changed, 43 insertions(+), 1 deletion(-) > > diff --git a/gcc/config/riscv/autovec.md b/gcc/config/riscv/autovec.md > index 8347e42bb9c..2da4fc67d51 100644 > --- a/gcc/config/riscv/autovec.md > +++ b/gcc/config/riscv/autovec.md > @@ -65,7 +65,7 @@ (define_expand "movmisalign" > > (define_expand "3" > [(set (match_operand:VI 0 "register_operand") > - (any_int_binop:VI > + (any_int_binop_no_shift:VI > (match_operand:VI 1 "") > (match_operand:VI 2 "")))] > "TARGET_VECTOR" > @@ -91,3 +91,41 @@ (define_expand "3" > NULL_RTX, mode); > DONE; > }) > + > +;; ========================================================================= > +;; == Binary integer shifts by scalar. > +;; ========================================================================= > + > +(define_expand "3" > + [(set (match_operand:VI 0 "register_operand") > + (any_shift:VI > + (match_operand:VI 1 "register_operand") > + (match_operand: 2 "csr_operand")))] I don't think VEL is _wrong_ here, as it's an integer type that's big enough to hold the shift amount, but we might get some odd generated code for the QI and HI flavors as we frequently don't handle the shorter types well. "csr_operand" does seem wrong, though, as that just accepts constants. Maybe "arith_operand" is the way to go? I haven't looked at the V immediates though. > + "TARGET_VECTOR" > +{ > + if (!CONST_SCALAR_INT_P (operands[2])) > + operands[2] = gen_lowpart (Pmode, operands[2]); > + riscv_vector::emit_len_binop (code_for_pred_scalar > + (, mode), > + operands[0], operands[1], operands[2], > + NULL_RTX, mode, Pmode); > + DONE; > +}) > + > +;; ========================================================================= > +;; == Binary integer shifts by vector. > +;; ========================================================================= > + > +(define_expand "v3" > + [(set (match_operand:VI 0 "register_operand") > + (any_shift:VI > + (match_operand:VI 1 "register_operand") > + (match_operand:VI 2 "vector_shift_operand")))] > + "TARGET_VECTOR" > +{ > + riscv_vector::emit_len_binop (code_for_pred > + (, mode), > + operands[0], operands[1], operands[2], > + NULL_RTX, mode); > + DONE; > +}) > diff --git a/gcc/config/riscv/vector-iterators.md b/gcc/config/riscv/vector-iterators.md > index 42848627c8c..fdb0bfbe3b1 100644 > --- a/gcc/config/riscv/vector-iterators.md > +++ b/gcc/config/riscv/vector-iterators.md > @@ -1429,6 +1429,10 @@ (define_code_iterator any_commutative_binop [plus and ior xor > > (define_code_iterator any_non_commutative_binop [minus div udiv mod umod]) > > +(define_code_iterator any_int_binop_no_shift > + [plus minus and ior xor smax umax smin umin mult div udiv mod umod > +]) > + > (define_code_iterator any_immediate_binop [plus minus and ior xor]) > > (define_code_iterator any_sat_int_binop [ss_plus ss_minus us_plus us_minus]) > -- > 2.40.0 It'd be great to have test cases for the patterns we're adding, at least for some of the stickier ones.