From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-pg1-x535.google.com (mail-pg1-x535.google.com [IPv6:2607:f8b0:4864:20::535]) by sourceware.org (Postfix) with ESMTPS id 5A7A23858D28 for ; Thu, 10 Nov 2022 01:46:30 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 5A7A23858D28 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=rivosinc.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=rivosinc.com Received: by mail-pg1-x535.google.com with SMTP id f63so355177pgc.2 for ; Wed, 09 Nov 2022 17:46:30 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20210112.gappssmtp.com; s=20210112; h=content-transfer-encoding:mime-version:message-id:to:from:cc :in-reply-to:subject:date:from:to:cc:subject:date:message-id :reply-to; bh=bL2MmovyNJitgzEV42lFI7jokE0Dz7NWY7DTm6Q7qGI=; b=Mnj741KpkxwPd+jR8ygNmX3So0/L62Mnj1nBYAjD0WSoMYHakPl2rVC5mW8CHsZdI5 wUOn6iFadxjilMbwCeFWopLoUDLxdXlwzrEBeTzjeFjza4LA6J72uVbhs4Hw4/znlV1F Hdmpsfut6KdMbhRJvBfd9QNHTgdc1Dy1AfTqGf0F7+9NiBxg+0rVPZotL6VvA1qEeUWS fEVXLLWgIbLLHM9Vhkw3Wg57KxFaAo2THrmfcYFUTDy28hqHO2EpFPoScpBI6W9A0zdE Qalbc1keaHmLJJbjw0YZs9BTVNtEMKshtlRxaxNBUPZ+mcXZ2fDZpqoDTrsE4HrB/3h4 fo8A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:message-id:to:from:cc :in-reply-to:subject:date:x-gm-message-state:from:to:cc:subject:date :message-id:reply-to; bh=bL2MmovyNJitgzEV42lFI7jokE0Dz7NWY7DTm6Q7qGI=; b=LoaiVvER6kKUM2lsHWBzMY3FXyxhXz/ItnrxDaEpslHOv0cZ3fllLTh0XYLhnPhDI0 uQcfFLhpg0t59jqHOFiiVHZMD8vcTsbdkjY1EK3DPpZHBRmdm0Kz4Lr4vwrCathJ00+o gIu0lwpOXmU9G9WOyteE4EqJU32PKAk4SbdG2VUTLeMI198GDTLlkicalSnCHDugRL+l eOysJHLCo03vpwpZMapb8kTBJcLfdEOAz9brvajFZrT/1T5334aLhD5hKfZnYNi/M3I1 nbP1EtoyZDjQ/uyeQ4tXuOJP04e9Yv5DsVD2nx+oaTVJJLsff8n5svin2EAnEhhVftEr utag== X-Gm-Message-State: ACrzQf2LNXepe+SabzbjQjW8PxrNn4jpjE0DJ4ZcZxtxMyz3rEL+O9LF zsxK0ct9nNA5wTSUnXow3PBttBhJ2QpwnQ== X-Google-Smtp-Source: AMsMyM47ULdZi5BVVNlPVrVoDa5IFcFiP3zqG9qOudYVh4Fc9K4hfh2L9mau6IFwCrTHJtwJXP4XvA== X-Received: by 2002:a63:2cd2:0:b0:41c:5901:67d8 with SMTP id s201-20020a632cd2000000b0041c590167d8mr53836050pgs.365.1668044788925; Wed, 09 Nov 2022 17:46:28 -0800 (PST) Received: from localhost ([50.221.140.188]) by smtp.gmail.com with ESMTPSA id z6-20020a623306000000b0056328e516f4sm9217503pfz.148.2022.11.09.17.46.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 09 Nov 2022 17:46:28 -0800 (PST) Date: Wed, 09 Nov 2022 17:46:28 -0800 (PST) X-Google-Original-Date: Wed, 09 Nov 2022 17:46:18 PST (-0800) Subject: Re: [PATCH] RISC-V: costs: support shift-and-add in strength-reduction In-Reply-To: <20221108195434.2701247-1-philipp.tomsich@vrull.eu> CC: gcc-patches@gcc.gnu.org, Kito Cheng , Vineet Gupta , christoph.muellner@vrull.eu, jlaw@ventanamicro.com, philipp.tomsich@vrull.eu From: Palmer Dabbelt To: philipp.tomsich@vrull.eu Message-ID: Mime-Version: 1.0 (MHng) Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 8bit X-Spam-Status: No, score=-11.9 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,GIT_PATCH_0,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: On Tue, 08 Nov 2022 11:54:34 PST (-0800), philipp.tomsich@vrull.eu wrote: > The strength-reduction implementation in expmed.c will assess the > profitability of using shift-and-add using a RTL expression that wraps > a MULT (with a power-of-2) in a PLUS. Unless the RISC-V rtx_costs > function recognizes this as expressing a sh[123]add instruction, we > will return an inflated cost---thus defeating the optimization. > > This change adds the necessary idiom recognition to provide an > accurate cost for this for of expressing sh[123]add. > > Instead on expanding to > li a5,200 > mulw a0,a5,a0 > with this change, the expression 'a * 200' is sythesized as: > sh2add a0,a0,a0 // *5 = a + 4 * a > sh2add a0,a0,a0 // *5 = a + 4 * a > slli a0,a0,3 // *8 That's more instructions, but multiplication is generally expensive. At some point I remember the SiFive cores getting very fast integer multipliers, but I don't see that reflected in the cost model anywhere so maybe I'm just wrong? Andrew or Kito might remember... If the mul-based sequences are still faster on the SiFive cores then we should probably find a way to keep emitting them, which may just be a matter of adjusting those multiply costs. Moving to the shift-based sequences seems reasonable for a generic target, though. Either way, it probably warrants a test case to make sure we don't regress in the future. > > gcc/ChangeLog: > > * config/riscv/riscv.c (riscv_rtx_costs): Recognize shNadd, > if expressed as a plus and multiplication with a power-of-2. > > --- > > gcc/config/riscv/riscv.cc | 13 +++++++++++++ > 1 file changed, 13 insertions(+) > > diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc > index ab6c745c722..0b2c4b3599d 100644 > --- a/gcc/config/riscv/riscv.cc > +++ b/gcc/config/riscv/riscv.cc > @@ -2451,6 +2451,19 @@ riscv_rtx_costs (rtx x, machine_mode mode, int outer_code, int opno ATTRIBUTE_UN > *total = COSTS_N_INSNS (1); > return true; > } > + /* Before strength-reduction, the shNadd can be expressed as the addition > + of a multiplication with a power-of-two. If this case is not handled, > + the strength-reduction in expmed.c will calculate an inflated cost. */ > + if (TARGET_ZBA > + && mode == word_mode > + && GET_CODE (XEXP (x, 0)) == MULT > + && REG_P (XEXP (XEXP (x, 0), 0)) > + && CONST_INT_P (XEXP (XEXP (x, 0), 1)) > + && IN_RANGE (pow2p_hwi (INTVAL (XEXP (XEXP (x, 0), 1))), 1, 3)) IIUC the fall-through is biting us here and this matches power-of-2 +1 and power-of-2 -1. That looks to be the case for the one below, though, so not sure if I'm just missing something? > + { > + *total = COSTS_N_INSNS (1); > + return true; > + } > /* shNadd.uw pattern for zba. > [(set (match_operand:DI 0 "register_operand" "=r") > (plus:DI