From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-pl1-x62d.google.com (mail-pl1-x62d.google.com [IPv6:2607:f8b0:4864:20::62d]) by sourceware.org (Postfix) with ESMTPS id 353DA3858D33 for ; Thu, 27 Apr 2023 16:20:09 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 353DA3858D33 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=rivosinc.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=rivosinc.com Received: by mail-pl1-x62d.google.com with SMTP id d9443c01a7336-1a8097c1ccfso89207515ad.1 for ; Thu, 27 Apr 2023 09:20:09 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20221208.gappssmtp.com; s=20221208; t=1682612408; x=1685204408; h=content-transfer-encoding:mime-version:message-id:to:from:cc :in-reply-to:subject:date:from:to:cc:subject:date:message-id :reply-to; bh=aug0/TyrWrvZz6ultaQBos/N39x1vM21EnNqAZdrfng=; b=3r2I/pue//0TH/kELLek5Qn48Zgl0rbzplq//tBvjxkiQWM1v364kUrg+VvCw5Qunk Gu8vyHvhJtrAnEp1Kv1T1DFRxzXPxGaRUbVYPoMueO4hgjHWrqiERaPBc9ViWWycKjQo 4lZRUoHWh5G9Mf1Gf+4zj6IkXqazq6T7CYkGdFR9QtJPmNmYlHZ8HsZ4qtYUcv0ylkE6 FX0gNs4DjHYv9Te6Ayi1+/bf+GWP95Lh89i0Ry+8bfnOlbxQ1UYygEMBNBS9w4GxYVU/ QQeg62L7wADSQb9ZG/bmRYFF9W3p6L/byJrZfy0yUh2LzDzk0Lw1+zC4ci2tSYLEg/aR UyjQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1682612408; x=1685204408; h=content-transfer-encoding:mime-version:message-id:to:from:cc :in-reply-to:subject:date:x-gm-message-state:from:to:cc:subject:date :message-id:reply-to; bh=aug0/TyrWrvZz6ultaQBos/N39x1vM21EnNqAZdrfng=; b=Y+z7G586RNcaEHR3nMtrpMRNF+VFArMgVt5TOn+60sLGFcyzWdrJEqbizMYenk72Pk UD0QnV/uQeM0iXbl+GPYKXnQ0UX6g1/5FAWvUpeXaq0T2ltP2MB/TJBAvwHDEbuV0xUr HKT5wi9o+J5J619vnehY9v719tlySa/TtIk/cVz+TJLDBiB4ZdPOY80ICHU8ufTgxpFi RY/7NTI6MlR5yPzUZvC9scOy5tVTi6oW6pskThRD/h3vXOUd9kIPCotoSsdgIeYqslnp LxzSP51eM1qNwmKaA0k+1zAYSl8mZouMxniYDUFOD//2PKvoMQRKgU63pAB+0R+NrWOT fskQ== X-Gm-Message-State: AC+VfDyQGeEmkaXrpS4yubwINHk42xW08jJ5DnIhBFipnhg8I+FR5frz 3T6Ja/WnwOY5pKHyl575P/k9xQ== X-Google-Smtp-Source: ACHHUZ7T5iG6xL72nA5TvmDspqUAhNMzdMJmjkg0XCjv3gc97FqnElfQHx2IZhiHk9Mn1JxRFHnJEw== X-Received: by 2002:a17:903:11cf:b0:1a9:95fa:1fa8 with SMTP id q15-20020a17090311cf00b001a995fa1fa8mr2420577plh.41.1682612407483; Thu, 27 Apr 2023 09:20:07 -0700 (PDT) Received: from localhost ([135.180.227.0]) by smtp.gmail.com with ESMTPSA id jd9-20020a170903260900b001a681fb3e77sm11547951plb.44.2023.04.27.09.20.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 27 Apr 2023 09:20:07 -0700 (PDT) Date: Thu, 27 Apr 2023 09:20:07 -0700 (PDT) X-Google-Original-Date: Thu, 27 Apr 2023 09:20:04 PDT (-0700) Subject: Re: [PATCH v4 05/10] RISC-V: autovec: Add autovectorization patterns for binary integer operations In-Reply-To: CC: juzhe.zhong@rivai.ai, rdapp.gcc@gmail.com, gcc-patches@gcc.gnu.org, jeffreyalaw@gmail.com, kito.cheng@sifive.com, Kito Cheng From: Palmer Dabbelt To: collison@rivosinc.com, kevinl@rivosinc.com Message-ID: Mime-Version: 1.0 (MHng) Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 8bit X-Spam-Status: No, score=-9.7 required=5.0 tests=BAYES_00,BODY_8BITS,DKIM_SIGNED,DKIM_VALID,GIT_PATCH_0,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,TXREP,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: On Wed, 26 Apr 2023 17:04:17 PDT (-0700), collison@rivosinc.com wrote: > Hi Robin and Juzhe, > > Just took a look and I like the approach. I assume it's best to just squash these into the series? That seems reasonable to me, the only issue is that Micheal's PTO for a few days (this week and the first half on next week), so it might take a bit longer that expected. There's a v5 on the lists, but we didn't have time to pick this all up and figured it'd be better to just get out whatever was ready. Kevin: do you have time to squash these in and re-spin the tests? The changes are big enough to warrant a v6 already, so might as well get started now. > On 4/26/23 19:43, juzhe.zhong wrote: >> Yeah，Robin stuff is what I want and is making perfect sense for me. >> ---- Replied Message ---- >> From Robin Dapp >> Date 04/27/2023 02:15 >> To juzhe.zhong@rivai.ai >> , >> collison , >> gcc-patches >> Cc jeffreyalaw , >> Kito.cheng , >> kito.cheng , >> palmer , >> palmer >> Subject Re: [PATCH v4 05/10] RISC-V:autovec: Add autovectorization >> patterns for binary integer operations >> >> Hi Michael, >> >> I have the diff below for the binops in my tree locally. >> Maybe something like this works for you? Untested but compiles and >> the expander helpers would need to be fortified obviously. >> >> Regards >> Robin >> >> -- >> >> gcc/ChangeLog: >> >>        * config/riscv/autovec.md (3): New binops expander. >>        * config/riscv/riscv-protos.h (emit_nonvlmax_binop): Define. >>        * config/riscv/riscv-v.cc (emit_pred_binop): New function. >>        (emit_nonvlmax_binop): New function. >>        * config/riscv/vector-iterators.md: New iterator. >> --- >> gcc/config/riscv/autovec.md          | 12 ++++ >> gcc/config/riscv/riscv-protos.h      |  1 + >> gcc/config/riscv/riscv-v.cc          | 89 ++++++++++++++++++++-------- >> gcc/config/riscv/vector-iterators.md | 20 +++++++ >> 4 files changed, 97 insertions(+), 25 deletions(-) >> >> diff --git a/gcc/config/riscv/autovec.md b/gcc/config/riscv/autovec.md >> index b5d46ff57ab..c21d241f426 100644 >> --- a/gcc/config/riscv/autovec.md >> +++ b/gcc/config/riscv/autovec.md >> @@ -47,3 +47,15 @@ (define_expand "len_store_" >>                  operands[1], operands[2], mode); >>   DONE; >> }) >> + >> +(define_expand "3" >> +  [(set (match_operand:VI 0 "register_operand") >> +    (any_int_binop:VI (match_operand:VI 1 "register_operand") >> +              (match_operand:VI 2 "register_operand")))] >> +  "TARGET_VECTOR" >> +{ >> +  riscv_vector::emit_nonvlmax_binop (code_for_pred (, >> mode), >> +                     operands[0], operands[1], operands[2], >> +                     gen_reg_rtx (Pmode), mode); >> +  DONE; >> +}) >> diff --git a/gcc/config/riscv/riscv-protos.h >> b/gcc/config/riscv/riscv-protos.h >> index f6ea6846736..5cca543c773 100644 >> --- a/gcc/config/riscv/riscv-protos.h >> +++ b/gcc/config/riscv/riscv-protos.h >> @@ -163,6 +163,7 @@ void emit_hard_vlmax_vsetvl (machine_mode, rtx); >> void emit_vlmax_op (unsigned, rtx, rtx, machine_mode); >> void emit_vlmax_op (unsigned, rtx, rtx, rtx, machine_mode); >> void emit_nonvlmax_op (unsigned, rtx, rtx, rtx, machine_mode); >> +void emit_nonvlmax_binop (unsigned, rtx, rtx, rtx, rtx, machine_mode); >> enum vlmul_type get_vlmul (machine_mode); >> unsigned int get_ratio (machine_mode); >> int get_ta (rtx); >> diff --git a/gcc/config/riscv/riscv-v.cc b/gcc/config/riscv/riscv-v.cc >> index 5e69427ac54..98ebc052340 100644 >> --- a/gcc/config/riscv/riscv-v.cc >> +++ b/gcc/config/riscv/riscv-v.cc >> @@ -52,7 +52,7 @@ namespace riscv_vector { >> template class insn_expander >> { >> public: >> -  insn_expander () : m_opno (0) {} >> +  insn_expander () : m_opno (0), has_dest(false) {} >>   void add_output_operand (rtx x, machine_mode mode) >>   { >>     create_output_operand (&m_ops[m_opno++], x, mode); >> @@ -83,6 +83,44 @@ public: >>     add_input_operand (gen_int_mode (type, Pmode), Pmode); >>   } >> >> +  void set_dest_and_mask (rtx mask, rtx dest, machine_mode mask_mode) >> +  { >> +    dest_mode = GET_MODE (dest); >> +    has_dest = true; >> + >> +    add_output_operand (dest, dest_mode); >> + >> +    if (mask) >> +      add_input_operand (mask, GET_MODE (mask)); >> +    else >> +      add_all_one_mask_operand (mask_mode); >> + >> +    add_vundef_operand (dest_mode); >> +  } >> + >> +  void set_len_and_policy (rtx len, bool vlmax_p) >> +    { >> +      gcc_assert (has_dest); >> +      gcc_assert (len || vlmax_p); >> + >> +      if (len) >> +    add_input_operand (len, Pmode); >> +      else >> +    { >> +      rtx vlmax = gen_reg_rtx (Pmode); >> +      emit_vlmax_vsetvl (dest_mode, vlmax); >> +      add_input_operand (vlmax, Pmode); >> +    } >> + >> +      if (GET_MODE_CLASS (dest_mode) != MODE_VECTOR_BOOL) >> +    add_policy_operand (get_prefer_tail_policy (), >> get_prefer_mask_policy ()); >> + >> +      if (vlmax_p) >> +    add_avl_type_operand (avl_type::VLMAX); >> +      else >> +    add_avl_type_operand (avl_type::NONVLMAX); >> +    } >> + >>   void expand (enum insn_code icode, bool temporary_volatile_p = false) >>   { >>     if (temporary_volatile_p) >> @@ -96,6 +134,8 @@ public: >> >> private: >>   int m_opno; >> +  bool has_dest; >> +  machine_mode dest_mode; >>   expand_operand m_ops[MAX_OPERANDS]; >> }; >> >> @@ -183,37 +223,29 @@ emit_pred_op (unsigned icode, rtx mask, rtx >> dest, rtx src, rtx len, >>          machine_mode mask_mode, bool vlmax_p) >> { >>   insn_expander<8> e; >> -  machine_mode mode = GET_MODE (dest); >> +  e.set_dest_and_mask (mask, dest, mask_mode); >> >> -  e.add_output_operand (dest, mode); >> - >> -  if (mask) >> -    e.add_input_operand (mask, GET_MODE (mask)); >> -  else >> -    e.add_all_one_mask_operand (mask_mode); >> +  e.add_input_operand (src, GET_MODE (src)); >> >> -  e.add_vundef_operand (mode); >> +  e.set_len_and_policy (len, vlmax_p); >> >> -  e.add_input_operand (src, GET_MODE (src)); >> +  e.expand ((enum insn_code) icode, MEM_P (dest) || MEM_P (src)); >> +} >> >> -  if (len) >> -    e.add_input_operand (len, Pmode); >> -  else >> -    { >> -      rtx vlmax = gen_reg_rtx (Pmode); >> -      emit_vlmax_vsetvl (mode, vlmax); >> -      e.add_input_operand (vlmax, Pmode); >> -    } >> +/* Emit an RVV unmask && vl mov from SRC to DEST.  */ >> +static void >> +emit_pred_binop (unsigned icode, rtx mask, rtx dest, rtx src1, rtx src2, >> +         rtx len, machine_mode mask_mode, bool vlmax_p) >> +{ >> +  insn_expander<9> e; >> +  e.set_dest_and_mask (mask, dest, mask_mode); >> >> -  if (GET_MODE_CLASS (mode) != MODE_VECTOR_BOOL) >> -    e.add_policy_operand (get_prefer_tail_policy (), >> get_prefer_mask_policy ()); >> +  e.add_input_operand (src1, GET_MODE (src1)); >> +  e.add_input_operand (src2, GET_MODE (src2)); >> >> -  if (vlmax_p) >> -    e.add_avl_type_operand (avl_type::VLMAX); >> -  else >> -    e.add_avl_type_operand (avl_type::NONVLMAX); >> +  e.set_len_and_policy (len, vlmax_p); >> >> -  e.expand ((enum insn_code) icode, MEM_P (dest) || MEM_P (src)); >> +  e.expand ((enum insn_code) icode, MEM_P (dest) || MEM_P (src1) || >> MEM_P (src2)); >> } >> >> void >> @@ -236,6 +268,13 @@ emit_nonvlmax_op (unsigned icode, rtx dest, rtx >> src, rtx len, >>   emit_pred_op (icode, NULL_RTX, dest, src, len, mask_mode, false); >> } >> >> +void >> +emit_nonvlmax_binop (unsigned icode, rtx dest, rtx src1, rtx src2, >> rtx len, >> +             machine_mode mask_mode) >> +{ >> +  emit_pred_binop (icode, NULL_RTX, dest, src1, src2, len, mask_mode, >> false); >> +} >> + >> static void >> expand_const_vector (rtx target, rtx src, machine_mode mask_mode) >> { >> diff --git a/gcc/config/riscv/vector-iterators.md >> b/gcc/config/riscv/vector-iterators.md >> index a8e856161d3..7cf21751d2f 100644 >> --- a/gcc/config/riscv/vector-iterators.md >> +++ b/gcc/config/riscv/vector-iterators.md >> @@ -934,6 +934,26 @@ (define_code_iterator any_int_binop [plus minus >> and ior xor ashift ashiftrt lshi >>   smax umax smin umin mult div udiv mod umod >> ]) >> >> +(define_code_attr ANY_INT_BINOP [ >> +    (plus "PLUS") >> +    (minus "MINUS") >> +    (and "AND") >> +    (ior "IOR") >> +    (xor "XOR") >> +    (ashift "ASHIFT") >> +    (ashiftrt "ASHIFTRT") >> +    (lshiftrt "LSHIFTRT") >> +    (smax "SMAX") >> +    (umax "UMAX") >> +    (smin "SMIN") >> +    (umin "UMIN") >> +    (mult "MULT") >> +    (div "DIV") >> +    (udiv "UDIV") >> +    (mod "MOD") >> +    (umod "UMOD") >> +]) >> + >> (define_code_iterator any_int_unop [neg not]) >> >> (define_code_iterator any_commutative_binop [plus and ior xor >> -- >> 2.40.0 >>