From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-ot1-x32a.google.com (mail-ot1-x32a.google.com [IPv6:2607:f8b0:4864:20::32a]) by sourceware.org (Postfix) with ESMTPS id AA15F3858298 for ; Fri, 14 Jul 2023 02:34:30 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org AA15F3858298 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=dabbelt.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=dabbelt.com Received: by mail-ot1-x32a.google.com with SMTP id 46e09a7af769-6b75637076eso1177505a34.2 for ; Thu, 13 Jul 2023 19:34:30 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=dabbelt-com.20221208.gappssmtp.com; s=20221208; t=1689302069; x=1691894069; h=content-transfer-encoding:mime-version:message-id:to:from:cc :in-reply-to:subject:date:from:to:cc:subject:date:message-id :reply-to; bh=MmjMsc33xfok8MyGm7SyUq6Fgw2beMrBaLkzQd/gDPQ=; b=v3RMn2vVrgpO4DaNiNNh593p7X0Fo1mYYxyfGnQpJiFLveoWeQve+cQ50ItlUU+J38 yHiyIINT3UTm3OuPzTBeH9pp33mRme3cSWN0o5qnQitFrl13zMmjJlnXF29be3jS0mxu 49UYByKx28w5KrGIZHT31gYuZ/86MxTsvaB73NbFcA6uOif2Q29Pb7JmmaPd+Vdf9b+l /rdoXvn3z7hHvtnkJXoFphnOxefldsToc/zErG/HKSZds4VPWj1H/hvCNHZEHcRQ8cPk hNYdqw1Q9s2vD+lpQiGvaUGfRaT7a7qdjDL0ePe8mDBUCDN9uNSjgC19K5zlMwaCqlzQ f4Gw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1689302069; x=1691894069; h=content-transfer-encoding:mime-version:message-id:to:from:cc :in-reply-to:subject:date:x-gm-message-state:from:to:cc:subject:date :message-id:reply-to; bh=MmjMsc33xfok8MyGm7SyUq6Fgw2beMrBaLkzQd/gDPQ=; b=HOzUYE6hda12HsTooLPL01QGDI+YA5qXTinm841GioH29LEwspTBaQLcec0sy7ykcm hgBd8mm4Ledlx2to5QTufz3tQb8RGodybtDSMTyidfoCOg9HT1Kavx5EyWWB9xF7B0qd pjm6PHU0WcvJQuOtpI5c6V+M5EIFffZATjgT1AyI1w77wMKhW1g5zXxzi1D7KHzdNGpS 3eZvys3sA/CbTaRxDRryPTjRMKyKrVuMcK9Mm+0QQtFLC4TmC4K9gK6LK+hqEjWRf7I8 1bKuikihBJiVpjwfjnEV9ra+VhSRzorUcF7Ngih5ss71Vm4Yj+OUTnb583BH4HdrY/dq rS7A== X-Gm-Message-State: ABy/qLbcFZBOI/sgu02pmWqJuZaeUbmHGsjbjta+aY5hcoxU3l4cTDve mSTuGux4FbAj4NGoVbPUt5SyPH7LjDNXvdFmrOY= X-Google-Smtp-Source: APBJJlGwnS8ioA4T5+V/DXYeMzjegAy+5XOMD3mVD5MhbETlobUEv3LaGYKYNhG8YFRNunnUlZP7Hw== X-Received: by 2002:a05:6358:2610:b0:134:d24d:86b with SMTP id l16-20020a056358261000b00134d24d086bmr5098097rwc.16.1689302069371; Thu, 13 Jul 2023 19:34:29 -0700 (PDT) Received: from localhost ([50.38.6.230]) by smtp.gmail.com with ESMTPSA id o6-20020a637306000000b0054fa8539681sm6315647pgc.34.2023.07.13.19.34.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 13 Jul 2023 19:34:28 -0700 (PDT) Date: Thu, 13 Jul 2023 19:34:28 -0700 (PDT) X-Google-Original-Date: Thu, 13 Jul 2023 19:33:42 PDT (-0700) Subject: Re: [PATCH] RISC-V: Remove the redundant expressions in the and3. In-Reply-To: <20230714020205.16214-1-lidie@eswincomputing.com> CC: gcc-patches@gcc.gnu.org, Kito Cheng , jeffeyalaw@gmail.com, lidie@eswincomputing.com From: Palmer Dabbelt To: lidie@eswincomputing.com Message-ID: Mime-Version: 1.0 (MHng) Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 8bit X-Spam-Status: No, score=-9.2 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,GIT_PATCH_0,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,TXREP,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: On Thu, 13 Jul 2023 19:02:05 PDT (-0700), lidie@eswincomputing.com wrote: > When generating the gen_and3 function based on the and3 > template, it produces the expression emit_insn (gen_rtx_SET (operand0, > gen_rtx_AND (, operand1, operand2)));, which is identical to the > portion I removed in this patch. Therefore, the redundant portion can be > deleted. > > Signed-off-by: Die Li > > gcc/ChangeLog: > > * config/riscv/riscv.md: Remove redundant portion in and3. > --- > gcc/config/riscv/riscv.md | 5 ----- > 1 file changed, 5 deletions(-) > > diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md > index 7988026d129..c4f8eb9488e 100644 > --- a/gcc/config/riscv/riscv.md > +++ b/gcc/config/riscv/riscv.md > @@ -1491,11 +1491,6 @@ > DONE; > } > } > - else > - { > - emit_move_insn (operands[0], gen_rtx_AND (mode, operands[1], operands[2])); > - DONE; > - } > }) > > (define_insn "*and3" Unless I'm missing something, this will just result in no emitted instructions for this "and" pattern? That seems wrong, it would at least have to put the source into the dest -- but "arith_operand_or_mode_mask" can contain values that don't just result in an extension (like arbitrary register values, for example), so I think we need the "and" operation. Does this pass the regression suite? Either way, if this branch of the conditional can't trigger we should tighten the constraint (or at a bare minimum add a comment as to why).