From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-pl1-x62b.google.com (mail-pl1-x62b.google.com [IPv6:2607:f8b0:4864:20::62b]) by sourceware.org (Postfix) with ESMTPS id 67CA538582A2 for ; Fri, 28 Oct 2022 16:47:19 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 67CA538582A2 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=dabbelt.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=dabbelt.com Received: by mail-pl1-x62b.google.com with SMTP id c24so5311785pls.9 for ; Fri, 28 Oct 2022 09:47:19 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=dabbelt-com.20210112.gappssmtp.com; s=20210112; h=content-transfer-encoding:mime-version:message-id:to:from:cc :in-reply-to:subject:date:from:to:cc:subject:date:message-id :reply-to; bh=cFGZ60e7S+UEwGYJATuzCx6o99lKD7spjc28H9mfmBQ=; b=qBmMOm+sscgT0SEUtXBmvYTjlrkVxkgoVd/C+/KHTmA8lsPrKs8ciMfCaDCqH/7ZjK NAJJ5g8Bk/Tbcq5Z02q1L4Zq1NhWM2nwv6N2wowbxG04w2ZU+QiKdhbvN0TP2697vy98 7vTv/VKbqKXjmj0B7vkSxTJ0DXgyEkGqLWRqJkgULIdLXaqw8VQBizg/veDVkd7Pg4cJ A9/kfU00F9oaYln22fNYQcp4H8yUiE8j3o+4oYJJvhvq1TD2B5itio5rqju3OThkUIGQ oetoavK48BodVbBwbN87/ZKJ4GHGpwihAL7DTo/YqGb8vYxgzbUzaUlL9z0+OJDEWYeH YPPQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:message-id:to:from:cc :in-reply-to:subject:date:x-gm-message-state:from:to:cc:subject:date :message-id:reply-to; bh=cFGZ60e7S+UEwGYJATuzCx6o99lKD7spjc28H9mfmBQ=; b=oE9ZQxxLEzhVrw+fEeiE3b3GOgN3seTHZ670oG8Peqlk8IIpHwNQXYNIXaoUnArKRY 6twWWVLpccJJ0WEniv2h2Wo03LyFdyBEverwBLJ+2ewKLJUp+DnNFeo9RmBw1oC5rj/9 gR61F67wPqd3DYagVYePxBZ8S1A9Jk5hXtTuw94hjj6UvvyUmGUmFzDa2oTKYNePzTS/ qp/Ybl6Xk5+0hG8lFRcI7TsTezK8UOpvuVtxuFpQETkeonJVX/Qz/O8Rcfv+RMHjf7SE wRUAKqwoq61N8CQHYWSCiL3c4uRiTffwukchzPqJVvg9yc9cL31FSR+puKRINku+mQUM A1kg== X-Gm-Message-State: ACrzQf2eak6dallwooUsi+PPMuTlljcKZX/hE6QfuKmJgflwbV0Hak/r vg4etufPRjcV65cbMzPQ+kLlsw== X-Google-Smtp-Source: AMsMyM7rIx27cMnl7tDIH2HQJakiq3TdBQhtDZjEQpU7Q2tRGqHP1hxNpsKyvbL3yxhHW6xIYEOW+w== X-Received: by 2002:a17:90a:ec04:b0:213:60bf:e6f7 with SMTP id l4-20020a17090aec0400b0021360bfe6f7mr14649007pjy.211.1666975638152; Fri, 28 Oct 2022 09:47:18 -0700 (PDT) Received: from localhost ([50.221.140.188]) by smtp.gmail.com with ESMTPSA id u16-20020a170902e5d000b00186b280a441sm3307425plf.239.2022.10.28.09.47.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 28 Oct 2022 09:47:17 -0700 (PDT) Date: Fri, 28 Oct 2022 09:47:17 -0700 (PDT) X-Google-Original-Date: Fri, 28 Oct 2022 09:47:20 PDT (-0700) Subject: Re: [PATCH v3] RISC-V: Libitm add RISC-V support. In-Reply-To: CC: xc-tan@outlook.com, fantasquex@gmail.com, gcc-patches@gcc.gnu.org, Andrew Waterman From: Palmer Dabbelt To: gcc-patches@gcc.gnu.org Message-ID: Mime-Version: 1.0 (MHng) Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 8bit X-Spam-Status: No, score=-10.7 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,GIT_PATCH_0,KAM_SHORT,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: On Fri, 28 Oct 2022 02:37:13 PDT (-0700), gcc-patches@gcc.gnu.org wrote: > I guess we don't really care about RV32E here, but in case you add a > guard for that? > > #ifdef __riscv_e > #error "rv32e unsupported" > #endif Ah, thanks. There's rv64e now too, but that's just an error message problem so probably not a big deal. > On Fri, Oct 28, 2022 at 4:39 PM Xiongchuan Tan via Gcc-patches > wrote: >> >> Reviewed-by: Palmer Dabbelt >> Acked-by: Palmer Dabbelt >> >> libitm/ChangeLog: >> >> * configure.tgt: Add riscv support. >> * config/riscv/asm.h: New file. >> * config/riscv/sjlj.S: New file. >> * config/riscv/target.h: New file. >> --- >> v2: Change HW_CACHELINE_SIZE to 64 (in accordance with the RVA profiles, see >> https://github.com/riscv/riscv-profiles/blob/main/profiles.adoc) >> >> v3: Ensure the stack is aligned to 16 bytes; make use of Zihintpause in >> cpu_relax() >> >> libitm/config/riscv/asm.h | 54 +++++++++++++ >> libitm/config/riscv/sjlj.S | 144 +++++++++++++++++++++++++++++++++++ >> libitm/config/riscv/target.h | 62 +++++++++++++++ >> libitm/configure.tgt | 2 + >> 4 files changed, 262 insertions(+) >> create mode 100644 libitm/config/riscv/asm.h >> create mode 100644 libitm/config/riscv/sjlj.S >> create mode 100644 libitm/config/riscv/target.h >> >> diff --git a/libitm/config/riscv/asm.h b/libitm/config/riscv/asm.h >> new file mode 100644 >> index 0000000..bb515f2 >> --- /dev/null >> +++ b/libitm/config/riscv/asm.h >> @@ -0,0 +1,54 @@ >> +/* Copyright (C) 2022 Free Software Foundation, Inc. >> + Contributed by Xiongchuan Tan . >> + >> + This file is part of the GNU Transactional Memory Library (libitm). >> + >> + Libitm is free software; you can redistribute it and/or modify it >> + under the terms of the GNU General Public License as published by >> + the Free Software Foundation; either version 3 of the License, or >> + (at your option) any later version. >> + >> + Libitm is distributed in the hope that it will be useful, but WITHOUT ANY >> + WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS >> + FOR A PARTICULAR PURPOSE. See the GNU General Public License for >> + more details. >> + >> + Under Section 7 of GPL version 3, you are granted additional >> + permissions described in the GCC Runtime Library Exception, version >> + 3.1, as published by the Free Software Foundation. >> + >> + You should have received a copy of the GNU General Public License and >> + a copy of the GCC Runtime Library Exception along with this program; >> + see the files COPYING3 and COPYING.RUNTIME respectively. If not, see >> + . */ >> + >> +#ifndef _RV_ASM_H >> +#define _RV_ASM_H >> + >> +#if __riscv_xlen == 64 >> +# define GPR_L ld >> +# define GPR_S sd >> +# define SZ_GPR 8 >> +# define LEN_GPR 14 >> +#elif __riscv_xlen == 32 >> +# define GPR_L lw >> +# define GPR_S sw >> +# define SZ_GPR 4 >> +# define LEN_GPR 16 /* Extra padding to align the stack to 16 bytes */ >> +#else >> +# error Unsupported XLEN (must be 64-bit or 32-bit). >> +#endif >> + >> +#if defined(__riscv_flen) && __riscv_flen == 64 >> +# define FPR_L fld >> +# define FPR_S fsd >> +# define SZ_FPR 8 >> +#elif defined(__riscv_flen) && __riscv_flen == 32 >> +# define FPR_L flw >> +# define FPR_S fsw >> +# define SZ_FPR 4 > > Check __riscv_flen is not 32 or 64 here, in case we add Q-extension > then we can error out. > >> diff --git a/libitm/config/riscv/sjlj.S b/libitm/config/riscv/sjlj.S >> new file mode 100644 >> index 0000000..93f12ec >> --- /dev/null >> +++ b/libitm/config/riscv/sjlj.S >> @@ -0,0 +1,144 @@ >> +#include "asmcfi.h" >> +#include "asm.h" >> + >> + .text >> + .align 2 >> + .global _ITM_beginTransaction >> + .type _ITM_beginTransaction, @function >> + >> +_ITM_beginTransaction: >> + cfi_startproc >> + mv a1, sp >> + addi sp, sp, -(LEN_GPR*SZ_GPR+ 12*SZ_FPR) > > This expression appeared 4 times, maybe define a marco ADJ_STACK_SIZE > or something else to hold that? > >> + cfi_adjust_cfa_offset(LEN_GPR*SZ_GPR+ 12*SZ_FPR) > >> diff --git a/libitm/config/riscv/target.h b/libitm/config/riscv/target.h >> new file mode 100644 >> index 0000000..b8a1665 >> --- /dev/null >> +++ b/libitm/config/riscv/target.h >> @@ -0,0 +1,62 @@ >> +typedef struct gtm_jmpbuf >> + { >> + long int pc; >> + void *cfa; >> + long int s[12]; /* Saved registers, s0 is fp */ >> + >> +#if __riscv_xlen == 32 >> + /* Ensure that the stack is 16-byte aligned */ >> + long int padding[2]; >> +#endif >> + >> + /* FP saved registers */ >> +#if defined(__riscv_flen) && __riscv_flen == 64 >> + double fs[12]; >> +#elif defined(__riscv_flen) && __riscv_flen == 32 >> + float fs[12]; > > Same here, error __riscv_flen if defined but not 64 or 32.