From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-pj1-x1035.google.com (mail-pj1-x1035.google.com [IPv6:2607:f8b0:4864:20::1035]) by sourceware.org (Postfix) with ESMTPS id 145D23850609 for ; Fri, 16 Dec 2022 21:59:26 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 145D23850609 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=dabbelt.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=dabbelt.com Received: by mail-pj1-x1035.google.com with SMTP id q17-20020a17090aa01100b002194cba32e9so7446983pjp.1 for ; Fri, 16 Dec 2022 13:59:26 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=dabbelt-com.20210112.gappssmtp.com; s=20210112; h=content-transfer-encoding:mime-version:message-id:to:from:cc :in-reply-to:subject:date:from:to:cc:subject:date:message-id :reply-to; bh=/l41AlDHRkApG9mdzIPHR7wB4CbJIW0o64jXGUELqtM=; b=juvO0xpXJscV1018n8itM90Mfvm1ZqmVp3vracvBkYMMe6xijhYf++A4dbXuFiD+DU NB6wHGqQYxX/hbqARxda0aayyTMnwUkvpKjObTC92rQ1vKp0QmYjCt0NNfbBESDVNtGc enLpX5SRW/GANqSPINZj7XWe+J7OOaHCoUrClZ87DeaQIUmHGQRrlVHFZtjBmVsn/SPr V3+pzofVyKdqBu1JNAUJMLu9z+BfFZhnFPzJZwziLC1LWiKloPlp5lPb7PqgFqtWpcBd 7Z2Syuis5sAkr4ZOmuAJjy8plxhyyRDHV8kPCk0xoM7pvc26CEY4GCydo1Ky8OWBX/a1 dmKA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:message-id:to:from:cc :in-reply-to:subject:date:x-gm-message-state:from:to:cc:subject:date :message-id:reply-to; bh=/l41AlDHRkApG9mdzIPHR7wB4CbJIW0o64jXGUELqtM=; b=w6OvuoWvrCaSf/MJCX1xxhKr/Jgg1QaxeD53ZWpZruZYacIMcMk8w75kATS0DS1ht8 rJ7YGwbC1ZLj4rGFg3JUHOFBVjTcXO2XVq3sVW4XM11oSSWUzw6fAelsg2lkmA3rD2Tm g6kHPBuEqa8mi5T1NACmgQEoNsZv71Jx4sN3GzuV4i5S6hLroF8tCp3qDyeRecep0Z0r R/Vj3PXZ4RWaXIa7tNqs2EIGSwC7mBNL3dIzDTDciJv0uWMIijqqdWjHfc5ToXpwN6zg MVK1v5izshDo44WnypMwwwzhGmBB8MfuWetGfLHepiEdB3JpSeDTRBu4Dtipv1Ul0HaK /3tQ== X-Gm-Message-State: ANoB5plhWGLojXB8274ypfAPtfq411kPJIkwY80qHX/xKFoGW6NgL7FA 4JmXz8cvxsyJaJBfF+SyC952BA== X-Google-Smtp-Source: AA0mqf6vHdXB46OwOR2qY/kkP/1x6Ht4F6nO8gMbParHAVUdNSTaOQ6PvUnChGp8xQ+YXWZTfYzUtw== X-Received: by 2002:a17:90b:2652:b0:219:6e12:bc98 with SMTP id pa18-20020a17090b265200b002196e12bc98mr35983847pjb.25.1671227964898; Fri, 16 Dec 2022 13:59:24 -0800 (PST) Received: from localhost ([50.221.140.188]) by smtp.gmail.com with ESMTPSA id nk12-20020a17090b194c00b002195819d541sm5415550pjb.8.2022.12.16.13.59.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 16 Dec 2022 13:59:24 -0800 (PST) Date: Fri, 16 Dec 2022 13:59:24 -0800 (PST) X-Google-Original-Date: Fri, 16 Dec 2022 13:15:30 PST (-0800) Subject: Re: [PATCH] RISC-V: Remove unit-stride store from ta attribute In-Reply-To: CC: juzhe.zhong@rivai.ai, gcc-patches@gcc.gnu.org, Kito Cheng From: Palmer Dabbelt To: jeffreyalaw@gmail.com Message-ID: Mime-Version: 1.0 (MHng) Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 8bit X-Spam-Status: No, score=-4.8 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: On Fri, 16 Dec 2022 12:01:04 PST (-0800), jeffreyalaw@gmail.com wrote: > > > On 12/14/22 04:36, juzhe.zhong@rivai.ai wrote: >> From: Ju-Zhe Zhong >> >> Since store instructions doesn't care about tail policy, we remove >> vste from "ta" attribute. Hence, we could have more fusion chances >> and better optimization. >> >> gcc/ChangeLog: >> >> * config/riscv/vector.md: Remove vste. > Just to confirm that I understand the basic model. Vector stores only > update active elements, thus they don't care about tail policy, right? > > Assuming that's the case, then this is OK. That had been my assumption as well, but I don't see that explicitly called out in the ISA manual. I see Masked vector stores only update active memory elements. where "active" is defined as * The _body_ elements are those whose element index is greater than or equal to the initial value in the `vstart` register, and less than the current vector length setting in `vl`. The body can be split into two disjoint subsets: ** The _active_ elements during a vector instruction's execution are the elements within the body and where the current mask is enabled at that element position. The active elements can raise exceptions and update the destination vector register group. but I don't see anything about the unmasked stores. The blurb about tail elements only applies to registers groups, not memory addresses, so I think that's kind of a grey area there too. I was pretty sure the intent here was to have tail elements not updated in memory, so hopefully I'm just missing something in the spec. I open an issue to check: https://github.com/riscv/riscv-v-spec/issues/846