Re: [PATCH] RISC-V: Implement ZTSO extension.

[Palmer Dabbelt <palmer@dabbelt.com>]

On Mon, 21 Mar 2022 19:39:24 PDT (-0700), kito.cheng@sifive.com wrote:
> Hi Palmer:
>
> I guess the problem is binutils isn't included and it's too close to the
> GCC release, and binutils will report errors if it has any unsupported
> extensions.

Ya, sorry, I was trying to say that we should have more than just the 
binutils support -- IIUC having binutils support the GCC flags at 
release is the standard way to do things, and I don't see any reason to 
rush this.

>
> Most distro will use GCC 12 + binutils 2.38 or GCC 11 + binutils 2.38, so
> either combination doesn't work for march string with ztso.
>
> So that's why I am not intending to include that at this moment, but maybe
> we could include that first and it'll work once binutils 2.39 released,
> then we can have GCC 12 + binutils 2.39 in the next few months.
>
> Anyway, I think I am fine with that, and I'll ping Nelson for the binutils
> part.
>
> On Tue, Mar 22, 2022 at 9:13 AM Palmer Dabbelt <palmer@dabbelt.com> wrote:
>
>> On Thu, 17 Mar 2022 23:52:04 PDT (-0700), gcc-patches@gcc.gnu.org wrote:
>> > Hi Shi-Hua:
>> >
>> > Thanks, this patch is LGTM, but I would defer that until stage 1,
>> > because the binutils part isn't merget yet.
>>
>> IMO we should at least have a __riscv_ztso define, and ideally have the
>> relevent builtins ported (atomics, fences, etc) as well.  Otherwise this
>> is really just setting a bit that makes binaries incompatible without
>> providing any real benefit.  That'll also let us work through how these
>> mappings should be implemented, so we don't end up with issues like we
>> did with WMO.
>>
>> >
>> > On Tue, Mar 15, 2022 at 5:10 PM <shihua@iscas.ac.cn> wrote:
>> >>
>> >> From: LiaoShihua <shihua@iscas.ac.cn>
>> >>
>> >>       ZTSO is the extension of tatol store order model.
>> >>       This extension adds no new instructions to the ISA, and you can
>> use it with arch "ztso".
>> >>       If you use it, TSO flag will be generate in the ELF header.
>> >>
>> >> gcc/ChangeLog:
>> >>
>> >>         * common/config/riscv/riscv-common.cc: define new arch.
>> >>         * config/riscv/riscv-opts.h (MASK_ZTSO): Ditto.
>> >>         (TARGET_ZTSO):Ditto.
>> >>         * config/riscv/riscv.opt:Ditto.
>> >>
>> >> ---
>> >>  gcc/common/config/riscv/riscv-common.cc | 4 +++-
>> >>  gcc/config/riscv/riscv-opts.h           | 3 +++
>> >>  gcc/config/riscv/riscv.opt              | 3 +++
>> >>  3 files changed, 9 insertions(+), 1 deletion(-)
>> >>
>> >> diff --git a/gcc/common/config/riscv/riscv-common.cc
>> b/gcc/common/config/riscv/riscv-common.cc
>> >> index a904893b9ed..f4730b991d7 100644
>> >> --- a/gcc/common/config/riscv/riscv-common.cc
>> >> +++ b/gcc/common/config/riscv/riscv-common.cc
>> >> @@ -185,6 +185,8 @@ static const struct riscv_ext_version
>> riscv_ext_version_table[] =
>> >>    {"zvl32768b", ISA_SPEC_CLASS_NONE, 1, 0},
>> >>    {"zvl65536b", ISA_SPEC_CLASS_NONE, 1, 0},
>> >>
>> >> +  {"ztso", ISA_SPEC_CLASS_NONE, 0, 1},
>> >> +
>> >>    /* Terminate the list.  */
>> >>    {NULL, ISA_SPEC_CLASS_NONE, 0, 0}
>> >>  };
>> >> @@ -1080,7 +1082,7 @@ static const riscv_ext_flag_table_t
>> riscv_ext_flag_table[] =
>> >>    {"zvl32768b", &gcc_options::x_riscv_zvl_flags, MASK_ZVL32768B},
>> >>    {"zvl65536b", &gcc_options::x_riscv_zvl_flags, MASK_ZVL65536B},
>> >>
>> >> -
>> >> +  {"ztso", &gcc_options::x_riscv_ztso_subext, MASK_ZTSO},
>> >>    {NULL, NULL, 0}
>> >>  };
>> >>
>> >> diff --git a/gcc/config/riscv/riscv-opts.h
>> b/gcc/config/riscv/riscv-opts.h
>> >> index 929e4e3a7c5..9cb5f2a550a 100644
>> >> --- a/gcc/config/riscv/riscv-opts.h
>> >> +++ b/gcc/config/riscv/riscv-opts.h
>> >> @@ -136,4 +136,7 @@ enum stack_protector_guard {
>> >>  #define TARGET_ZVL32768B ((riscv_zvl_flags & MASK_ZVL32768B) != 0)
>> >>  #define TARGET_ZVL65536B ((riscv_zvl_flags & MASK_ZVL65536B) != 0)
>> >>
>> >> +#define MASK_ZTSO    (1 <<  0)
>> >> +#define TARGET_ZTSO    ((riscv_ztso_subext & MASK_ZTSO) != 0)
>> >> +
>> >>  #endif /* ! GCC_RISCV_OPTS_H */
>> >> diff --git a/gcc/config/riscv/riscv.opt b/gcc/config/riscv/riscv.opt
>> >> index 9fffc08220d..6128bfa31dc 100644
>> >> --- a/gcc/config/riscv/riscv.opt
>> >> +++ b/gcc/config/riscv/riscv.opt
>> >> @@ -209,6 +209,9 @@ int riscv_vector_eew_flags
>> >>  TargetVariable
>> >>  int riscv_zvl_flags
>> >>
>> >> +TargetVariable
>> >> +int riscv_ztso_subext
>> >> +
>> >>  Enum
>> >>  Name(isa_spec_class) Type(enum riscv_isa_spec_class)
>> >>  Supported ISA specs (for use with the -misa-spec= option):
>> >> --
>> >> 2.31.1.windows.1
>> >>
>>