From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-pl1-x634.google.com (mail-pl1-x634.google.com [IPv6:2607:f8b0:4864:20::634]) by sourceware.org (Postfix) with ESMTPS id A86D63858D32 for ; Sat, 18 Feb 2023 18:26:36 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org A86D63858D32 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=dabbelt.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=dabbelt.com Received: by mail-pl1-x634.google.com with SMTP id o9so1291971plk.12 for ; Sat, 18 Feb 2023 10:26:36 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=dabbelt-com.20210112.gappssmtp.com; s=20210112; h=content-transfer-encoding:mime-version:message-id:to:from :in-reply-to:subject:date:from:to:cc:subject:date:message-id :reply-to; bh=ZxgUz+WDPmNecYxp4wbWovFDgeZu/ZF0f38J36jhSHI=; b=oMc2ODaTuq9/nSET5EJ3UQhiligCziL+gni+RdiV1tDffKIpkE5fFOw9Rttx81tyhB PmFj74wpIfJD/10pNGPXjtbyEevimOvZg5g5YqmKFcJjd/fcWu4twcWI15sb5daC/TE9 YrBorYe4WNqL72ztZzSuW1k6VFPAofL5TnNAiG+e54GbW2M633xNlMdvLSJ+QA0p/CIS bTJ9olywl0o27c/O3eD0futdc068qnf6gWQnoSKN9eau6szCkRBVexcJkxDKMWa3Ktag JuoAkUxQkcmeGReTjQM4+cOijjWDPRnMG6vwEXsapsGPhkaMLIl4pZEvogve877131E3 7XJA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:message-id:to:from :in-reply-to:subject:date:x-gm-message-state:from:to:cc:subject:date :message-id:reply-to; bh=ZxgUz+WDPmNecYxp4wbWovFDgeZu/ZF0f38J36jhSHI=; b=jfzaD0v7XCTsXUHpa6CAvScPl6bejD49zN4ahG/4+RIaRoj1dcGaxAAiHDKVEI33aK fyN/h5mdnvqQcztVWS5JH/v/RPoDLmfp4oih59TVUBXufh4n30vbn8+Pqy3F9KybsE1i RFE1dkXml/mU9laOZR/lYNGL6pdFHpAlXQ3aWHU0wFJ9upoO2E+GOZ79NDjjj9jIaGTA AnQoUnl9pRDZuWsBHpSz7X4AYNCSxPXREG04vM0aCEW1NhYlUanmayxUF7YvYdVlT9i1 WcTL6CwC6like0PjhzSJyHXAdOf63CV0wTOssmPH5u/hA8nrCQFs4G4k+qfem6q51bKq so2g== X-Gm-Message-State: AO0yUKU9Bw5vDqLs1QQqZvPxvFGtm59tYtJxuJ6iUz4eI4Pi9noWMmHM R2rPWDvJBpDh22xJtlYNTS/WKc5afN/lP0Bt X-Google-Smtp-Source: AK7set+D2tGzKBSzCSmoB0XLBdHNLHETcmIXTgYFByipPCrWcAciOdx32F42i2rAtOMw2rmkBNW7lA== X-Received: by 2002:a17:903:2c8:b0:19a:996c:5c2b with SMTP id s8-20020a17090302c800b0019a996c5c2bmr169967plk.39.1676744794760; Sat, 18 Feb 2023 10:26:34 -0800 (PST) Received: from localhost ([50.221.140.188]) by smtp.gmail.com with ESMTPSA id jl1-20020a170903134100b00196025a34b9sm4967624plb.159.2023.02.18.10.26.33 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 18 Feb 2023 10:26:34 -0800 (PST) Date: Sat, 18 Feb 2023 10:26:34 -0800 (PST) X-Google-Original-Date: Sat, 18 Feb 2023 10:25:50 PST (-0800) Subject: Re: RISC-V: Add divmod instruction support In-Reply-To: From: Palmer Dabbelt To: gcc-patches@gcc.gnu.org Message-ID: Mime-Version: 1.0 (MHng) Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 8bit X-Spam-Status: No, score=-10.8 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,GIT_PATCH_0,KAM_SHORT,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: On Fri, 17 Feb 2023 06:02:40 PST (-0800), gcc-patches@gcc.gnu.org wrote: > Hi all, > If we have division and remainder calculations with the same operands: > > a = b / c; > d = b % c; > > We can replace the calculation of remainder with multiplication + > subtraction, using the result from the previous division: > > a = b / c; > d = a * c; > d = b - d; > > Which will be faster. Do you have any benchmarks that show that performance increase? The ISA manual specifically says the suggested sequence is div+mod, and while those suggestions don't always pan out for real hardware it's likely that at least some implementations will end up with the ISA-suggested fusions. > Currently, it isn't done for RISC-V. > > I've added an expander for DIVMOD which replaces 'rem' with 'mul + sub'. > > Best regards, > Matevos. > > gcc/ChangeLog: > > * config/riscv/riscv.md: Added divmod expander. > > gcc/testsuite/ChangeLog: > * gcc.target/riscv/divmod.c: New testcase. > > --- inline copy of the patch --- > > diff --git a/gcc/config/riscv/iterators.md b/gcc/config/riscv/iterators.md > index f95dd405e12..d941483d9f1 100644 > --- a/gcc/config/riscv/iterators.md > +++ b/gcc/config/riscv/iterators.md > @@ -148,6 +148,11 @@ > ;; from the same template. > (define_code_iterator any_mod [mod umod]) > > +;; These code iterators allow unsigned and signed divmod to be generated > +;; from the same template. > +(define_code_iterator only_div [div udiv]) > +(define_code_attr paired_mod [(div "mod") (udiv "umod")]) > + > ;; These code iterators allow the signed and unsigned scc operations to use > ;; the same template. > (define_code_iterator any_gt [gt gtu]) > @@ -175,7 +180,8 @@ > (gt "") (gtu "u") > (ge "") (geu "u") > (lt "") (ltu "u") > - (le "") (leu "u")]) > + (le "") (leu "u") > + (div "") (udiv "u")]) > > ;; is like , but the signed form expands to "s" rather than "". > (define_code_attr su [(sign_extend "s") (zero_extend "u")]) > diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md > index c8adc5af5d2..2d48ff3f8de 100644 > --- a/gcc/config/riscv/riscv.md > +++ b/gcc/config/riscv/riscv.md > @@ -1044,6 +1044,22 @@ > [(set_attr "type" "idiv") > (set_attr "mode" "DI")]) > > +(define_expand "divmod4" > + [(parallel > + [(set (match_operand:GPR 0 "register_operand") > + (only_div:GPR (match_operand:GPR 1 "register_operand") > + (match_operand:GPR 2 "register_operand"))) > + (set (match_operand:GPR 3 "register_operand") > + (:GPR (match_dup 1) (match_dup 2)))])] > + "TARGET_DIV" > + { > + rtx tmp = gen_reg_rtx (mode); > + emit_insn (gen_div3 (operands[0], operands[1], > operands[2])); > + emit_insn (gen_mul3 (tmp, operands[0], operands[2])); > + emit_insn (gen_sub3 (operands[3], operands[1], tmp)); > + DONE; > + }) > + > (define_insn "*si3_extended" > [(set (match_operand:DI 0 "register_operand" "=r") > (sign_extend:DI > diff --git a/gcc/testsuite/gcc.target/riscv/divmod.c > b/gcc/testsuite/gcc.target/riscv/divmod.c > new file mode 100644 > index 00000000000..254b25e654d > --- /dev/null > +++ b/gcc/testsuite/gcc.target/riscv/divmod.c > @@ -0,0 +1,14 @@ > +/* { dg-do compile } */ > +/* { dg-skip-if "" { *-*-* } { "-O0" "-O1" "-Og" } } */ > + > +void > +foo(int a, int b, int *c, int *d) > +{ > + *c = a / b; > + *d = a % b; > +} > + > +/* { dg-final { scan-assembler-not "rem" } } */ > +/* { dg-final { scan-assembler-times "mul" 1 } } */ > +/* { dg-final { scan-assembler-times "sub" 1 } } */