From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-pj1-x102f.google.com (mail-pj1-x102f.google.com [IPv6:2607:f8b0:4864:20::102f]) by sourceware.org (Postfix) with ESMTPS id E09133858C62 for ; Mon, 14 Nov 2022 20:58:08 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org E09133858C62 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=rivosinc.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=rivosinc.com Received: by mail-pj1-x102f.google.com with SMTP id v4-20020a17090a088400b00212cb0ed97eso11891145pjc.5 for ; Mon, 14 Nov 2022 12:58:08 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20210112.gappssmtp.com; s=20210112; h=content-transfer-encoding:mime-version:message-id:to:from:cc :in-reply-to:subject:date:from:to:cc:subject:date:message-id :reply-to; bh=6ztGFiX/qdGagl1uGDpQAMn9ymlvrXnUqhWcI/OM1yw=; b=VYL60fW40pF+q0Ugf5+ZKl2k0nC8Sq37JfUleu6Vc1dOzr6QNkL0f9NCtG6n4mB2lX tnnj1sB5K3i4rfHynzwK9qYxOhDmKBlXm98y0AdPVnHDVhSun0IU2qT4m0MMZjJ8dDuj HKisZkvBWpvMr7+G4/5Dy8c/7J7z4IqAlVK6jdW/aWOnfaqDjrj5TEk9Cwa+BwJwOtkD vV0dWwbfHCdAa77la7Uv324sVChj8uttcZSoGSBeGiGfitD6t7V5a6JDk795aIIjY9gR n4V7r91NSFaIg9AVmVBGCMTFphfAYJMjuxOgs/5f2ZFB3cNZY6xuAw+5epVRYoaRMCHW DO1Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:message-id:to:from:cc :in-reply-to:subject:date:x-gm-message-state:from:to:cc:subject:date :message-id:reply-to; bh=6ztGFiX/qdGagl1uGDpQAMn9ymlvrXnUqhWcI/OM1yw=; b=IWHuaXYhnulbGekACpo7g36RuHro0+gbou+dWedTz/NwsEnX48PPiwPK1XZYGDSBCo rLWiSfm1ocqKwc/bqGbJVjuvVr3feCtvkvz4mxGPJV4NS6X7XH0HlPgxt/P5WxIBsSIg eA339NBuGbOFJvk+2ZifRTuFakEzL6Ygl7NGbln9yxaQAi7sPmXo8bu+oIQVGk0ENM2i DLEU7gtSGlziBf7TLCQOJldTucpGgBGkWoeiDOQsnXM6hONjCYARn4ERsH/xO8yVbxb7 P5E5JF6HVNrhE/sB4G0THl0cX8QMfGL+/XNNGMVHeH0L4AEABBNKBl15dl7/an7c812t ya3w== X-Gm-Message-State: ANoB5pkd2xzo9nUQ7+FB5eYqKo/jsnxLLzWkmZh2BO+bWiTGMMAleRHA ctRF2gyqOvD2n9mh3oii3JXAJIu0OhNMtQ== X-Google-Smtp-Source: AA0mqf4D6kTXK3zCPnq6oZo3XquwXxcyeQNNBl95LB8/x0op1quPmg3BgRL2NO7AFsLYs7AdzPaAvw== X-Received: by 2002:a17:90a:73cd:b0:213:ce62:8e0f with SMTP id n13-20020a17090a73cd00b00213ce628e0fmr15740771pjk.44.1668459487554; Mon, 14 Nov 2022 12:58:07 -0800 (PST) Received: from localhost ([50.221.140.188]) by smtp.gmail.com with ESMTPSA id h4-20020a170902680400b0017b264a2d4asm7937652plk.44.2022.11.14.12.58.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 14 Nov 2022 12:58:06 -0800 (PST) Date: Mon, 14 Nov 2022 12:58:06 -0800 (PST) X-Google-Original-Date: Mon, 14 Nov 2022 12:58:03 PST (-0800) Subject: Re: [PATCH v2 0/2] Basic support for the Ventana VT1 w/ instruction fusion In-Reply-To: CC: gcc-patches@gcc.gnu.org, Vineet Gupta , jlaw@ventanamicro.com, Kito Cheng , christoph.muellner@vrull.eu From: Palmer Dabbelt To: philipp.tomsich@vrull.eu Message-ID: Mime-Version: 1.0 (MHng) Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 8bit X-Spam-Status: No, score=-5.8 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: On Mon, 14 Nov 2022 12:03:38 PST (-0800), philipp.tomsich@vrull.eu wrote: > On Mon, 14 Nov 2022 at 21:00, Palmer Dabbelt wrote: >> >> On Sun, 13 Nov 2022 12:48:22 PST (-0800), philipp.tomsich@vrull.eu wrote: >> > >> > This series provides support for the Ventana VT1 (a 4-way superscalar >> > rv64gc_zba_zbb_zbc_zbs_zifenci_xventanacondops core) including support >> > for the supported instruction fusion patterns. >> > >> > This includes the addition of the fusion-aware scheduling >> > infrastructure for RISC-V and implements idiom recognition for the >> > fusion patterns supported by VT1. >> > >> > Note that we don't signal support for XVentanaCondOps at this point, >> > as the XVentanaCondOps support is in-flight separately. Changing the >> > defaults for VT1 can happen late in the cycle, so no need to link the >> > two different changesets. >> > >> > Changes in v2: >> > - Rebased and changed over to .rst-based documentation >> > - Updated to catch more fusion cases >> > - Signals support for Zifencei >> > >> > Philipp Tomsich (2): >> > RISC-V: Add basic support for the Ventana-VT1 core >> > RISC-V: Add instruction fusion (for ventana-vt1) >> > >> > gcc/config/riscv/riscv-cores.def | 3 + >> > gcc/config/riscv/riscv-opts.h | 2 +- >> > gcc/config/riscv/riscv.cc | 233 ++++++++++++++++++ >> > .../risc-v-options.rst | 5 +- >> > 4 files changed, 240 insertions(+), 3 deletions(-) >> >> I guess we never really properly talked about this on the GCC mailing >> lists, but IMO it's fine to start taking code for designs that have been >> announced under the assumption that if the hardware doesn't actually >> show up according to those timelines that it will be assumed to have >> never existed and thus be removed more quickly than usual. >> >> That said, I can't find anything describing that the VT-1 exists aside >> from these patches. Is there anything that describes this design and >> when it's expected to be available? > > I have to defer to Jeff on this one. Looks like you already committed it, though: 991cfe5b30c ("RISC-V: Add instruction fusion (for ventana-vt1)") b4fca4fc70d ("RISC-V: Add basic support for the Ventana-VT1 core") We talked about this multiple times and I thought you were on board with the proposed "hardware needs to be announced" changes, did I misunderstand that?