From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-pg1-x52f.google.com (mail-pg1-x52f.google.com [IPv6:2607:f8b0:4864:20::52f]) by sourceware.org (Postfix) with ESMTPS id E5D0F3858C54 for ; Tue, 22 Mar 2022 01:13:50 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org E5D0F3858C54 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=dabbelt.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=dabbelt.com Received: by mail-pg1-x52f.google.com with SMTP id c11so11516597pgu.11 for ; Mon, 21 Mar 2022 18:13:50 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=dabbelt-com.20210112.gappssmtp.com; s=20210112; h=date:subject:in-reply-to:cc:from:to:message-id:mime-version :content-transfer-encoding; bh=8CExGP3boNCpeZv51CrQ/BCn+nKFJfnN2IYjBDG3frM=; b=VVjj8N9TA0lEa8qblyQpqaD98+OhEO8z0O0hUA/i2fdf10/ZJPbjow8dTUTn58Hc27 c4TB1/83wPzBn8JbwBWOj02FoBcBvnmsp+0CWJFloJN1KjNAt/mCvFSU6nvJVG9CXdBI pj4S4sdkmpyWK8HWks9IlB0I9zhjykuf+PqFakY5M5jSAfR2E+mpiuV6lH4eo+iO9G4C O+YCCm3y4e5EAS+Hd+YREkYuReffaFaevoqbUUD9bdjLSRCO824fScDowSRPKSKrOvMb Xx9v/Ma14l9rUtnnrZBfN8sQJN88se+oLXSjY+8btkUEVv9SIl8q1M6T8+7S63HWOydl E9Eg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:date:subject:in-reply-to:cc:from:to:message-id :mime-version:content-transfer-encoding; bh=8CExGP3boNCpeZv51CrQ/BCn+nKFJfnN2IYjBDG3frM=; b=eJQyCxHh+Nk+s358lf1tb16fTJ/29KsvCJJAAGcqea5Qk0Ovk1VceNF50f7f3FBkPd OyuwyDq4nFpMyqoPvMcEo4ZqVoIit1rQD/0BtelFAMpd4SBWypH1Q/w1jno5mAOhS1u4 lEEpUVpMZYcpvjezoL/LWFGJu6mr7yvkxtmH2JdmdycAWoE0Wt21kFYw4j11FJoQWmQK 1e/WPV348b/crBJvf6JmsXEqnkvYTmwGZbVLTOPP2aV3yRMDr60wUdPr9KEFeD7r2UmT uxxjUQUvbsoHeJqDdNeS0gMabZv24YWHEp05TS9qV2uqn1xUX/B+1YWT1IbhYUH9A41m aBxA== X-Gm-Message-State: AOAM533H1Kz1VVUPAgIEhR/juwUnrMG8BTXQXtQASxxiMGQoLVkMFBPa zSMYg1qNVt0soM39jOXuHK7NQw== X-Google-Smtp-Source: ABdhPJxl6axh6Px7qtvjXKHu5sqcRqbpx6btQ7T6oUNoCOIfgNhykNDkguFEKIviTEH3CZHTKnjirg== X-Received: by 2002:a63:fb57:0:b0:381:c29a:d966 with SMTP id w23-20020a63fb57000000b00381c29ad966mr20111868pgj.358.1647911629708; Mon, 21 Mar 2022 18:13:49 -0700 (PDT) Received: from localhost ([12.3.194.138]) by smtp.gmail.com with ESMTPSA id e13-20020a63370d000000b003810782e0cdsm16319913pga.56.2022.03.21.18.13.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 21 Mar 2022 18:13:48 -0700 (PDT) Date: Mon, 21 Mar 2022 18:13:48 -0700 (PDT) X-Google-Original-Date: Mon, 21 Mar 2022 18:13:43 PDT (-0700) Subject: Re: [PATCH] RISC-V: Implement ZTSO extension. In-Reply-To: CC: shihua@iscas.ac.cn, kito.cheng@sifive.com, cmuellner@ventanamicro.com, gcc-patches@gcc.gnu.org, Andrew Waterman From: Palmer Dabbelt To: gcc-patches@gcc.gnu.org Message-ID: Mime-Version: 1.0 (MHng) Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 8bit X-Spam-Status: No, score=-11.1 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, GIT_PATCH_0, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.4 X-Spam-Checker-Version: SpamAssassin 3.4.4 (2020-01-24) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 22 Mar 2022 01:13:53 -0000 On Thu, 17 Mar 2022 23:52:04 PDT (-0700), gcc-patches@gcc.gnu.org wrote: > Hi Shi-Hua: > > Thanks, this patch is LGTM, but I would defer that until stage 1, > because the binutils part isn't merget yet. IMO we should at least have a __riscv_ztso define, and ideally have the relevent builtins ported (atomics, fences, etc) as well. Otherwise this is really just setting a bit that makes binaries incompatible without providing any real benefit. That'll also let us work through how these mappings should be implemented, so we don't end up with issues like we did with WMO. > > On Tue, Mar 15, 2022 at 5:10 PM wrote: >> >> From: LiaoShihua >> >> ZTSO is the extension of tatol store order model. >> This extension adds no new instructions to the ISA, and you can use it with arch "ztso". >> If you use it, TSO flag will be generate in the ELF header. >> >> gcc/ChangeLog: >> >> * common/config/riscv/riscv-common.cc: define new arch. >> * config/riscv/riscv-opts.h (MASK_ZTSO): Ditto. >> (TARGET_ZTSO):Ditto. >> * config/riscv/riscv.opt:Ditto. >> >> --- >> gcc/common/config/riscv/riscv-common.cc | 4 +++- >> gcc/config/riscv/riscv-opts.h | 3 +++ >> gcc/config/riscv/riscv.opt | 3 +++ >> 3 files changed, 9 insertions(+), 1 deletion(-) >> >> diff --git a/gcc/common/config/riscv/riscv-common.cc b/gcc/common/config/riscv/riscv-common.cc >> index a904893b9ed..f4730b991d7 100644 >> --- a/gcc/common/config/riscv/riscv-common.cc >> +++ b/gcc/common/config/riscv/riscv-common.cc >> @@ -185,6 +185,8 @@ static const struct riscv_ext_version riscv_ext_version_table[] = >> {"zvl32768b", ISA_SPEC_CLASS_NONE, 1, 0}, >> {"zvl65536b", ISA_SPEC_CLASS_NONE, 1, 0}, >> >> + {"ztso", ISA_SPEC_CLASS_NONE, 0, 1}, >> + >> /* Terminate the list. */ >> {NULL, ISA_SPEC_CLASS_NONE, 0, 0} >> }; >> @@ -1080,7 +1082,7 @@ static const riscv_ext_flag_table_t riscv_ext_flag_table[] = >> {"zvl32768b", &gcc_options::x_riscv_zvl_flags, MASK_ZVL32768B}, >> {"zvl65536b", &gcc_options::x_riscv_zvl_flags, MASK_ZVL65536B}, >> >> - >> + {"ztso", &gcc_options::x_riscv_ztso_subext, MASK_ZTSO}, >> {NULL, NULL, 0} >> }; >> >> diff --git a/gcc/config/riscv/riscv-opts.h b/gcc/config/riscv/riscv-opts.h >> index 929e4e3a7c5..9cb5f2a550a 100644 >> --- a/gcc/config/riscv/riscv-opts.h >> +++ b/gcc/config/riscv/riscv-opts.h >> @@ -136,4 +136,7 @@ enum stack_protector_guard { >> #define TARGET_ZVL32768B ((riscv_zvl_flags & MASK_ZVL32768B) != 0) >> #define TARGET_ZVL65536B ((riscv_zvl_flags & MASK_ZVL65536B) != 0) >> >> +#define MASK_ZTSO (1 << 0) >> +#define TARGET_ZTSO ((riscv_ztso_subext & MASK_ZTSO) != 0) >> + >> #endif /* ! GCC_RISCV_OPTS_H */ >> diff --git a/gcc/config/riscv/riscv.opt b/gcc/config/riscv/riscv.opt >> index 9fffc08220d..6128bfa31dc 100644 >> --- a/gcc/config/riscv/riscv.opt >> +++ b/gcc/config/riscv/riscv.opt >> @@ -209,6 +209,9 @@ int riscv_vector_eew_flags >> TargetVariable >> int riscv_zvl_flags >> >> +TargetVariable >> +int riscv_ztso_subext >> + >> Enum >> Name(isa_spec_class) Type(enum riscv_isa_spec_class) >> Supported ISA specs (for use with the -misa-spec= option): >> -- >> 2.31.1.windows.1 >>