From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-pl1-x634.google.com (mail-pl1-x634.google.com [IPv6:2607:f8b0:4864:20::634]) by sourceware.org (Postfix) with ESMTPS id B283238582AC for ; Mon, 14 Nov 2022 20:00:15 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org B283238582AC Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=rivosinc.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=rivosinc.com Received: by mail-pl1-x634.google.com with SMTP id l2so11048272pld.13 for ; Mon, 14 Nov 2022 12:00:15 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20210112.gappssmtp.com; s=20210112; h=content-transfer-encoding:mime-version:message-id:to:from:cc :in-reply-to:subject:date:from:to:cc:subject:date:message-id :reply-to; bh=2xhD3/EHKqazI4v+uSr72gv44RArKKLoQ8NZ1NJj7vs=; b=LMb/HzK1/3ALoAHrdb5mNXTpMV2F3B3G839weXdMU03O2xofU9RbE0GOTbcW5CW8Ce Qa9EqXscHITXMttPW81dvjL+j976/68gZEh+92cvS+BRqljv8tmVoeQ9KyTPeDeqahvA qQKagdT03xoBnaY+3SJoC36j29wY4tl1uqlBzcR28y0EJEW6KNBJEYvRKBb6X080UqML YLUGoiXVqxrYE9oKFD2ZO/HzwoPRjlMGB7drYIQb70T3ZFA8iBROzgARECfMQVFKBa3k MCVTneSBlWdzZfCfau5CaJfF3t4wBSfizFRlZYvmZZlXeR/g9hN3VvH3CoPHKtdfMfqq ayKQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:message-id:to:from:cc :in-reply-to:subject:date:x-gm-message-state:from:to:cc:subject:date :message-id:reply-to; bh=2xhD3/EHKqazI4v+uSr72gv44RArKKLoQ8NZ1NJj7vs=; b=bPFFFYtM8xpIxaZVNDq915uyS/UoYLndhbrgWu2H0qOkS3EFF8kZ2duxUMKYeQ0AHG nJ4WZnkmQ3gZ+e7iTHVvyP1vt6vSCNPuv5TIVelO3mL2cfcmEQdnghCrq8XQS27hxqwP MZMd8jaldqpKA2hV/jgz6/uNojRvRJ0ycJbre3gC9wLj4m3ATzcdXriVtzPo4QEU1E7+ Hiice64sblqdHnRazy+p6r8p2tNlpr4ABBur9U26v6NXObdxWxMw+G9FWY8J2psbjniz zw4/ek9BIuEJpffBOca56psiPEnDpNWbafCHxhk+BUY3VHcI2tb86GfWckmkDAWpJ7/a +6Hg== X-Gm-Message-State: ANoB5pk9qgU7xIyXdAQKtUeJyR5K/n200y/R8aqvLsGPDCWp7Ek+dMEX lVYYHib+iRdjI/1dsKXKgs72yK8D3/q+Iw== X-Google-Smtp-Source: AA0mqf4xNpRM3c3qChDPB4Bv8OY0eARpbWl5h4ZkhvpScWkr63DdxkLP0bhKDBFaDO6doSNDag7fKA== X-Received: by 2002:a17:902:8e83:b0:187:2364:1dd5 with SMTP id bg3-20020a1709028e8300b0018723641dd5mr680292plb.170.1668456014402; Mon, 14 Nov 2022 12:00:14 -0800 (PST) Received: from localhost ([50.221.140.188]) by smtp.gmail.com with ESMTPSA id ju13-20020a170903428d00b001870dc3b4c0sm7962128plb.74.2022.11.14.12.00.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 14 Nov 2022 12:00:13 -0800 (PST) Date: Mon, 14 Nov 2022 12:00:13 -0800 (PST) X-Google-Original-Date: Mon, 14 Nov 2022 12:00:10 PST (-0800) Subject: Re: [PATCH v2 0/2] Basic support for the Ventana VT1 w/ instruction fusion In-Reply-To: <20221113204824.4062042-1-philipp.tomsich@vrull.eu> CC: gcc-patches@gcc.gnu.org, Vineet Gupta , jlaw@ventanamicro.com, Kito Cheng , christoph.muellner@vrull.eu, philipp.tomsich@vrull.eu From: Palmer Dabbelt To: philipp.tomsich@vrull.eu Message-ID: Mime-Version: 1.0 (MHng) Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 8bit X-Spam-Status: No, score=-5.9 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: On Sun, 13 Nov 2022 12:48:22 PST (-0800), philipp.tomsich@vrull.eu wrote: > > This series provides support for the Ventana VT1 (a 4-way superscalar > rv64gc_zba_zbb_zbc_zbs_zifenci_xventanacondops core) including support > for the supported instruction fusion patterns. > > This includes the addition of the fusion-aware scheduling > infrastructure for RISC-V and implements idiom recognition for the > fusion patterns supported by VT1. > > Note that we don't signal support for XVentanaCondOps at this point, > as the XVentanaCondOps support is in-flight separately. Changing the > defaults for VT1 can happen late in the cycle, so no need to link the > two different changesets. > > Changes in v2: > - Rebased and changed over to .rst-based documentation > - Updated to catch more fusion cases > - Signals support for Zifencei > > Philipp Tomsich (2): > RISC-V: Add basic support for the Ventana-VT1 core > RISC-V: Add instruction fusion (for ventana-vt1) > > gcc/config/riscv/riscv-cores.def | 3 + > gcc/config/riscv/riscv-opts.h | 2 +- > gcc/config/riscv/riscv.cc | 233 ++++++++++++++++++ > .../risc-v-options.rst | 5 +- > 4 files changed, 240 insertions(+), 3 deletions(-) I guess we never really properly talked about this on the GCC mailing lists, but IMO it's fine to start taking code for designs that have been announced under the assumption that if the hardware doesn't actually show up according to those timelines that it will be assumed to have never existed and thus be removed more quickly than usual. That said, I can't find anything describing that the VT-1 exists aside from these patches. Is there anything that describes this design and when it's expected to be available?