From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-pj1-x1035.google.com (mail-pj1-x1035.google.com [IPv6:2607:f8b0:4864:20::1035]) by sourceware.org (Postfix) with ESMTPS id 1401B3858280 for ; Fri, 14 Jul 2023 02:44:36 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 1401B3858280 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=dabbelt.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=dabbelt.com Received: by mail-pj1-x1035.google.com with SMTP id 98e67ed59e1d1-2657d405ad5so902199a91.1 for ; Thu, 13 Jul 2023 19:44:36 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=dabbelt-com.20221208.gappssmtp.com; s=20221208; t=1689302674; x=1691894674; h=content-transfer-encoding:mime-version:message-id:to:from:cc :in-reply-to:subject:date:from:to:cc:subject:date:message-id :reply-to; bh=32CjPr1tZahVaY2iA2u0apJZbQOdc5wFh0Qup3dcnfw=; b=3DxT5Uax13z3FPeYM4y7nfnjF67CJkCWODcQWgSfn84VXJdSVL9g9accsGfCZMff7s bYIITW29MrOjYD6VGGlh+/fNKB3lDIdaPApniRkwmfhx/NoTvCpFzv49sfhUoN224lOM BKtjgd+TOVt2iVdTOksccnZMPLc9vGmi76C68Y88XUgSfkGpdjMtDLzFQiErAxMUgzMu 4TNXubY3aEkX5fpR5pexeK7sSkpRyPqIGGAhV3evlvdIEesBZYG80EO/0dc+KZ4Rkc/n XopTY0KN4sHkA5knazUdBdjIKV5kOjAMpU/fPGpvCMayFHtubLITa6njLr6I/HWek3lt Y/aA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1689302674; x=1691894674; h=content-transfer-encoding:mime-version:message-id:to:from:cc :in-reply-to:subject:date:x-gm-message-state:from:to:cc:subject:date :message-id:reply-to; bh=32CjPr1tZahVaY2iA2u0apJZbQOdc5wFh0Qup3dcnfw=; b=bzQYYM0dzY1RditmXe88FBVnze+fDJfJe0tthaidFU/snFSY66tC+whjWh698Wokn+ FMZNZWKH8Bl2gwUA907wfD3Vg1XknBdq8h/TXBpJNuVqJX54cHY03Y0QD++zj4FdhG9Z xsIaJiGmW9OihwEJ6l7mvP8X0jD1JdmhaCwy6B8dzOEQkYR7kjrWDyQ4TyGQ2yCJ3xzx rW3FjB/IDWKtiC0RGiGzUm0BfjA97HTU5/xvoWwQ73Ir8UABznyMWj8z0MUZVsLjph3s JYtcwK9TSW5CHeGjvAJt1Kx+iFUm5tp8TZ8fRtPRtzIsuu+MR+niZUi+QwQxYHplql/v vJ1Q== X-Gm-Message-State: ABy/qLbUmYHnwJqsrBhvhbROrBWzrxFx8ba80ReJqCiqZMSe1yUYHIZ8 PFgXlXLU1f52DJnLm1iw4ij3Og== X-Google-Smtp-Source: APBJJlFhFMruW6kbYJwQpr81RQX7s/k9HHn/pw4m3d3IGySJyoaxupI6DdnR0VVtwKxhi++nCDVY6A== X-Received: by 2002:a17:90a:68c8:b0:263:4815:cb9a with SMTP id q8-20020a17090a68c800b002634815cb9amr2912464pjj.41.1689302674271; Thu, 13 Jul 2023 19:44:34 -0700 (PDT) Received: from localhost ([50.38.6.230]) by smtp.gmail.com with ESMTPSA id k17-20020a17090aaa1100b0025c2c398d33sm178081pjq.39.2023.07.13.19.44.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 13 Jul 2023 19:44:33 -0700 (PDT) Date: Thu, 13 Jul 2023 19:44:33 -0700 (PDT) X-Google-Original-Date: Thu, 13 Jul 2023 19:43:47 PDT (-0700) Subject: Re: [PATCH] RISC-V: Remove the redundant expressions in the and3. In-Reply-To: CC: lidie@eswincomputing.com, gcc-patches@gcc.gnu.org, jeffeyalaw@gmail.com From: Palmer Dabbelt To: gcc-patches@gcc.gnu.org Message-ID: Mime-Version: 1.0 (MHng) Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 8bit X-Spam-Status: No, score=-9.3 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,GIT_PATCH_0,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,TXREP,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: On Thu, 13 Jul 2023 19:41:08 PDT (-0700), gcc-patches@gcc.gnu.org wrote: > Expanding without DONE or FAIL will leave the pattern as well, so this > patch is fine IMO, so this patch LGTM, but anyway I will test this and > commit if passed :) Ah, thanks, I guess I didn't know that. This is probably fine then, but we might have some code floating around we could toss... > On Fri, Jul 14, 2023 at 10:34 AM Palmer Dabbelt wrote: >> >> On Thu, 13 Jul 2023 19:02:05 PDT (-0700), lidie@eswincomputing.com wrote: >> > When generating the gen_and3 function based on the and3 >> > template, it produces the expression emit_insn (gen_rtx_SET (operand0, >> > gen_rtx_AND (, operand1, operand2)));, which is identical to the >> > portion I removed in this patch. Therefore, the redundant portion can be >> > deleted. >> > >> > Signed-off-by: Die Li >> > >> > gcc/ChangeLog: >> > >> > * config/riscv/riscv.md: Remove redundant portion in and3. >> > --- >> > gcc/config/riscv/riscv.md | 5 ----- >> > 1 file changed, 5 deletions(-) >> > >> > diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md >> > index 7988026d129..c4f8eb9488e 100644 >> > --- a/gcc/config/riscv/riscv.md >> > +++ b/gcc/config/riscv/riscv.md >> > @@ -1491,11 +1491,6 @@ >> > DONE; >> > } >> > } >> > - else >> > - { >> > - emit_move_insn (operands[0], gen_rtx_AND (mode, operands[1], operands[2])); >> > - DONE; >> > - } >> > }) >> > >> > (define_insn "*and3" >> >> Unless I'm missing something, this will just result in no emitted >> instructions for this "and" pattern? That seems wrong, it would at >> least have to put the source into the dest -- but >> "arith_operand_or_mode_mask" can contain values that don't just result >> in an extension (like arbitrary register values, for example), so I >> think we need the "and" operation. >> >> Does this pass the regression suite? >> >> Either way, if this branch of the conditional can't trigger we should >> tighten the constraint (or at a bare minimum add a comment as to why).