From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-pl1-x632.google.com (mail-pl1-x632.google.com [IPv6:2607:f8b0:4864:20::632]) by sourceware.org (Postfix) with ESMTPS id 6870D3844061 for ; Wed, 10 Apr 2024 16:18:13 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 6870D3844061 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=dabbelt.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=dabbelt.com ARC-Filter: OpenARC Filter v1.0.0 sourceware.org 6870D3844061 Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=2607:f8b0:4864:20::632 ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1712765904; cv=none; b=hC0usYoWEMbgVMxAAl62x2WaRzLOBwrnedVkREwwZTgEHUlnVLPb74FEm6T4HqnnpHtzpT4LXPGnqTasj6uECIBMoiXjdIH3AV23MuMMSDRQ7vC2Fua/vgUSAFaolY3nCJPLS2WOVyMo6qk4vhgLmuVYMhK1UNC2ZuivehnR2xI= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1712765904; c=relaxed/simple; bh=TdpdtQbTPR3NbgP9VgdKpXo0KFG720eD59tmhiZ/PCE=; h=DKIM-Signature:Date:Subject:From:To:Message-ID:Mime-Version; b=uv+fvq5TFktMJSdpOsw2c6yGbbwINRVlXxwVl46tZVfZaq8RrLA778C//nMskfm+qDUu4CjEXQs7b37376Nx/i0Im4173SV1naee8c4yopVEtD9yr1SqQBMsp5PBjfxuW3t7Otd9qFixf/Pfom7N7Y9Gy4jX5afyhIzmY9/FX3A= ARC-Authentication-Results: i=1; server2.sourceware.org Received: by mail-pl1-x632.google.com with SMTP id d9443c01a7336-1e4f341330fso6510525ad.0 for ; Wed, 10 Apr 2024 09:18:13 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=dabbelt-com.20230601.gappssmtp.com; s=20230601; t=1712765891; x=1713370691; darn=gcc.gnu.org; h=content-transfer-encoding:mime-version:message-id:to:from:cc :in-reply-to:subject:date:from:to:cc:subject:date:message-id :reply-to; bh=B3qUW3tWNg5lD6zK9xOc2MGX5mzcVJgvTR0qDU0weUA=; b=NtQ0XbOwcTvwz8p0eSZg/htMqsxIu1hsHXkYBVQ+WH/g3aH3xVeQyWhURd0vRnKqLf 1FsAbz5UDEyRJWKpDzx+UAKD0wHSqQYFmn28By26XUwx3zOtteWtV4jct+1/rjvGkbsI hdd5h+GI9EJcvd1UmM0iG2/AxCH0RxCrOCD8u9lrdGSij/PzEoOQxzXRDl6EaP1gkd7l Z0I0op8/+wtzkPWzcpFhuFQrJc65sjgL/X0fYinKPLw57VqotgwGPBBzXbWx8qNkOQf8 Z9gcfKs1wAaogbuY8pEJKbf9jstU3OG6oce8+0zOuBl/nwCql6WdUny5HJmD3GIGJA+W 5YAA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1712765891; x=1713370691; h=content-transfer-encoding:mime-version:message-id:to:from:cc :in-reply-to:subject:date:x-gm-message-state:from:to:cc:subject:date :message-id:reply-to; bh=B3qUW3tWNg5lD6zK9xOc2MGX5mzcVJgvTR0qDU0weUA=; b=EHPTW+UWOlXUfgM5njUPQgN5yv8gfXBDzv1GG/t4AbAbsn9QQkRi8avrMrLTX/LIjP 4I3z8yeEQhNnq5neEzBTrEmwW2oHaFiNZw20W8lZLr2Mb+8CA9C6QBwspyzZFW/ux7Ek 5Y2Q1jjKa8kPPDSQaCNy1AVYhuHCW4zf91etLed/UiAqgPvL5BvJBX/6X0ECH3ng1fOr BLhMbHKh97R5YsAZwsn8q/ZD+iJaqGGY3om5mZpYhboWKq8mlbcIe5ZiVn/H9PkRHcf1 7BzlsH7iF41F/o9D+Rrc8p8vuJUvKzhJtlOb0ChLI7idwPOkJemo+H5o01GpnVlRWfPh kLuw== X-Gm-Message-State: AOJu0YxbqJ2WRRyy974EGujaEWoijxjPHwMmcddAwfF+z7zED4WiWkNz NPAfWAYyPSPz4zlEve4M1kkP8SDXxoa30xG9z0Px3DA+Bzl4nzfoQ7P8wr4g1xL1wp/hctCncvK J X-Google-Smtp-Source: AGHT+IH3YNdxXuIaqjv0idSZMuqUTFf1ORzKG6qJA7rbsWBj1ArzaIN4rbKZOcTIWIbB9/wQuTRdSw== X-Received: by 2002:a17:902:e5c3:b0:1e4:342a:b351 with SMTP id u3-20020a170902e5c300b001e4342ab351mr3741488plf.4.1712765891059; Wed, 10 Apr 2024 09:18:11 -0700 (PDT) Received: from localhost ([192.184.165.199]) by smtp.gmail.com with ESMTPSA id l9-20020a170903120900b001e469386fddsm4680526plh.40.2024.04.10.09.18.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 10 Apr 2024 09:18:10 -0700 (PDT) Date: Wed, 10 Apr 2024 09:18:10 -0700 (PDT) X-Google-Original-Date: Wed, 10 Apr 2024 09:18:08 PDT (-0700) Subject: Re: [PATCH] wwwdocs: gcc-14: Add RISC-V changes In-Reply-To: <20240410075759.994891-1-kito.cheng@sifive.com> CC: gcc-patches@gcc.gnu.org, Kito Cheng , Patrick O'Neill , jeffreyalaw@gmail.com, kito.cheng@sifive.com From: Palmer Dabbelt To: kito.cheng@sifive.com Message-ID: Mime-Version: 1.0 (MHng) Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 8bit X-Spam-Status: No, score=-8.2 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,GIT_PATCH_0,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,TLD_CHINA,TXREP,URIBL_SBL_A autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: On Wed, 10 Apr 2024 00:58:00 PDT (-0700), kito.cheng@sifive.com wrote: > --- > htdocs/gcc-14/changes.html | 155 ++++++++++++++++++++++++++++++++++++- > 1 file changed, 154 insertions(+), 1 deletion(-) > > diff --git a/htdocs/gcc-14/changes.html b/htdocs/gcc-14/changes.html > index 2d8968cf..6cbb2e8f 100644 > --- a/htdocs/gcc-14/changes.html > +++ b/htdocs/gcc-14/changes.html > @@ -739,7 +739,160 @@ __asm (".global __flmap_lock" "\n\t" > > > > - > +

RISC-V

> +
    > +
  • The SLP and loop vectorizer is now enabled for RISC-V when the vector I think "are now enabled"? > + extension is enabled, thanks to Ju-Zhe Zhong from > + RiVAI, > + Pan Li from Intel, and Robin Dapp > + from Ventana Micro for > + contributing most of the implementation!
    • > +
  • The -mrvv-max-lmul= option has been introduced for > + performance tuning of the loop vectorizer. The default value is > + -mrvv-max-lmul=m1, which limits the maximum LMUL to 1. > + The -mrvv-max-lmul=dynamic setting can dynamically select > + the maximum LMUL value based on register pressure.
    • > +
  • Atomic code generation has been improved and is now in conformance with > + the latest psABI specification, thanks to Patrick O'Neill from > + Rivos.
    • > +
  • Support for the vector intrinsics as specified in > + > + version 1.0 of the RISC-V vector intrinsic specification.
    • > +
  • Support for the experimental vector crypto intrinsics as specified in > + > + RISC-V vector intrinsic specification, thanks to Feng Wang et al. > + from ESWIN Computing
    • > +
  • Support for the T-head vector intrinsics.
    • > +
  • Support for the scalar bitmanip and scalar crypto intrinsics, thanks to > + Liao Shihua from PLCT.
    • > +
  • Support for the large code model via option -mcmodel=large, > + thanks to Kuan-Lin Chen from > + Andes Technology.
    • > +
  • Support for the standard vector calling convention variant, thanks to > + Lehua Ding from RiVAI.
    • > +
  • Supports the target attribute, which allows users to compile > + a function with specific extensions.
    • > +
  • -march= option no longer requires the architecture string > + to be in canonical order, with only a few constraints remaining: the > + architecture string must start with rv[32|64][i|g|e], and > + must use an underscore as the separator after a multi-letter extension. > +
    • > +
  • -march=help option has been introduced to dump all > + supported extensions.
    • > +
  • Added experimental support for the -mrvv-vector-bits=zvl > + option and the riscv_rvv_vector_bits attribute, which > + specify a fixed length for scalable vector types. This option is > + optimized for specific vector core implementations; however, the code > + generated with this option is NOT portable, IIUC the code is just optimized for a specific vector length, not any specific core. It's portable to other cores, just not portable to cores with different vector lengths. So I think we can soften the language a bit there, as it's not like we're emitting vendor-specific code on this one. > + thanks to Pan Li from Intel. > +
    • > +
  • Support for TLS descriptors has been introduced, which can be enabled by > + the -mtls-dialect=desc option. The default behavior can be > + configured with --with-tls=[trad|desc].
    • > +
  • Support for the TLS descriptors, this can be enabled by > + -mtls-dialect=desc and the default behavior can be configure > + by --with-tls=[trad|desc], thanks to Tatsuyuki Ishi from > + Blue Whale Systems Maybe should call out that this will require the next glibc release to function correctly? > +
    • > +
  • Support for the following standard extensions has been added: > +
      > +
    • Vector crypto extensions: > +
        > +
      • Zvbb
        • > +
      • Zvkb
        • > +
      • Zvbc
        • > +
      • Zvkg
        • > +
      • Zvkned
        • > +
      • Zvkhna
        • > +
      • Zvkhnb
        • > +
      • Zvksed
        • > +
      • Zvksh
        • > +
      • Zvkn
        • > +
      • Zvknc
        • > +
      • Zvkng
        • > +
      • Zvks
        • > +
      • Zvksc
        • > +
      • Zvksg
        • > +
      • Zvkt
        • > +
      > +
      • > +
    • Code size reduction extensions: > +
        > +
      • Zca
        • > +
      • Zcb
        • > +
      • Zce
        • > +
      • Zcf
        • > +
      • Zcd
        • > +
      • Zcmp
        • > +
      • Zcmt
        • > +
      > +
      • > +
    • Zicond
      • > +
    • Zfa
      • > +
    • Ztso
      • > +
    • Zvfbfmin
      • > +
    • Zvfhmin
      • > +
    • Zvfh
      • > +
    • Za64rs
      • > +
    • Za128rs
      • > +
    • Ziccif
      • > +
    • Ziccrse
      • > +
    • Ziccamoa
      • > +
    • Zicclsm
      • > +
    • Zic64b
      • > +
    • Smaia
      • > +
    • Smepmp
      • > +
    • Smstateen
      • > +
    • Ssaia
      • > +
    • Sscofpmf
      • > +
    • Ssstateen
      • > +
    • Sstc
      • > +
    • Svinval
      • > +
    • Svnapot
      • > +
    • Svpbmt
      • > +
    > +
    • > +
  • Support for the following vendor extensions has been added: > +
      > +
    • T-Head: > +
        > +
      • XTheadVector
        • > +
      > +
      • > +
    • CORE-V: > +
        > +
      • XCVmac
        • > +
      • XCValu
        • > +
      • XCVelw
        • > +
      • XCVsimd
        • > +
      • XCVbi
        • > +
      > +
      • > +
    • Ventana Micro: > +
        > +
      • XVentanaCondops
        • > +
      > +
      • > +
    > +
    • > +
  • The following new CPUs are supported through the -mcpu > + option (GCC identifiers in parentheses). > +
      > +
    • SiFive's X280 (sifive-x280).
      • > +
    • SiFive's P450 (sifive-p450).
      • > +
    • SiFive's P670 (sifive-p670).
      • > +
    > +
    • > +
  • The following new CPUs are supported through the -mtune > + option (GCC identifiers in parentheses). > +
      > +
    • Generic out-of-order core (generic-ooo).
      • > +
    • SiFive's P400 series (sifive-p400-series).
      • > +
    • SiFive's P600 series (sifive-p600-series).
      • > +
    • XiangShan's Nanhu microarchitecture (xiangshan-nanhu).
      • > +
    > +
    • > +
> > Thanks for doing this. This all pretty minor wording stuff, so Reviewed-by: Palmer Dabbelt Acked-by: Palmer Dabbelt Maybe next year we'll remember to ask submitters for these ;)