From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-pg1-x534.google.com (mail-pg1-x534.google.com [IPv6:2607:f8b0:4864:20::534]) by sourceware.org (Postfix) with ESMTPS id 9DAB03858416 for ; Sat, 29 Apr 2023 17:28:56 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 9DAB03858416 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=dabbelt.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=dabbelt.com Received: by mail-pg1-x534.google.com with SMTP id 41be03b00d2f7-5144a9c11c7so913256a12.2 for ; Sat, 29 Apr 2023 10:28:56 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=dabbelt-com.20221208.gappssmtp.com; s=20221208; t=1682789335; x=1685381335; h=content-transfer-encoding:mime-version:message-id:to:from:cc :in-reply-to:subject:date:from:to:cc:subject:date:message-id :reply-to; bh=GE2YQuD+y14tJumnk79A6PoeitM28qaULtLQiPNq5bs=; b=lC2Tz/XtgD5v/hiYvOG8V0MPxHt7J46PWKkptQftE+5kEknTNEoE11YLGg6SSRJz3e aprs+Z38BI0WTg/xetn9e+QHsj+iXWF9p86uG4Lb3lUEtiKlX6V1VQd7TiEcTJ1qxcdY KeUxhExZZXeKY/HAy7YElgzAnfXJySamBAsfXwP2ycfOf+cm9a77HLB3ku42EXQa+OmG fXhItOKRpU4RVHG95w1+SU2hAzG8HoDgA5W5Y+uNMj9sI/EXcKnGM+dBEYjRwSnW+1e2 SrDrVn1TNf2eBIZeQo95DYRZz1Uf5PZkpb28jmwM8fZacQW5EpSttThE0MLrdT5qC6Dd HyeQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1682789335; x=1685381335; h=content-transfer-encoding:mime-version:message-id:to:from:cc :in-reply-to:subject:date:x-gm-message-state:from:to:cc:subject:date :message-id:reply-to; bh=GE2YQuD+y14tJumnk79A6PoeitM28qaULtLQiPNq5bs=; b=TtyKGlCFSu55FgV84FbYcwDuFG+IjYLyiK5RBvhbJOwBHdV6GbcYsdvUBks1jwwy8G gJ71+nrt5GXBzyopVbK7Ae0Q9Op0XmPVf068FEQNRLOrjh7tECdgD1JpqFOAGLkum2Ji 5MPMDT4oTh1oAWHyXlBAglBqyAVRQa11Kzal+j7OXcZ++Q4Ea71z2bS21xhDYR1dUd3S jybF1jHoyLZqN0Vx5z5gDsoY/aHlOYMWcvGXLhj9xWTsLy2ZfAF3Pa8OYd2NBox5wh3f nFUpVEmCB5Prykng67uboBp//iRUWZOcoepggtQyPQ9BBlNFANm/BSmmmFtc8fWIWgwK 4EGA== X-Gm-Message-State: AC+VfDzEBDUv9ddjxFYgpiRRUZvSe5pMyLfS7+Bza7bZUEdIKmkI6Wi4 FjxQD1LOUyzcWzXzSiOMLcBoQg== X-Google-Smtp-Source: ACHHUZ58SRAYIgT3aX5CefAgS8Fvui1RoGSYaBUWVENkBpqk2LKQGjce8qUo/Vnheoswogmkrfu7bA== X-Received: by 2002:a17:902:d585:b0:1a6:6b9d:5e12 with SMTP id k5-20020a170902d58500b001a66b9d5e12mr9059777plh.8.1682789335269; Sat, 29 Apr 2023 10:28:55 -0700 (PDT) Received: from localhost ([50.221.140.188]) by smtp.gmail.com with ESMTPSA id a18-20020a170902ecd200b001a9a8983a15sm5532094plh.231.2023.04.29.10.28.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 29 Apr 2023 10:28:54 -0700 (PDT) Date: Sat, 29 Apr 2023 10:28:54 -0700 (PDT) X-Google-Original-Date: Sat, 29 Apr 2023 10:28:37 PDT (-0700) Subject: Re: [PATCH] RISC-V: Allow RVV VMS{Compare}(V1, V1) simplify to VMSET In-Reply-To: CC: jeffreyalaw@gmail.com, pan2.li@intel.com, yanzhang.wang@intel.com, gcc-patches@gcc.gnu.org, juzhe.zhong@rivai.ai, kito.cheng@sifive.com From: Palmer Dabbelt To: gcc-patches@gcc.gnu.org Message-ID: Mime-Version: 1.0 (MHng) Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 8bit X-Spam-Status: No, score=-3.1 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,TXREP,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: On Sat, 29 Apr 2023 10:21:53 PDT (-0700), gcc-patches@gcc.gnu.org wrote: > On Sat, Apr 29, 2023 at 8:06 AM Jeff Law via Gcc-patches < > gcc-patches@gcc.gnu.org> wrote: >> >> >> >> On 4/28/23 20:55, Li, Pan2 wrote: >> > Thanks Jeff for comments. >> > >> > It makes sense to me. For the EQ operator we should have CONSTM1. >> That's not the way I interpret the RVV documentation. Of course it's >> not terribly clear. I guess one could do some experiments with qemu >> or try to dig into the sail code and figure out the intent from those. QEMU specifically takes advantage of the behavior Andrew is pointing out it the spec, and will soon do so more aggressively (assuming the patches Daniel just sent out get merged). >> Does this mean s390 parts has similar issue here? Then for instructions >> like VMSEQ, we need to adjust the simplify_rtx up to a point. >> You'd have to refer to the s390 instruction set reference to understand >> precisely how the vector compares work. >> >> But as it stands this really isn't a simplify-rtx question, but a >> question of the semantics of risc-v. What happens with the high bits >> in the destination mask register is critical -- and if risc-v doesn't >> set them to all ones in this case, then that would mean that defining >> that macro is simply wrong for risc-v. > > The relevant statement in the spec is that "the tail elements are always > updated with a tail-agnostic policy". The vmset.m instruction will cause > mask register bits [0, vl-1] to be set to 1; elements [vl, VLMAX-1] will > either be undisturbed or set to 1, i.e., effectively unspecified. > >> >> jeff