From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-ot1-x333.google.com (mail-ot1-x333.google.com [IPv6:2607:f8b0:4864:20::333]) by sourceware.org (Postfix) with ESMTPS id EFD1338582A2 for ; Wed, 13 Dec 2023 03:55:26 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org EFD1338582A2 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=dabbelt.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=dabbelt.com ARC-Filter: OpenARC Filter v1.0.0 sourceware.org EFD1338582A2 Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=2607:f8b0:4864:20::333 ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1702439729; cv=none; b=aU+aN+7yUw0wdM2T1r2iSHxgriGWaDP/NBMGPUB4MxPDd7oq0cTYvGnw0g+67cv46iukvXGVE2Pxng9gsrnvwvDv1IvMpheYC5pgoRH6d8+E7LqviuIlR4H3Uc4O2LAusYUyN9nt3JqGqjKzlBiGnIWTcN8ZBS8LoDUN5SRKPBg= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1702439729; c=relaxed/simple; bh=FBEzO3jt67hsK4mJEaKq1Ix4CsSgNFPbEaaaM3+aZPE=; h=DKIM-Signature:Date:Subject:From:To:Message-ID:Mime-Version; b=mjQxcNOeNumq8/jmmmmjf32SJum8Fjfu0ZbdIsqLGX7dyp5LtC4/NE1kHiN1sS8PhvArUCTxl7tSj4ac7h0cgcotzogWGvGlL2KtdEtWL+8CaEoNan+NRpGtouBg1oNxhkoPk+U52ypE3S6FTQ0NgvXxBAha8W8nYaLzt5FnNDg= ARC-Authentication-Results: i=1; server2.sourceware.org Received: by mail-ot1-x333.google.com with SMTP id 46e09a7af769-6d9e0f0cba9so4079920a34.1 for ; Tue, 12 Dec 2023 19:55:26 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=dabbelt-com.20230601.gappssmtp.com; s=20230601; t=1702439726; x=1703044526; darn=gcc.gnu.org; h=content-transfer-encoding:mime-version:message-id:to:from:cc :in-reply-to:subject:date:from:to:cc:subject:date:message-id :reply-to; bh=c7pXP8dYPHBD5ejhXUcQfCP275rdhKutPi1W+9PKSPE=; b=TJYdIT7oMPmohsHvAHpWjD5xWiP4RqTRoif53/OQmKTzWa6WmIAtSBM5+IWMpCuNBr bxtAIoXvfFEswjL38In2aX/zsHZ7igB+6KcHwUcnSzHdwumuTPbtU/lLkqIaclDfNpDx MbotsN0EKbeiX2q4sZ45iXKAoWhHBN24gjPbVDxt7MOld0ao3vMXksEdiBQw1tX5pLI4 W+ETpgxXNIzKbsBjhHu/Elg/3F42PhZ6ZvTHuPjRDk6OagAF1r6ix4F2iYMTE//wx494 DcSiF+rZqYFDUzTXgVq6vBPgSozgjurFIGdrfiTx4dHo5Og4XX0lRmFtPUMWDk6Fh1xj JXVg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1702439726; x=1703044526; h=content-transfer-encoding:mime-version:message-id:to:from:cc :in-reply-to:subject:date:x-gm-message-state:from:to:cc:subject:date :message-id:reply-to; bh=c7pXP8dYPHBD5ejhXUcQfCP275rdhKutPi1W+9PKSPE=; b=QwdzsqHzRBLFwNx/UA5g/CD3N9fy60G9ifwuaCzLeLgPU+JU+hG+IVNPO0t38gpaY9 sGfYlSX9J2126gcNonuaN1s/KLCTY0bYLaerFprFC/7w3oGPbL4UJztuPlILMT6VMpcF XcegvWvTOiVOl89/HpnjZE3RPq5wHhHn3xmFXFbIQovTe6hWhDpKtXvp/jn5idr53tZT 4RXgT0TGkpMfcQCfhOLL8s85LcvK4RlFEZcUuTMQI3lCROpUpZFiVUF9mmaVo2adnot4 uHZPa+6pjS0KmPhGSciARkTuMa1yPGe4fgi/IGKqlKGNOpqzZXemAm84ID9IIMfubL8V BA4A== X-Gm-Message-State: AOJu0Yxsw6udKHr2FT7hacIrRfPHiQD5NtHDhD3GtN/MfkTZPHy4Qafg kP6wvWuC8Q3eg8UZuF2+nQ1BEm9HSRcfhc5FiJE= X-Google-Smtp-Source: AGHT+IGqfrczF6NYC1ZfVLyaJqpP+ARMBybs8kw25mJEq6anof0Ubp1xnqH8yLD5vYN6sz2nndblsw== X-Received: by 2002:a05:6830:151:b0:6d9:af93:54be with SMTP id j17-20020a056830015100b006d9af9354bemr6730123otp.68.1702439725682; Tue, 12 Dec 2023 19:55:25 -0800 (PST) Received: from localhost ([192.184.165.199]) by smtp.gmail.com with ESMTPSA id l5-20020a056830154500b006d87c7497e7sm2599804otp.1.2023.12.12.19.55.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 12 Dec 2023 19:55:25 -0800 (PST) Date: Tue, 12 Dec 2023 19:55:25 -0800 (PST) X-Google-Original-Date: Tue, 12 Dec 2023 19:54:43 PST (-0800) Subject: Re: [PATCH] RISC-V: Add Zvfbfmin extension to the -march= option In-Reply-To: <20231213032451.8054-1-zengxiao@eswincomputing.com> CC: gcc-patches@gcc.gnu.org, jeffreyalaw@gmail.com, research_trasio@irq.a4lg.com, Kito Cheng , pan2.li@intel.com, zengxiao@eswincomputing.com From: Palmer Dabbelt To: zengxiao@eswincomputing.com Message-ID: Mime-Version: 1.0 (MHng) Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 8bit X-Spam-Status: No, score=-10.0 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,GIT_PATCH_0,KAM_SHORT,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,TXREP,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: On Tue, 12 Dec 2023 19:24:51 PST (-0800), zengxiao@eswincomputing.com wrote: > This patch would like to add new sub extension (aka Zvfbfmin) to the > -march= option. It introduces a new data type BF16. > > Depending on different usage scenarios, the Zvfbfmin extension may > depend on 'V' or 'Zve32f'. This patch only implements dependencies > in scenario of Embedded Processor. In scenario of Application > Processor, it is necessary to explicitly indicate the dependent > 'V' extension. > > You can locate more information about Zvfbfmin from below spec doc. > > https://github.com/riscv/riscv-bfloat16/releases/download/20231027/riscv-bfloat16.pdf > > gcc/ChangeLog: > > * common/config/riscv/riscv-common.cc: > (riscv_implied_info): Add zvfbfmin item. > (riscv_ext_version_table): Ditto. > (riscv_ext_flag_table): Ditto. > * config/riscv/riscv.opt: > (MASK_ZVFBFMIN): New macro. > (MASK_VECTOR_ELEN_BF_16): Ditto. > (TARGET_ZVFBFMIN): Ditto. > > gcc/testsuite/ChangeLog: > > * gcc.target/riscv/arch-31.c: New test. > * gcc.target/riscv/arch-32.c: New test. > * gcc.target/riscv/predef-32.c: New test. > * gcc.target/riscv/predef-33.c: New test. > --- > gcc/common/config/riscv/riscv-common.cc | 4 ++ > gcc/config/riscv/riscv.opt | 4 ++ > gcc/testsuite/gcc.target/riscv/arch-31.c | 5 +++ > gcc/testsuite/gcc.target/riscv/arch-32.c | 5 +++ > gcc/testsuite/gcc.target/riscv/predef-32.c | 43 ++++++++++++++++++++++ > gcc/testsuite/gcc.target/riscv/predef-33.c | 43 ++++++++++++++++++++++ > 6 files changed, 104 insertions(+) > create mode 100644 gcc/testsuite/gcc.target/riscv/arch-31.c > create mode 100644 gcc/testsuite/gcc.target/riscv/arch-32.c > create mode 100644 gcc/testsuite/gcc.target/riscv/predef-32.c > create mode 100644 gcc/testsuite/gcc.target/riscv/predef-33.c > > diff --git a/gcc/common/config/riscv/riscv-common.cc b/gcc/common/config/riscv/riscv-common.cc > index 4d5a2f874a2..370d00b8f7a 100644 > --- a/gcc/common/config/riscv/riscv-common.cc > +++ b/gcc/common/config/riscv/riscv-common.cc > @@ -151,6 +151,7 @@ static const riscv_implied_info_t riscv_implied_info[] = > > {"zfa", "f"}, > > + {"zvfbfmin", "zve32f"}, > {"zvfhmin", "zve32f"}, > {"zvfh", "zve32f"}, > {"zvfh", "zfhmin"}, > @@ -313,6 +314,7 @@ static const struct riscv_ext_version riscv_ext_version_table[] = > > {"zfh", ISA_SPEC_CLASS_NONE, 1, 0}, > {"zfhmin", ISA_SPEC_CLASS_NONE, 1, 0}, > + {"zvfbfmin", ISA_SPEC_CLASS_NONE, 1, 0}, > {"zvfhmin", ISA_SPEC_CLASS_NONE, 1, 0}, > {"zvfh", ISA_SPEC_CLASS_NONE, 1, 0}, > > @@ -1657,6 +1659,7 @@ static const riscv_ext_flag_table_t riscv_ext_flag_table[] = > {"zve64x", &gcc_options::x_riscv_vector_elen_flags, MASK_VECTOR_ELEN_64}, > {"zve64f", &gcc_options::x_riscv_vector_elen_flags, MASK_VECTOR_ELEN_FP_32}, > {"zve64d", &gcc_options::x_riscv_vector_elen_flags, MASK_VECTOR_ELEN_FP_64}, > + {"zvfbfmin", &gcc_options::x_riscv_vector_elen_flags, MASK_VECTOR_ELEN_BF_16}, > {"zvfhmin", &gcc_options::x_riscv_vector_elen_flags, MASK_VECTOR_ELEN_FP_16}, > {"zvfh", &gcc_options::x_riscv_vector_elen_flags, MASK_VECTOR_ELEN_FP_16}, > > @@ -1692,6 +1695,7 @@ static const riscv_ext_flag_table_t riscv_ext_flag_table[] = > > {"zfhmin", &gcc_options::x_riscv_zf_subext, MASK_ZFHMIN}, > {"zfh", &gcc_options::x_riscv_zf_subext, MASK_ZFH}, > + {"zvfbfmin", &gcc_options::x_riscv_zf_subext, MASK_ZVFBFMIN}, > {"zvfhmin", &gcc_options::x_riscv_zf_subext, MASK_ZVFHMIN}, > {"zvfh", &gcc_options::x_riscv_zf_subext, MASK_ZVFH}, > > diff --git a/gcc/config/riscv/riscv.opt b/gcc/config/riscv/riscv.opt > index 59ce7106ecf..b7c0b72265e 100644 > --- a/gcc/config/riscv/riscv.opt > +++ b/gcc/config/riscv/riscv.opt > @@ -285,6 +285,8 @@ Mask(VECTOR_ELEN_FP_64) Var(riscv_vector_elen_flags) > > Mask(VECTOR_ELEN_FP_16) Var(riscv_vector_elen_flags) > > +Mask(VECTOR_ELEN_BF_16) Var(riscv_vector_elen_flags) > + > TargetVariable > int riscv_zvl_flags > > @@ -366,6 +368,8 @@ Mask(ZFHMIN) Var(riscv_zf_subext) > > Mask(ZFH) Var(riscv_zf_subext) > > +Mask(ZVFBFMIN) Var(riscv_zf_subext) > + > Mask(ZVFHMIN) Var(riscv_zf_subext) > > Mask(ZVFH) Var(riscv_zf_subext) > diff --git a/gcc/testsuite/gcc.target/riscv/arch-31.c b/gcc/testsuite/gcc.target/riscv/arch-31.c > new file mode 100644 > index 00000000000..5180753b905 > --- /dev/null > +++ b/gcc/testsuite/gcc.target/riscv/arch-31.c > @@ -0,0 +1,5 @@ > +/* { dg-do compile } */ > +/* { dg-options "-march=rv32i_zvfbfmin -mabi=ilp32f" } */ > +int foo() > +{ > +} > diff --git a/gcc/testsuite/gcc.target/riscv/arch-32.c b/gcc/testsuite/gcc.target/riscv/arch-32.c > new file mode 100644 > index 00000000000..49616832512 > --- /dev/null > +++ b/gcc/testsuite/gcc.target/riscv/arch-32.c > @@ -0,0 +1,5 @@ > +/* { dg-do compile } */ > +/* { dg-options "-march=rv64iv_zvfbfmin -mabi=lp64d" } */ > +int foo() > +{ > +} > diff --git a/gcc/testsuite/gcc.target/riscv/predef-32.c b/gcc/testsuite/gcc.target/riscv/predef-32.c > new file mode 100644 > index 00000000000..7417e0d996f > --- /dev/null > +++ b/gcc/testsuite/gcc.target/riscv/predef-32.c > @@ -0,0 +1,43 @@ > +/* { dg-do compile } */ > +/* { dg-options "-O2 -march=rv32i_zvfbfmin -mabi=ilp32f -mcmodel=medlow -misa-spec=20191213" } */ > + > +int main () { > + > +#ifndef __riscv_arch_test > +#error "__riscv_arch_test" > +#endif > + > +#if __riscv_xlen != 32 > +#error "__riscv_xlen" > +#endif > + > +#if !defined(__riscv_i) > +#error "__riscv_i" > +#endif > + > +#if !defined(__riscv_f) > +#error "__riscv_f" > +#endif > + > +#if !defined(__riscv_zvfbfmin) > +#error "__riscv_zvfbfmin" > +#endif > + > +#if defined(__riscv_v) > +#error "__riscv_v" > +#endif > + > +#if defined(__riscv_d) > +#error "__riscv_d" > +#endif > + > +#if defined(__riscv_c) > +#error "__riscv_c" > +#endif > + > +#if defined(__riscv_a) > +#error "__riscv_a" > +#endif > + > + return 0; > +} > diff --git a/gcc/testsuite/gcc.target/riscv/predef-33.c b/gcc/testsuite/gcc.target/riscv/predef-33.c > new file mode 100644 > index 00000000000..74d05bc9719 > --- /dev/null > +++ b/gcc/testsuite/gcc.target/riscv/predef-33.c > @@ -0,0 +1,43 @@ > +/* { dg-do compile } */ > +/* { dg-options "-O2 -march=rv64iv_zvfbfmin -mabi=lp64d -mcmodel=medlow -misa-spec=20191213" } */ > + > +int main () { > + > +#ifndef __riscv_arch_test > +#error "__riscv_arch_test" > +#endif > + > +#if __riscv_xlen != 64 > +#error "__riscv_xlen" > +#endif > + > +#if !defined(__riscv_i) > +#error "__riscv_i" > +#endif > + > +#if !defined(__riscv_f) > +#error "__riscv_f" > +#endif > + > +#if !defined(__riscv_d) > +#error "__riscv_d" > +#endif > + > +#if !defined(__riscv_v) > +#error "__riscv_v" > +#endif > + > +#if !defined(__riscv_zvfbfmin) > +#error "__riscv_zvfbfmin" > +#endif > + > +#if defined(__riscv_c) > +#error "__riscv_c" > +#endif > + > +#if defined(__riscv_a) > +#error "__riscv_a" > +#endif > + > + return 0; > +} Reviewed-by: Palmer Dabbelt