From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-pf1-x42f.google.com (mail-pf1-x42f.google.com [IPv6:2607:f8b0:4864:20::42f]) by sourceware.org (Postfix) with ESMTPS id 45C593857434 for ; Thu, 27 Oct 2022 20:51:34 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 45C593857434 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=dabbelt.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=dabbelt.com Received: by mail-pf1-x42f.google.com with SMTP id 192so2890691pfx.5 for ; Thu, 27 Oct 2022 13:51:34 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=dabbelt-com.20210112.gappssmtp.com; s=20210112; h=content-transfer-encoding:mime-version:message-id:to:from:cc :in-reply-to:subject:date:from:to:cc:subject:date:message-id :reply-to; bh=7FpguS4PQAPFR5gMfi8kfuLydA5hnLJu0mvOWqoihtM=; b=FokgOY0ITOONjUtv790c5n1IsGjRwXnjTWCyihhO5aR+C/CaHAKZzoU5MfI0XSa7lQ Gcik/CjkmCcf9/jMogkCURvvbKZ6ow516RHzEHw6YcQxTln8RYZyLobiAVTury/oW7uz CXLI3l4cCBIvUxrN9ubhX1czRlBnUCWxI+25JQVL1SOKlqUMqcYtwJbKHyAMcaSNs1F4 6dk38ek05fduPT6gOS9eMZEG51F0eG+SDeNhgCslbxJbBp3NBa3hUwT7MOJgOx0h69tA U9ZIgpJq9F7gMFbW81wsfATbsOjDKuzBjHmt3XdHN98IP8I9dScdhMvfVxAXCVaPSoUb bZPg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:message-id:to:from:cc :in-reply-to:subject:date:x-gm-message-state:from:to:cc:subject:date :message-id:reply-to; bh=7FpguS4PQAPFR5gMfi8kfuLydA5hnLJu0mvOWqoihtM=; b=RNWR8CD+n7bXHbylrH9Xqn9x7xBvOuINZRaC8bupzHG6D9a/tXJCLTXJK9+tckyVHZ +spS0sa2mqsxjqzTg+AB1mIscxMYV1t4r8lKDssN/qh8bhInv1tLz9pTgvjEwhVR/Qce fi/c8fNDgGs3EdP5KRDIzlwqGiK6vWdnfDBKqSoR1H52/ptgxSxt0Urq4HI+7lnksBo6 116sh+/elC1aFDBpAPtQudBJqSoDZzMNlc7tv/FQXaXoMLadPWLJeDow/DrnkZzomyOU dGNNvX/pyAm+tzvbcKmPdbxb1WuF7/0ImDOVeSSSGFOAMa2k1gNb1D9bHieV9W6WGoPC k6WA== X-Gm-Message-State: ACrzQf3NfQ5S4VCNZGMLDFUPPR+FlQtFS3pwFVqBJ8zfI64Um18XGUzn 4jjUf5agk/rrbuSreVo7J0iaFHFKiG4RVQ== X-Google-Smtp-Source: AMsMyM4U2+SEVelM51/on+bhKdPp5/NVtsX7OW3JN/mAF2k3++/7rfnNiZvV+mGkevg26NUleWEB7Q== X-Received: by 2002:a63:211d:0:b0:44e:f294:8440 with SMTP id h29-20020a63211d000000b0044ef2948440mr43159861pgh.103.1666903892476; Thu, 27 Oct 2022 13:51:32 -0700 (PDT) Received: from localhost ([50.221.140.188]) by smtp.gmail.com with ESMTPSA id v16-20020a63f210000000b0045724d09cb4sm1432725pgh.29.2022.10.27.13.51.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 27 Oct 2022 13:51:31 -0700 (PDT) Date: Thu, 27 Oct 2022 13:51:31 -0700 (PDT) X-Google-Original-Date: Thu, 27 Oct 2022 13:51:35 PDT (-0700) Subject: Re: [PATCH] RISC-V: Add Zawrs ISA extension support In-Reply-To: CC: gcc-patches@gcc.gnu.org, kito.cheng@sifive.com, Jim Wilson , Andrew Waterman , philipp.tomsich@vrull.eu, jeffreyalaw@gmail.com, Aaron Durbin , Vineet Gupta From: Palmer Dabbelt To: christoph.muellner@vrull.eu Message-ID: Mime-Version: 1.0 (MHng) Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 8bit X-Spam-Status: No, score=-10.8 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,GIT_PATCH_0,KAM_SHORT,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: On Thu, 27 Oct 2022 11:23:17 PDT (-0700), christoph.muellner@vrull.eu wrote: > On Thu, Oct 27, 2022 at 8:11 PM Christoph Muellner < > christoph.muellner@vrull.eu> wrote: > >> From: Christoph Muellner >> >> This patch adds support for the Zawrs ISA extension. >> The patch depends on the corresponding Binutils patch >> to be usable (see [1]) >> >> The specification can be found here: >> https://github.com/riscv/riscv-zawrs/blob/main/zawrs.adoc >> >> Note, that the Zawrs extension is not frozen or ratified yet. >> Therefore this patch is an RFC and not intended to get merged. >> > > Sorry, forgot to update this part: > The Zawrs extension is frozen but not ratified. > Let me know if I should send a v2 for this change of the commit msg. IMO it's fine to just fix it up at commit time. This LGTM, we just need the NEWS entry too. I also don't see any build/test results. Thanks! > Binuitls support has been merged recently: > > https://sourceware.org/git/?p=binutils-gdb.git;a=commit;h=eb668e50036e979fb0a74821df4eee0307b44e66 > > >> >> [1] https://sourceware.org/pipermail/binutils/2022-April/120559.html >> >> gcc/ChangeLog: >> >> * common/config/riscv/riscv-common.cc: Add zawrs extension. >> * config/riscv/riscv-opts.h (MASK_ZAWRS): New. >> (TARGET_ZAWRS): New. >> * config/riscv/riscv.opt: New. >> >> gcc/testsuite/ChangeLog: >> >> * gcc.target/riscv/zawrs.c: New test. >> >> Signed-off-by: Christoph Muellner >> --- >> gcc/common/config/riscv/riscv-common.cc | 4 ++++ >> gcc/config/riscv/riscv-opts.h | 3 +++ >> gcc/config/riscv/riscv.opt | 3 +++ >> gcc/testsuite/gcc.target/riscv/zawrs.c | 13 +++++++++++++ >> 4 files changed, 23 insertions(+) >> create mode 100644 gcc/testsuite/gcc.target/riscv/zawrs.c >> >> diff --git a/gcc/common/config/riscv/riscv-common.cc >> b/gcc/common/config/riscv/riscv-common.cc >> index d6404a01205..4b7f777c103 100644 >> --- a/gcc/common/config/riscv/riscv-common.cc >> +++ b/gcc/common/config/riscv/riscv-common.cc >> @@ -163,6 +163,8 @@ static const struct riscv_ext_version >> riscv_ext_version_table[] = >> {"zifencei", ISA_SPEC_CLASS_20191213, 2, 0}, >> {"zifencei", ISA_SPEC_CLASS_20190608, 2, 0}, >> >> + {"zawrs", ISA_SPEC_CLASS_NONE, 1, 0}, >> + >> {"zba", ISA_SPEC_CLASS_NONE, 1, 0}, >> {"zbb", ISA_SPEC_CLASS_NONE, 1, 0}, >> {"zbc", ISA_SPEC_CLASS_NONE, 1, 0}, >> @@ -1180,6 +1182,8 @@ static const riscv_ext_flag_table_t >> riscv_ext_flag_table[] = >> {"zicsr", &gcc_options::x_riscv_zi_subext, MASK_ZICSR}, >> {"zifencei", &gcc_options::x_riscv_zi_subext, MASK_ZIFENCEI}, >> >> + {"zawrs", &gcc_options::x_riscv_za_subext, MASK_ZAWRS}, >> + >> {"zba", &gcc_options::x_riscv_zb_subext, MASK_ZBA}, >> {"zbb", &gcc_options::x_riscv_zb_subext, MASK_ZBB}, >> {"zbc", &gcc_options::x_riscv_zb_subext, MASK_ZBC}, >> diff --git a/gcc/config/riscv/riscv-opts.h b/gcc/config/riscv/riscv-opts.h >> index 1dfe8c89209..25fd85b09b1 100644 >> --- a/gcc/config/riscv/riscv-opts.h >> +++ b/gcc/config/riscv/riscv-opts.h >> @@ -73,6 +73,9 @@ enum stack_protector_guard { >> #define TARGET_ZICSR ((riscv_zi_subext & MASK_ZICSR) != 0) >> #define TARGET_ZIFENCEI ((riscv_zi_subext & MASK_ZIFENCEI) != 0) >> >> +#define MASK_ZAWRS (1 << 0) >> +#define TARGET_ZAWRS ((riscv_za_subext & MASK_ZAWRS) != 0) >> + >> #define MASK_ZBA (1 << 0) >> #define MASK_ZBB (1 << 1) >> #define MASK_ZBC (1 << 2) >> diff --git a/gcc/config/riscv/riscv.opt b/gcc/config/riscv/riscv.opt >> index 426ea95cd14..7c3ca48d1cc 100644 >> --- a/gcc/config/riscv/riscv.opt >> +++ b/gcc/config/riscv/riscv.opt >> @@ -203,6 +203,9 @@ long riscv_stack_protector_guard_offset = 0 >> TargetVariable >> int riscv_zi_subext >> >> +TargetVariable >> +int riscv_za_subext >> + >> TargetVariable >> int riscv_zb_subext >> >> diff --git a/gcc/testsuite/gcc.target/riscv/zawrs.c >> b/gcc/testsuite/gcc.target/riscv/zawrs.c >> new file mode 100644 >> index 00000000000..0b7e2662343 >> --- /dev/null >> +++ b/gcc/testsuite/gcc.target/riscv/zawrs.c >> @@ -0,0 +1,13 @@ >> +/* { dg-do compile } */ >> +/* { dg-options "-march=rv64gc_zawrs" { target { rv64 } } } */ >> +/* { dg-options "-march=rv32gc_zawrs" { target { rv32 } } } */ >> + >> +#ifndef __riscv_zawrs >> +#error Feature macro not defined >> +#endif >> + >> +int >> +foo (int a) >> +{ >> + return a; >> +} >> -- >> 2.37.3 >> >>