From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-pl1-x62c.google.com (mail-pl1-x62c.google.com [IPv6:2607:f8b0:4864:20::62c]) by sourceware.org (Postfix) with ESMTPS id 329053858C5F for ; Thu, 9 Feb 2023 19:09:28 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 329053858C5F Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=dabbelt.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=dabbelt.com Received: by mail-pl1-x62c.google.com with SMTP id iz19so2588420plb.13 for ; Thu, 09 Feb 2023 11:09:28 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=dabbelt-com.20210112.gappssmtp.com; s=20210112; h=content-transfer-encoding:mime-version:message-id:to:from:cc :in-reply-to:subject:date:from:to:cc:subject:date:message-id :reply-to; bh=SOvzW/s+Stn2pqgOG0OJy9NBRUsi+x+M0yyIDB82xKU=; b=eibWsi86HKPuVO6Yr6ECsV/l3/yNv5FTU6r1wNABMWrGkpOAVGgarhOUTZnQDom6lg +991nm9Krj+MEtbquYgA4ozAO6LCFnQWWKCy/M4qlEhaIRLnxQxuzhD/I47vEoLEkcIK Y2DzgF/3SoULIjZOvBvyIwBvvc2OXwGIZ691Oa9uRqh6x1gdJvccCfPPabjxvTyvpbLg CR5JnsN8jcYFm8CktckW5ricD2FKAhjDooOv1/RzOhYLho/IAnp46uYtmA30YKM5qknk D7Xx+GIm3gQJb1i+hybAtE7DiVPZYrw9uzrYjdJSZfoF4xo5FCvGlUyasF8FUzk273MH N9lw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:message-id:to:from:cc :in-reply-to:subject:date:x-gm-message-state:from:to:cc:subject:date :message-id:reply-to; bh=SOvzW/s+Stn2pqgOG0OJy9NBRUsi+x+M0yyIDB82xKU=; b=Pmoi2fAVe0ORcP++WBI8H/DXcdFpAIErqYM3W4viF4Hl12CupaSGBTMYtwBFh1wZ4D byQd0eyc0818qUC8GijE17kPkXnPlx9mi5QgSvJ8bGyWLpFX8XLP3J3g1eBeUd4ASphJ Q9EV0LsUWQYaLBDF+vnWknbT4e9GrjJyZQqLtHuBrW2e2GeOmFhj0R88rg4K+OSn4Z6l TF9+k2f4TaDtR96jqF4bIobwinpric14/QzermplDmyB3lfjz2d9bFznjEc36MgAQTUE 9Zfr8bgfHo277cRo+0fn5c1wvPp69+vJVs/SXIhBRcxSI7efZ4zpSc0dSdPftFc/jtWw tCNw== X-Gm-Message-State: AO0yUKVilSCD8KNfA44DdVfbp/Vlv0Gr/tWewpuEVkcO3bd9vdR9zM4U NN3MXOMIXnTt57S7OY+3d7Pdi9AVSSsHUrNi X-Google-Smtp-Source: AK7set9r0xqc52UCw2lb0cmGZi3DLcUiTWUV5JvS0D8XCUTgDRoXMPWuuwGAhjuUAd4g+l8mH1JiMA== X-Received: by 2002:a05:6a20:e410:b0:bf:58d1:ce88 with SMTP id nh16-20020a056a20e41000b000bf58d1ce88mr2290765pzb.7.1675969766618; Thu, 09 Feb 2023 11:09:26 -0800 (PST) Received: from localhost ([50.221.140.188]) by smtp.gmail.com with ESMTPSA id m3-20020a632603000000b0049f77341db3sm1578094pgm.42.2023.02.09.11.09.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 09 Feb 2023 11:09:26 -0800 (PST) Date: Thu, 09 Feb 2023 11:09:26 -0800 (PST) X-Google-Original-Date: Thu, 09 Feb 2023 11:08:40 PST (-0800) Subject: Re: [PATCH] testsuite: adjust patterns in RISC-V tests to skip unwind table directives In-Reply-To: CC: gcc-patches@gcc.gnu.org, Kito Cheng , Andrew Waterman , Jim Wilson From: Palmer Dabbelt To: gcc-patches@gcc.gnu.org Message-ID: Mime-Version: 1.0 (MHng) Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 8bit X-Spam-Status: No, score=-10.7 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,GIT_PATCH_0,KAM_SHORT,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: On Thu, 09 Feb 2023 01:48:25 PST (-0800), gcc-patches@gcc.gnu.org wrote: > PR target/108723 > * gcc.target/riscv/shorten-memrefs-1.c: Adjust patterns to skip > over cfi directives. > * gcc.target/riscv/shorten-memrefs-2.c: Likewise. > * gcc.target/riscv/shorten-memrefs-3.c: Likewise. > * gcc.target/riscv/shorten-memrefs-4.c: Likewise. > * gcc.target/riscv/shorten-memrefs-5.c: Likewise. > * gcc.target/riscv/shorten-memrefs-6.c: Likewise. > * gcc.target/riscv/shorten-memrefs-8.c: Likewise. > --- > gcc/testsuite/gcc.target/riscv/shorten-memrefs-1.c | 4 ++-- > gcc/testsuite/gcc.target/riscv/shorten-memrefs-2.c | 8 ++++---- > gcc/testsuite/gcc.target/riscv/shorten-memrefs-3.c | 2 +- > gcc/testsuite/gcc.target/riscv/shorten-memrefs-4.c | 4 ++-- > gcc/testsuite/gcc.target/riscv/shorten-memrefs-5.c | 8 ++++---- > gcc/testsuite/gcc.target/riscv/shorten-memrefs-6.c | 2 +- > gcc/testsuite/gcc.target/riscv/shorten-memrefs-8.c | 4 ++-- > 7 files changed, 16 insertions(+), 16 deletions(-) It kind of smells like there's some better way to write these test cases, but the label->instruction matching was already there. I'm fine just taking the fix for now so Reviewed-by: Palmer Dabbelt Acked-by: Palmer Dabbelt but if anyone has ideas on how to make the tests less fragile I'm all ears. I didn't actually run the tests and I'm pretty bad at doing regexes in my head, though. If you ran them and can commit that's good with me, but LMK if you want me to. Thanks! > > diff --git a/gcc/testsuite/gcc.target/riscv/shorten-memrefs-1.c b/gcc/testsuite/gcc.target/riscv/shorten-memrefs-1.c > index f0222f46eff..cce7c80f6c1 100644 > --- a/gcc/testsuite/gcc.target/riscv/shorten-memrefs-1.c > +++ b/gcc/testsuite/gcc.target/riscv/shorten-memrefs-1.c > @@ -23,5 +23,5 @@ store2z (long long *array) > array[203] = 0; > } > > -/* { dg-final { scan-assembler-not "store1z:\n\taddi" } } */ > -/* { dg-final { scan-assembler-not "store2z:\n\taddi" } } */ > +/* { dg-final { scan-assembler-not "store1z:\n(\t?\\.\[^\n\]*\n)\taddi" } } */ > +/* { dg-final { scan-assembler-not "store2z:\n(\t?\\.\[^\n\]*\n)\taddi" } } */ > diff --git a/gcc/testsuite/gcc.target/riscv/shorten-memrefs-2.c b/gcc/testsuite/gcc.target/riscv/shorten-memrefs-2.c > index ec39104fd88..a9ddb797d06 100644 > --- a/gcc/testsuite/gcc.target/riscv/shorten-memrefs-2.c > +++ b/gcc/testsuite/gcc.target/riscv/shorten-memrefs-2.c > @@ -44,9 +44,9 @@ load2r (long long *array) > return a; > } > > -/* { dg-final { scan-assembler "store1a:\n\taddi" } } */ > +/* { dg-final { scan-assembler "store1a:\n(\t?\\.\[^\n\]*\n)*\taddi" } } */ > /* The sd insns in store2a are not rewritten because shorten_memrefs currently > only optimizes lw and sw. > -/* { dg-final { scan-assembler "store2a:\n\taddi" { xfail riscv*-*-* } } } */ > -/* { dg-final { scan-assembler "load1r:\n\taddi" } } */ > -/* { dg-final { scan-assembler "load2r:\n\taddi" } } */ > +/* { dg-final { scan-assembler "store2a:\n(\t?\\.\[^\n\]*\n)*\taddi" { xfail riscv*-*-* } } } */ > +/* { dg-final { scan-assembler "load1r:\n(\t?\\.\[^\n\]*\n)*\taddi" } } */ > +/* { dg-final { scan-assembler "load2r:\n(\t?\\.\[^\n\]*\n)*\taddi" } } */ > diff --git a/gcc/testsuite/gcc.target/riscv/shorten-memrefs-3.c b/gcc/testsuite/gcc.target/riscv/shorten-memrefs-3.c > index 50316284832..3d561124b81 100644 > --- a/gcc/testsuite/gcc.target/riscv/shorten-memrefs-3.c > +++ b/gcc/testsuite/gcc.target/riscv/shorten-memrefs-3.c > @@ -36,5 +36,5 @@ load2a (long long a0, long long a1, long long a2, long long a3, long long a4, > return sub2 (a0, a1, a2, a3, a4, 0, a); > } > > -/* { dg-final { scan-assembler-not "load1a:\n\taddi" { xfail riscv*-*-* } } } */ > +/* { dg-final { scan-assembler-not "load1a:\n(\t?\\.\[^\n\]*\n)*\taddi" { xfail riscv*-*-* } } } */ > /* { dg-final { scan-assembler-not "load2a:\n.*addi\[ \t\]*\[at\]\[0-9\],\[at\]\[0-9\],\[0-9\]*" { xfail riscv*-*-* } } } */ > diff --git a/gcc/testsuite/gcc.target/riscv/shorten-memrefs-4.c b/gcc/testsuite/gcc.target/riscv/shorten-memrefs-4.c > index d985512e2b3..26decf085fb 100644 > --- a/gcc/testsuite/gcc.target/riscv/shorten-memrefs-4.c > +++ b/gcc/testsuite/gcc.target/riscv/shorten-memrefs-4.c > @@ -23,5 +23,5 @@ store2z (long long *array) > array[203] = 0; > } > > -/* { dg-final { scan-assembler-not "store1z:\n\taddi" } } */ > -/* { dg-final { scan-assembler-not "store2z:\n\taddi" } } */ > +/* { dg-final { scan-assembler-not "store1z:\n(\t?\\.\[^\n\]*\n)\taddi" } } */ > +/* { dg-final { scan-assembler-not "store2z:\n(\t?\\.\[^\n\]*\n)\taddi" } } */ > diff --git a/gcc/testsuite/gcc.target/riscv/shorten-memrefs-5.c b/gcc/testsuite/gcc.target/riscv/shorten-memrefs-5.c > index 9217922c10d..11e858ed6da 100644 > --- a/gcc/testsuite/gcc.target/riscv/shorten-memrefs-5.c > +++ b/gcc/testsuite/gcc.target/riscv/shorten-memrefs-5.c > @@ -44,11 +44,11 @@ load2r (long long *array) > return a; > } > > -/* { dg-final { scan-assembler "store1a:\n\taddi" } } */ > +/* { dg-final { scan-assembler "store1a:\n(\t?\\.\[^\n\]*\n)*\taddi" } } */ > /* The sd insns in store2a are not rewritten because shorten_memrefs currently > only optimizes lw and sw. > -/* { dg-final { scan-assembler "store2a:\n\taddi" { xfail riscv*-*-* } } } */ > -/* { dg-final { scan-assembler "load1r:\n\taddi" } } */ > +/* { dg-final { scan-assembler "store2a:\n(\t?\\.\[^\n\]*\n)*\taddi" { xfail riscv*-*-* } } } */ > +/* { dg-final { scan-assembler "load1r:\n(\t?\\.\[^\n\]*\n)*\taddi" } } */ > /* The ld insns in load2r are not rewritten because shorten_memrefs currently > only optimizes lw and sw. > -/* { dg-final { scan-assembler "load2r:\n\taddi" { xfail riscv*-*-* } } } */ > +/* { dg-final { scan-assembler "load2r:\n(\t?\\.\[^\n\]*\n)*\taddi" { xfail riscv*-*-* } } } */ > diff --git a/gcc/testsuite/gcc.target/riscv/shorten-memrefs-6.c b/gcc/testsuite/gcc.target/riscv/shorten-memrefs-6.c > index c36af6d6a5d..b6539b76aaf 100644 > --- a/gcc/testsuite/gcc.target/riscv/shorten-memrefs-6.c > +++ b/gcc/testsuite/gcc.target/riscv/shorten-memrefs-6.c > @@ -36,5 +36,5 @@ load2a (long long a0, long long a1, long long a2, long long a3, long long a4, > return sub2 (a0, a1, a2, a3, a4, 0, a); > } > > -/* { dg-final { scan-assembler-not "load1a:\n\taddi" { xfail riscv*-*-* } } } */ > +/* { dg-final { scan-assembler-not "load1a:\n(\t?\\.\[^\n\]*\n)*\taddi" { xfail riscv*-*-* } } } */ > /* { dg-final { scan-assembler-not "load2a:\n.*addi\[ \t\]*\[at\]\[0-9\],\[at\]\[0-9\],\[0-9\]*" } } */ > diff --git a/gcc/testsuite/gcc.target/riscv/shorten-memrefs-8.c b/gcc/testsuite/gcc.target/riscv/shorten-memrefs-8.c > index 6dfc015cf3a..3ff6956b33e 100644 > --- a/gcc/testsuite/gcc.target/riscv/shorten-memrefs-8.c > +++ b/gcc/testsuite/gcc.target/riscv/shorten-memrefs-8.c > @@ -23,6 +23,6 @@ load (char *p) > return a; > } > > -/* { dg-final { scan-assembler "store:\n\taddi\ta\[0-7\],a\[0-7\],1" } } */ > -/* { dg-final { scan-assembler "load:\n\taddi\ta\[0-7\],a\[0-7\],1" } } */ > +/* { dg-final { scan-assembler "store:\n(\t?\\.\[^\n\]*\n)*\taddi\ta\[0-7\],a\[0-7\],1" } } */ > +/* { dg-final { scan-assembler "load:\n(\t?\\.\[^\n\]*\n)*\taddi\ta\[0-7\],a\[0-7\],1" } } */