From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-pj1-x102d.google.com (mail-pj1-x102d.google.com [IPv6:2607:f8b0:4864:20::102d]) by sourceware.org (Postfix) with ESMTPS id 92AC3385454D for ; Thu, 17 Nov 2022 23:56:39 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 92AC3385454D Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=rivosinc.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=rivosinc.com Received: by mail-pj1-x102d.google.com with SMTP id k2-20020a17090a4c8200b002187cce2f92so1618163pjh.2 for ; Thu, 17 Nov 2022 15:56:39 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20210112.gappssmtp.com; s=20210112; h=content-transfer-encoding:mime-version:message-id:to:from:cc :in-reply-to:subject:date:from:to:cc:subject:date:message-id :reply-to; bh=meU5Zo9P5wqKyxtJ1dSB0hL+TzjDMw74Y03YgS+8jgk=; b=PCL+Tn0biHEcVT0coFIOnovOsoGS9U5IUSwVYifLLjECVT8pRFsyrm5Qv0uoq6iXic q744+NtjRwsn5Jfo52YyAcUgPjuAe7jjVdsXAIzITOj2UjQ8BPBZmsOgV2e6PjlA2pl6 AUoxdFsOLSeY/pZzI3hA1KUgpr53a6CH/FpDIupCQaGPIbfVvwkPsz/QqzYr5v+JgB1v HS9AXUXFqwwPJ5qZvEeWwrX7BFJk3gdtyI6xM4O+17/pXE2ee8aslkvAWdM6Vdb1sNF1 syD2jgsJTnLxmbzuby0oxwutfr7zrVfuAeyPebckx8MxbdPbkvknkcUWrK0pd11TdHN1 aECQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:message-id:to:from:cc :in-reply-to:subject:date:x-gm-message-state:from:to:cc:subject:date :message-id:reply-to; bh=meU5Zo9P5wqKyxtJ1dSB0hL+TzjDMw74Y03YgS+8jgk=; b=3YvK5dcxHNtplIFALmXWLD0gSwbGPp5/qk+i1CxujiwZ0cTCiJRPw2CRcwFPhPp9PD 72TCbosIzwl8nhO3CCfAvunVHc/y0RlrL2IwuREWk6EYZ7LO/9rxEabtKPuqKP6Uy1y8 gmlV21px+eKhpSg94PB2JpN7pUXToCvQEpp/sDLyS9H6ywi+5d00gYRvtAEnV5RMU4fo lqANVjpn4mqzt+PGK4Jw5T/UqppDbjt6P7oKnljGrvt3h/BdknYhnlRh925zris3W+Hw 9JRNEf8Ih890Y+Pq9GUJFExb/iIPegAzFYvJqGnWSt9NekoeU9P4gzjvjTlzCm/WBCbW 7qWw== X-Gm-Message-State: ANoB5pmjU0PnXJPgm3EftflaI3thn9EXmZ2CRBXNuobe4G32Ua3VNANL x6o9n+ay/qChTR1FbKN+jnf9lw== X-Google-Smtp-Source: AA0mqf4QwMK7/sLdDnszwi2Qls3yTRwNYBnmIWqGzfI/m45AYOsJbRKxZ+K4V9x7i++mj5FNK3aeow== X-Received: by 2002:a17:902:aa93:b0:17c:892e:7c8e with SMTP id d19-20020a170902aa9300b0017c892e7c8emr5011492plr.92.1668729398464; Thu, 17 Nov 2022 15:56:38 -0800 (PST) Received: from localhost ([50.221.140.188]) by smtp.gmail.com with ESMTPSA id t15-20020a1709027fcf00b00186a8085382sm789286plb.43.2022.11.17.15.56.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 17 Nov 2022 15:56:38 -0800 (PST) Date: Thu, 17 Nov 2022 15:56:38 -0800 (PST) X-Google-Original-Date: Thu, 17 Nov 2022 15:56:33 PST (-0800) Subject: Re: [PATCH 4/7] RISC-V: Recognize sign-extract + and cases for XVentanaCondOps In-Reply-To: CC: philipp.tomsich@vrull.eu, gcc-patches@gcc.gnu.org, Vineet Gupta , christoph.muellner@vrull.eu, Kito Cheng , jlaw@ventanamicro.com From: Palmer Dabbelt To: gcc-patches@gcc.gnu.org Message-ID: Mime-Version: 1.0 (MHng) Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 8bit X-Spam-Status: No, score=-11.8 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,GIT_PATCH_0,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: On Thu, 17 Nov 2022 15:41:26 PST (-0800), gcc-patches@gcc.gnu.org wrote: > > On 11/12/22 14:29, Philipp Tomsich wrote: >> Users might use explicit arithmetic operations to create a mask and >> then and it, in a sequence like >> cond = (bits >> SHIFT) & 1; >> mask = ~(cond - 1); >> val &= mask; >> which will present as a single-bit sign-extract. >> >> Dependening on what combination of XVentanaCondOps and Zbs are >> available, this will map to the following sequences: >> - bexti + vt.maskc, if both Zbs and XVentanaCondOps are present >> - andi + vt.maskc, if only XVentanaCondOps is available and the >> sign-extract is operating on bits 10:0 (bit >> 11 can't be reached, as the immediate is >> sign-extended) >> - slli + srli + and, otherwise. >> >> gcc/ChangeLog: >> >> * config/riscv/xventanacondops.md: Recognize SIGN_EXTRACT >> of a single-bit followed by AND for XVentanaCondOps. >> >> Signed-off-by: Philipp Tomsich >> --- >> >> gcc/config/riscv/xventanacondops.md | 46 +++++++++++++++++++++++++++++ >> 1 file changed, 46 insertions(+) >> >> diff --git a/gcc/config/riscv/xventanacondops.md b/gcc/config/riscv/xventanacondops.md >> index 7930ef1d837..3e9d5833a4b 100644 >> --- a/gcc/config/riscv/xventanacondops.md >> +++ b/gcc/config/riscv/xventanacondops.md >> @@ -73,3 +73,49 @@ >> "TARGET_XVENTANACONDOPS" >> [(set (match_dup 5) (match_dup 1)) >> (set (match_dup 0) (and:X (neg:X (ne:X (match_dup 5) (const_int 0))) >> + >> +;; Users might use explicit arithmetic operations to create a mask and >> +;; then and it, in a sequence like > > Nit.  Seems like a word is missing.  "make and then and it"?? > > > Do we really care about TARGET_XVENTANACONDOPS && ! TARGET_ZBS? I guess that's really more of a question for the Ventana folks, but assuming all the Ventana widgets have Zbs then it seems reasonable to just couple them -- there's already enough options in RISC-V land to test everything, might as well make sure what slips through the cracks isn't being built. Probably best to have a comment saying why here, and then something to enforce the dependency in -march (either as an implict extension dependency, or just a warning/error) so users don't get tripped up on configs that aren't expected to work. > If there's a good reason to care about the !TARGET_ZBS case, then OK > with the nit fixed.   If we agree that the !TARGET_ZBS case isn't all > that important, then obviously OK with that pattern removed too. > > I'm about out of oomph today.  I may take a look at 7/7 tonight though.  > Given it hits target independent code we probably want to get resolution > on that patch sooner rather than later. Thanks, there's no way we would have gotten this all sorted out so fast without the help!