* [PATCH PR96357][GCC][AArch64]: could not split insn UNSPEC_COND_FSUB with AArch64 SVE @ 2020-08-19 5:49 Przemyslaw Wirkus 2020-08-19 10:32 ` Richard Sandiford 0 siblings, 1 reply; 8+ messages in thread From: Przemyslaw Wirkus @ 2020-08-19 5:49 UTC (permalink / raw) To: gcc-patches Cc: Richard Earnshaw, Richard Sandiford, Marcus Shawcroft, Kyrylo Tkachov [-- Attachment #1: Type: text/plain, Size: 914 bytes --] Hi, Problem is related to that operand 4 (In original pattern *cond_sub<mode>_any_const) is no longer the same as operand 1, and so the pattern doesn't match the split condition. Pattern *cond_sub<mode>_any_const is being split by this patch into two separate patterns: * Pattern *cond_sub<mode>_relaxed_const now matches const_int SVE_RELAXED_GP operand. * Pattern *cond_sub<mode>_strict_const now matches const_int SVE_STRICT_GP operand. * Remove aarch64_sve_pred_dominates_p condition from both patterns. Bootstrapped and tested on aarch64-none-linux-gnu. OK for master? Cheers, Przemyslaw gcc/ChangeLog: PR target/96357 * config/aarch64/aarch64-sve.md (*cond_sub<mode>_relaxed_const): Updated and renamed from *cond_sub<mode>_any_const pattern. (*cond_sub<mode>_strict_const): New pattern. gcc/testsuite/ChangeLog: * gcc.target/aarch64/sve/pr96357.c: New test. [-- Attachment #2: rb13393.patch --] [-- Type: application/octet-stream, Size: 4042 bytes --] diff --git a/gcc/config/aarch64/aarch64-sve.md b/gcc/config/aarch64/aarch64-sve.md index 9d06bf719b5bd2d3405db89d49f9b4a4b893cee8..efd046bffd1507b2d5820cd2afd13ae3eee3d9f7 100644 --- a/gcc/config/aarch64/aarch64-sve.md +++ b/gcc/config/aarch64/aarch64-sve.md @@ -5234,21 +5234,20 @@ (define_insn_and_rewrite "*cond_sub<mode>_3_const" ;; Predicated floating-point subtraction from a constant, merging with an ;; independent value. -(define_insn_and_rewrite "*cond_sub<mode>_any_const" +(define_insn_and_rewrite "*cond_sub<mode>_relaxed_const" [(set (match_operand:SVE_FULL_F 0 "register_operand" "=w, w, ?w") (unspec:SVE_FULL_F [(match_operand:<VPRED> 1 "register_operand" "Upl, Upl, Upl") (unspec:SVE_FULL_F [(match_operand 5) - (match_operand:SI 6 "aarch64_sve_gp_strictness") + (const_int SVE_RELAXED_GP) (match_operand:SVE_FULL_F 2 "aarch64_sve_float_arith_immediate") (match_operand:SVE_FULL_F 3 "register_operand" "w, w, w")] UNSPEC_COND_FSUB) (match_operand:SVE_FULL_F 4 "aarch64_simd_reg_or_zero" "Dz, 0, w")] UNSPEC_SEL))] "TARGET_SVE - && !rtx_equal_p (operands[3], operands[4]) - && aarch64_sve_pred_dominates_p (&operands[5], operands[1])" + && !rtx_equal_p (operands[3], operands[4])" "@ movprfx\t%0.<Vetype>, %1/z, %3.<Vetype>\;fsubr\t%0.<Vetype>, %1/m, %0.<Vetype>, #%2 movprfx\t%0.<Vetype>, %1/m, %3.<Vetype>\;fsubr\t%0.<Vetype>, %1/m, %0.<Vetype>, #%2 @@ -5271,6 +5270,43 @@ (define_insn_and_rewrite "*cond_sub<mode>_any_const" [(set_attr "movprfx" "yes")] ) +;; Predicated floating-point subtraction from a constant, merging with an +;; independent value. +(define_insn_and_rewrite "*cond_sub<mode>_strict_const" + [(set (match_operand:SVE_FULL_F 0 "register_operand" "=w, w, ?w") + (unspec:SVE_FULL_F + [(match_operand:<VPRED> 1 "register_operand" "Upl, Upl, Upl") + (unspec:SVE_FULL_F + [(match_dup 1) + (const_int SVE_STRICT_GP) + (match_operand:SVE_FULL_F 2 "aarch64_sve_float_arith_immediate") + (match_operand:SVE_FULL_F 3 "register_operand" "w, w, w")] + UNSPEC_COND_FSUB) + (match_operand:SVE_FULL_F 4 "aarch64_simd_reg_or_zero" "Dz, 0, w")] + UNSPEC_SEL))] + "TARGET_SVE + && !rtx_equal_p (operands[3], operands[4])" + "@ + movprfx\t%0.<Vetype>, %1/z, %3.<Vetype>\;fsubr\t%0.<Vetype>, %1/m, %0.<Vetype>, #%2 + movprfx\t%0.<Vetype>, %1/m, %3.<Vetype>\;fsubr\t%0.<Vetype>, %1/m, %0.<Vetype>, #%2 + #" + "&& 1" + { + if (reload_completed + && register_operand (operands[4], <MODE>mode) + && !rtx_equal_p (operands[0], operands[4])) + { + emit_insn (gen_vcond_mask_<mode><vpred> (operands[0], operands[3], + operands[4], operands[1])); + operands[4] = operands[3] = operands[0]; + } + else if (!rtx_equal_p (operands[1], operands[5])) + operands[5] = copy_rtx (operands[1]); + else + FAIL; + } + [(set_attr "movprfx" "yes")] +) ;; Register merging forms are handled through SVE_COND_FP_BINARY. ;; ------------------------------------------------------------------------- diff --git a/gcc/testsuite/gcc.target/aarch64/sve/pr96357.c b/gcc/testsuite/gcc.target/aarch64/sve/pr96357.c new file mode 100644 index 0000000000000000000000000000000000000000..e52867f57291d4a5d9a7d7c0d64e92efc8b28cfe --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/pr96357.c @@ -0,0 +1,25 @@ +/* { dg-do compile } */ +/* { dg-options "-O3 -march=armv8.2-a+sve" } */ + +int d; + +void +f1(char f, char *g, char *h, char *l, char *n) { + double i = d, j = 1.0 - f, k = j ? d : j; + if (k == 1.0) + i = 0.0; + *l = *n = *g = *h = i * 0.5; +} + +void +f2() { + int a, m, c; + for (c = 2048; c; c--) { + char b = a++; + f1(b, m, m + 1, m + 2, m + 3); /*{ dg-warning {passing argument [0-9]+ of 'f1' makes pointer from integer without a cast} } */ + m += 4; + } +} + +/* { dg-final { scan-assembler {\tmovprfx\tz[0-9]+, z[0-9]+} } } */ +/* { dg-final { scan-assembler {\tfsubr\tz[0-9]+\.d, p[0-7]/m, z[0-9]+\.d, #1.0} } } */ ^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH PR96357][GCC][AArch64]: could not split insn UNSPEC_COND_FSUB with AArch64 SVE 2020-08-19 5:49 [PATCH PR96357][GCC][AArch64]: could not split insn UNSPEC_COND_FSUB with AArch64 SVE Przemyslaw Wirkus @ 2020-08-19 10:32 ` Richard Sandiford 2020-08-25 8:56 ` Przemyslaw Wirkus 0 siblings, 1 reply; 8+ messages in thread From: Richard Sandiford @ 2020-08-19 10:32 UTC (permalink / raw) To: Przemyslaw Wirkus Cc: gcc-patches, Richard Earnshaw, Marcus Shawcroft, Kyrylo Tkachov Przemyslaw Wirkus <Przemyslaw.Wirkus@arm.com> writes: > Hi, > > Problem is related to that operand 4 (In original pattern > *cond_sub<mode>_any_const) is no longer the same as operand 1, and so > the pattern doesn't match the split condition. > > Pattern *cond_sub<mode>_any_const is being split by this patch into two > separate patterns: > * Pattern *cond_sub<mode>_relaxed_const now matches const_int > SVE_RELAXED_GP operand. > * Pattern *cond_sub<mode>_strict_const now matches const_int > SVE_STRICT_GP operand. > * Remove aarch64_sve_pred_dominates_p condition from both patterns. Thanks for doing this. > @@ -5271,6 +5270,43 @@ (define_insn_and_rewrite "*cond_sub<mode>_any_const" > [(set_attr "movprfx" "yes")] > ) > > +;; Predicated floating-point subtraction from a constant, merging with an > +;; independent value. The previous pattern had the same comment. Maybe add: The subtraction predicate and the merge predicate are allowed to be different. to the relaxed one and: The subtraction predicate and the merge predicate must be the same. to this one. > +(define_insn_and_rewrite "*cond_sub<mode>_strict_const" > + [(set (match_operand:SVE_FULL_F 0 "register_operand" "=w, w, ?w") > + (unspec:SVE_FULL_F > + [(match_operand:<VPRED> 1 "register_operand" "Upl, Upl, Upl") > + (unspec:SVE_FULL_F > + [(match_dup 1) > + (const_int SVE_STRICT_GP) > + (match_operand:SVE_FULL_F 2 "aarch64_sve_float_arith_immediate") > + (match_operand:SVE_FULL_F 3 "register_operand" "w, w, w")] > + UNSPEC_COND_FSUB) > + (match_operand:SVE_FULL_F 4 "aarch64_simd_reg_or_zero" "Dz, 0, w")] > + UNSPEC_SEL))] > + "TARGET_SVE > + && !rtx_equal_p (operands[3], operands[4])" Very minor, but the file generally puts conditions on a single line if they'll fit. Same for the relaxed version. > + "@ > + movprfx\t%0.<Vetype>, %1/z, %3.<Vetype>\;fsubr\t%0.<Vetype>, %1/m, %0.<Vetype>, #%2 > + movprfx\t%0.<Vetype>, %1/m, %3.<Vetype>\;fsubr\t%0.<Vetype>, %1/m, %0.<Vetype>, #%2 > + #" > + "&& 1" > + { > + if (reload_completed > + && register_operand (operands[4], <MODE>mode) > + && !rtx_equal_p (operands[0], operands[4])) > + { > + emit_insn (gen_vcond_mask_<mode><vpred> (operands[0], operands[3], > + operands[4], operands[1])); > + operands[4] = operands[3] = operands[0]; > + } > + else if (!rtx_equal_p (operands[1], operands[5])) > + operands[5] = copy_rtx (operands[1]); The last two lines are a hold-over from the relaxed version, where there were two predicates. There's no operand 5 in this pattern, so we should just delete the lines. Thanks, Richard ^ permalink raw reply [flat|nested] 8+ messages in thread
* RE: [PATCH PR96357][GCC][AArch64]: could not split insn UNSPEC_COND_FSUB with AArch64 SVE 2020-08-19 10:32 ` Richard Sandiford @ 2020-08-25 8:56 ` Przemyslaw Wirkus 2020-08-25 11:14 ` Richard Sandiford 0 siblings, 1 reply; 8+ messages in thread From: Przemyslaw Wirkus @ 2020-08-25 8:56 UTC (permalink / raw) To: Richard Sandiford Cc: gcc-patches, Richard Earnshaw, Marcus Shawcroft, Kyrylo Tkachov [-- Attachment #1: Type: text/plain, Size: 3508 bytes --] Hi Richard, Thank you for your comments. I've attached updated patch with changes reflecting your comments. Kind regards, Przemyslaw > -----Original Message----- > From: Richard Sandiford <richard.sandiford@arm.com> > Sent: 19 August 2020 11:32 > To: Przemyslaw Wirkus <Przemyslaw.Wirkus@arm.com> > Cc: gcc-patches@gcc.gnu.org; Richard Earnshaw > <Richard.Earnshaw@arm.com>; Marcus Shawcroft > <Marcus.Shawcroft@arm.com>; Kyrylo Tkachov <Kyrylo.Tkachov@arm.com> > Subject: Re: [PATCH PR96357][GCC][AArch64]: could not split insn > UNSPEC_COND_FSUB with AArch64 SVE > > Przemyslaw Wirkus <Przemyslaw.Wirkus@arm.com> writes: > > Hi, > > > > Problem is related to that operand 4 (In original pattern > > *cond_sub<mode>_any_const) is no longer the same as operand 1, and so > > the pattern doesn't match the split condition. > > > > Pattern *cond_sub<mode>_any_const is being split by this patch into > > two separate patterns: > > * Pattern *cond_sub<mode>_relaxed_const now matches const_int > > SVE_RELAXED_GP operand. > > * Pattern *cond_sub<mode>_strict_const now matches const_int > > SVE_STRICT_GP operand. > > * Remove aarch64_sve_pred_dominates_p condition from both patterns. > > Thanks for doing this. > > > @@ -5271,6 +5270,43 @@ (define_insn_and_rewrite > "*cond_sub<mode>_any_const" > > [(set_attr "movprfx" "yes")] > > ) > > > > +;; Predicated floating-point subtraction from a constant, merging > > +with an ;; independent value. > > The previous pattern had the same comment. Maybe add: > > The subtraction predicate and the merge predicate are allowed to be > different. > > to the relaxed one and: > > The subtraction predicate and the merge predicate must be the same. > > to this one. > > > +(define_insn_and_rewrite "*cond_sub<mode>_strict_const" > > + [(set (match_operand:SVE_FULL_F 0 "register_operand" "=w, w, ?w") > > + (unspec:SVE_FULL_F > > + [(match_operand:<VPRED> 1 "register_operand" "Upl, Upl, Upl") > > + (unspec:SVE_FULL_F > > + [(match_dup 1) > > + (const_int SVE_STRICT_GP) > > + (match_operand:SVE_FULL_F 2 > "aarch64_sve_float_arith_immediate") > > + (match_operand:SVE_FULL_F 3 "register_operand" "w, w, w")] > > + UNSPEC_COND_FSUB) > > + (match_operand:SVE_FULL_F 4 "aarch64_simd_reg_or_zero" "Dz, 0, > w")] > > + UNSPEC_SEL))] > > + "TARGET_SVE > > + && !rtx_equal_p (operands[3], operands[4])" > > Very minor, but the file generally puts conditions on a single line if they'll fit. > Same for the relaxed version. > > > + "@ > > + > movprfx\t%0.<Vetype>, %1/z, %3.<Vetype>\;fsubr\t%0.<Vetype>, %1/m, %0.< > Vetype>, #%2 > > + > movprfx\t%0.<Vetype>, %1/m, %3.<Vetype>\;fsubr\t%0.<Vetype>, %1/m, %0. > <Vetype>, #%2 > > + #" > > + "&& 1" > > + { > > + if (reload_completed > > + && register_operand (operands[4], <MODE>mode) > > + && !rtx_equal_p (operands[0], operands[4])) > > + { > > + emit_insn (gen_vcond_mask_<mode><vpred> (operands[0], > operands[3], > > + operands[4], operands[1])); > > + operands[4] = operands[3] = operands[0]; > > + } > > + else if (!rtx_equal_p (operands[1], operands[5])) > > + operands[5] = copy_rtx (operands[1]); > > The last two lines are a hold-over from the relaxed version, where there were > two predicates. There's no operand 5 in this pattern, so we should just delete > the lines. > > Thanks, > Richard [-- Attachment #2: rb13404.patch --] [-- Type: application/octet-stream, Size: 4108 bytes --] diff --git a/gcc/config/aarch64/aarch64-sve.md b/gcc/config/aarch64/aarch64-sve.md index 9d06bf719b5bd2d3405db89d49f9b4a4b893cee8..a6d76f58b0358b3678b8c15096048353ea0708d0 100644 --- a/gcc/config/aarch64/aarch64-sve.md +++ b/gcc/config/aarch64/aarch64-sve.md @@ -5234,21 +5234,21 @@ (define_insn_and_rewrite "*cond_sub<mode>_3_const" ;; Predicated floating-point subtraction from a constant, merging with an ;; independent value. -(define_insn_and_rewrite "*cond_sub<mode>_any_const" +;; The subtraction predicate and the merge predicate are allowed to be +;; different. +(define_insn_and_rewrite "*cond_sub<mode>_relaxed_const" [(set (match_operand:SVE_FULL_F 0 "register_operand" "=w, w, ?w") (unspec:SVE_FULL_F [(match_operand:<VPRED> 1 "register_operand" "Upl, Upl, Upl") (unspec:SVE_FULL_F [(match_operand 5) - (match_operand:SI 6 "aarch64_sve_gp_strictness") + (const_int SVE_RELAXED_GP) (match_operand:SVE_FULL_F 2 "aarch64_sve_float_arith_immediate") (match_operand:SVE_FULL_F 3 "register_operand" "w, w, w")] UNSPEC_COND_FSUB) (match_operand:SVE_FULL_F 4 "aarch64_simd_reg_or_zero" "Dz, 0, w")] UNSPEC_SEL))] - "TARGET_SVE - && !rtx_equal_p (operands[3], operands[4]) - && aarch64_sve_pred_dominates_p (&operands[5], operands[1])" + "TARGET_SVE && !rtx_equal_p (operands[3], operands[4])" "@ movprfx\t%0.<Vetype>, %1/z, %3.<Vetype>\;fsubr\t%0.<Vetype>, %1/m, %0.<Vetype>, #%2 movprfx\t%0.<Vetype>, %1/m, %3.<Vetype>\;fsubr\t%0.<Vetype>, %1/m, %0.<Vetype>, #%2 @@ -5271,6 +5271,41 @@ (define_insn_and_rewrite "*cond_sub<mode>_any_const" [(set_attr "movprfx" "yes")] ) +;; Predicated floating-point subtraction from a constant, merging with an +;; independent value. +;; The subtraction predicate and the merge predicate must be the same. +(define_insn_and_rewrite "*cond_sub<mode>_strict_const" + [(set (match_operand:SVE_FULL_F 0 "register_operand" "=w, w, ?w") + (unspec:SVE_FULL_F + [(match_operand:<VPRED> 1 "register_operand" "Upl, Upl, Upl") + (unspec:SVE_FULL_F + [(match_dup 1) + (const_int SVE_STRICT_GP) + (match_operand:SVE_FULL_F 2 "aarch64_sve_float_arith_immediate") + (match_operand:SVE_FULL_F 3 "register_operand" "w, w, w")] + UNSPEC_COND_FSUB) + (match_operand:SVE_FULL_F 4 "aarch64_simd_reg_or_zero" "Dz, 0, w")] + UNSPEC_SEL))] + "TARGET_SVE && !rtx_equal_p (operands[3], operands[4])" + "@ + movprfx\t%0.<Vetype>, %1/z, %3.<Vetype>\;fsubr\t%0.<Vetype>, %1/m, %0.<Vetype>, #%2 + movprfx\t%0.<Vetype>, %1/m, %3.<Vetype>\;fsubr\t%0.<Vetype>, %1/m, %0.<Vetype>, #%2 + #" + "&& 1" + { + if (reload_completed + && register_operand (operands[4], <MODE>mode) + && !rtx_equal_p (operands[0], operands[4])) + { + emit_insn (gen_vcond_mask_<mode><vpred> (operands[0], operands[3], + operands[4], operands[1])); + operands[4] = operands[3] = operands[0]; + } + else + FAIL; + } + [(set_attr "movprfx" "yes")] +) ;; Register merging forms are handled through SVE_COND_FP_BINARY. ;; ------------------------------------------------------------------------- diff --git a/gcc/testsuite/gcc.target/aarch64/sve/pr96357.c b/gcc/testsuite/gcc.target/aarch64/sve/pr96357.c new file mode 100644 index 0000000000000000000000000000000000000000..e52867f57291d4a5d9a7d7c0d64e92efc8b28cfe --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/pr96357.c @@ -0,0 +1,25 @@ +/* { dg-do compile } */ +/* { dg-options "-O3 -march=armv8.2-a+sve" } */ + +int d; + +void +f1(char f, char *g, char *h, char *l, char *n) { + double i = d, j = 1.0 - f, k = j ? d : j; + if (k == 1.0) + i = 0.0; + *l = *n = *g = *h = i * 0.5; +} + +void +f2() { + int a, m, c; + for (c = 2048; c; c--) { + char b = a++; + f1(b, m, m + 1, m + 2, m + 3); /*{ dg-warning {passing argument [0-9]+ of 'f1' makes pointer from integer without a cast} } */ + m += 4; + } +} + +/* { dg-final { scan-assembler {\tmovprfx\tz[0-9]+, z[0-9]+} } } */ +/* { dg-final { scan-assembler {\tfsubr\tz[0-9]+\.d, p[0-7]/m, z[0-9]+\.d, #1.0} } } */ ^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH PR96357][GCC][AArch64]: could not split insn UNSPEC_COND_FSUB with AArch64 SVE 2020-08-25 8:56 ` Przemyslaw Wirkus @ 2020-08-25 11:14 ` Richard Sandiford 2020-08-28 10:38 ` Przemyslaw Wirkus 0 siblings, 1 reply; 8+ messages in thread From: Richard Sandiford @ 2020-08-25 11:14 UTC (permalink / raw) To: Przemyslaw Wirkus Cc: gcc-patches, Richard Earnshaw, Marcus Shawcroft, Kyrylo Tkachov Przemyslaw Wirkus <Przemyslaw.Wirkus@arm.com> writes: > @@ -5234,21 +5234,21 @@ (define_insn_and_rewrite "*cond_sub<mode>_3_const" > > ;; Predicated floating-point subtraction from a constant, merging with an > ;; independent value. > -(define_insn_and_rewrite "*cond_sub<mode>_any_const" > +;; The subtraction predicate and the merge predicate are allowed to be > +;; different. Sorry for the micromanagement, but I think this is easier to read if it flows as a single paragraph: ;; Predicated floating-point subtraction from a constant, merging with an ;; independent value. The subtraction predicate and the merge predicate are ;; allowed to be different. or is written as two separate paragraphs: ;; Predicated floating-point subtraction from a constant, merging with an ;; independent value. ;; ;; The subtraction predicate and the merge predicate are allowed to be ;; different. Same for the second comment. > @@ -5271,6 +5271,41 @@ (define_insn_and_rewrite "*cond_sub<mode>_any_const" > [(set_attr "movprfx" "yes")] > ) > > +;; Predicated floating-point subtraction from a constant, merging with an > +;; independent value. > +;; The subtraction predicate and the merge predicate must be the same. > +(define_insn_and_rewrite "*cond_sub<mode>_strict_const" > + [(set (match_operand:SVE_FULL_F 0 "register_operand" "=w, w, ?w") > + (unspec:SVE_FULL_F > + [(match_operand:<VPRED> 1 "register_operand" "Upl, Upl, Upl") > + (unspec:SVE_FULL_F > + [(match_dup 1) > + (const_int SVE_STRICT_GP) > + (match_operand:SVE_FULL_F 2 "aarch64_sve_float_arith_immediate") > + (match_operand:SVE_FULL_F 3 "register_operand" "w, w, w")] > + UNSPEC_COND_FSUB) > + (match_operand:SVE_FULL_F 4 "aarch64_simd_reg_or_zero" "Dz, 0, w")] > + UNSPEC_SEL))] > + "TARGET_SVE && !rtx_equal_p (operands[3], operands[4])" > + "@ > + movprfx\t%0.<Vetype>, %1/z, %3.<Vetype>\;fsubr\t%0.<Vetype>, %1/m, %0.<Vetype>, #%2 > + movprfx\t%0.<Vetype>, %1/m, %3.<Vetype>\;fsubr\t%0.<Vetype>, %1/m, %0.<Vetype>, #%2 > + #" > + "&& 1" > + { > + if (reload_completed > + && register_operand (operands[4], <MODE>mode) > + && !rtx_equal_p (operands[0], operands[4])) > + { > + emit_insn (gen_vcond_mask_<mode><vpred> (operands[0], operands[3], > + operands[4], operands[1])); > + operands[4] = operands[3] = operands[0]; > + } > + else > + FAIL; I should have realised this would be the case, sorry, but now that there's only one rewrite, this should simply be: "&& reload_completed && register_operand (operands[4], <MODE>mode) && !rtx_equal_p (operands[0], operands[4]))" { emit_insn (gen_vcond_mask_<mode><vpred> (operands[0], operands[3], operands[4], operands[1])); operands[4] = operands[3] = operands[0]; } OK with those changes, thanks. Richard ^ permalink raw reply [flat|nested] 8+ messages in thread
* RE: [PATCH PR96357][GCC][AArch64]: could not split insn UNSPEC_COND_FSUB with AArch64 SVE 2020-08-25 11:14 ` Richard Sandiford @ 2020-08-28 10:38 ` Przemyslaw Wirkus 2020-09-09 8:25 ` Przemyslaw Wirkus 0 siblings, 1 reply; 8+ messages in thread From: Przemyslaw Wirkus @ 2020-08-28 10:38 UTC (permalink / raw) To: Richard Sandiford Cc: gcc-patches, Richard Earnshaw, Marcus Shawcroft, Kyrylo Tkachov > Sorry for the micromanagement, but I think this is easier to read if it flows as a > single paragraph: [snip...] > I should have realised this would be the case, sorry, but now that there's only > one rewrite, this should simply be: > > "&& reload_completed > && register_operand (operands[4], <MODE>mode) > && !rtx_equal_p (operands[0], operands[4]))" > { > emit_insn (gen_vcond_mask_<mode><vpred> (operands[0], operands[3], > operands[4], operands[1])); > operands[4] = operands[3] = operands[0]; > } Done and done. > OK with those changes, thanks. > > Richard Committed with: commit b648814c02eb418aaf27897c480452172ee96303 Date: Fri Aug 28 11:31:04 2020 +0100 Kind regards, Przemyslaw ^ permalink raw reply [flat|nested] 8+ messages in thread
* RE: [PATCH PR96357][GCC][AArch64]: could not split insn UNSPEC_COND_FSUB with AArch64 SVE 2020-08-28 10:38 ` Przemyslaw Wirkus @ 2020-09-09 8:25 ` Przemyslaw Wirkus 2020-09-09 8:35 ` Richard Sandiford 0 siblings, 1 reply; 8+ messages in thread From: Przemyslaw Wirkus @ 2020-09-09 8:25 UTC (permalink / raw) To: Richard Sandiford, Richard Earnshaw, Marcus Shawcroft, Kyrylo Tkachov Cc: gcc-patches Hello maintainers, Can I backport this patch to GCC 10 please ? Regards Przemyslaw > Committed with: > > commit b648814c02eb418aaf27897c480452172ee96303 > Date: Fri Aug 28 11:31:04 2020 +0100 > > Kind regards, > Przemyslaw ^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH PR96357][GCC][AArch64]: could not split insn UNSPEC_COND_FSUB with AArch64 SVE 2020-09-09 8:25 ` Przemyslaw Wirkus @ 2020-09-09 8:35 ` Richard Sandiford 2020-09-09 8:42 ` Przemyslaw Wirkus 0 siblings, 1 reply; 8+ messages in thread From: Richard Sandiford @ 2020-09-09 8:35 UTC (permalink / raw) To: Przemyslaw Wirkus Cc: Richard Earnshaw, Marcus Shawcroft, Kyrylo Tkachov, gcc-patches Przemyslaw Wirkus <Przemyslaw.Wirkus@arm.com> writes: > Hello maintainers, > > Can I backport this patch to GCC 10 please ? Sure, that's fine. Thanks, Richard > > Regards > Przemyslaw > >> Committed with: >> >> commit b648814c02eb418aaf27897c480452172ee96303 >> Date: Fri Aug 28 11:31:04 2020 +0100 >> >> Kind regards, >> Przemyslaw ^ permalink raw reply [flat|nested] 8+ messages in thread
* RE: [PATCH PR96357][GCC][AArch64]: could not split insn UNSPEC_COND_FSUB with AArch64 SVE 2020-09-09 8:35 ` Richard Sandiford @ 2020-09-09 8:42 ` Przemyslaw Wirkus 0 siblings, 0 replies; 8+ messages in thread From: Przemyslaw Wirkus @ 2020-09-09 8:42 UTC (permalink / raw) To: Richard Sandiford Cc: Richard Earnshaw, Marcus Shawcroft, Kyrylo Tkachov, gcc-patches > Przemyslaw Wirkus <Przemyslaw.Wirkus@arm.com> writes: > > Hello maintainers, > > > > Can I backport this patch to GCC 10 please ? > > Sure, that's fine. commit 41d22ec51c4190133a082197e7ff67b4741fc09b Date: Fri Aug 28 11:31:04 2020 +0100 > Thanks, > Richard > > > > > Regards > > Przemyslaw > > > >> Committed with: > >> > >> commit b648814c02eb418aaf27897c480452172ee96303 > >> Date: Fri Aug 28 11:31:04 2020 +0100 > >> > >> Kind regards, > >> Przemyslaw ^ permalink raw reply [flat|nested] 8+ messages in thread
end of thread, other threads:[~2020-09-09 8:42 UTC | newest] Thread overview: 8+ messages (download: mbox.gz / follow: Atom feed) -- links below jump to the message on this page -- 2020-08-19 5:49 [PATCH PR96357][GCC][AArch64]: could not split insn UNSPEC_COND_FSUB with AArch64 SVE Przemyslaw Wirkus 2020-08-19 10:32 ` Richard Sandiford 2020-08-25 8:56 ` Przemyslaw Wirkus 2020-08-25 11:14 ` Richard Sandiford 2020-08-28 10:38 ` Przemyslaw Wirkus 2020-09-09 8:25 ` Przemyslaw Wirkus 2020-09-09 8:35 ` Richard Sandiford 2020-09-09 8:42 ` Przemyslaw Wirkus
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