From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by sourceware.org (Postfix) with ESMTP id D8DBD3858D28 for ; Fri, 24 Nov 2023 12:03:07 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org D8DBD3858D28 Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=arm.com ARC-Filter: OpenARC Filter v1.0.0 sourceware.org D8DBD3858D28 Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1700827393; cv=none; b=iCW0jjnspQi/x6x6aiiuSdxTZJ4sovYm+Prdow26SlPPWsKgHgnLp6Klh2e2+1TP0H+8gCOhDfvpHiHxD8OpFCtJHEW5EtMmas+gL10XmS+AsY0bkCw0MJhtMfEmoUZaQJPnKnmtUVNB+2tPPR4SdWmhmHJAfQqTjkWT47KXQis= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1700827393; c=relaxed/simple; bh=upwSb/NGuP4XuuatwvYg5r0gYgFf0B6AmWfj/1t95Lo=; h=From:To:Subject:Date:Message-ID:MIME-Version; b=exkuXGLVcfKjGjVTMI2tlWJiTTxl45zl2TOozOmt47JOf17OrvNyUACv1Q+huwwB9LpJJf5ryoxL33MrKs5RsIi+MqTPSq78maZJNOSPPJfd1kj1SGu8x8c6oh9VQi20+Y73O8521Xh9tlja77wjzY1oLXrzt7R1zEuGfuOd1oI= ARC-Authentication-Results: i=1; server2.sourceware.org Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 0F4281063; Fri, 24 Nov 2023 04:03:54 -0800 (PST) Received: from localhost (e121540-lin.manchester.arm.com [10.32.110.72]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id E154C3F7A6; Fri, 24 Nov 2023 04:03:06 -0800 (PST) From: Richard Sandiford To: Victor Do Nascimento Mail-Followup-To: Victor Do Nascimento ,, , , richard.sandiford@arm.com Cc: , , Subject: Re: [PATCH 1/5] aarch64: rcpc3: Add +rcpc3 extension References: <20231109141300.3542453-1-victor.donascimento@arm.com> <20231109141300.3542453-2-victor.donascimento@arm.com> Date: Fri, 24 Nov 2023 12:03:05 +0000 In-Reply-To: <20231109141300.3542453-2-victor.donascimento@arm.com> (Victor Do Nascimento's message of "Thu, 9 Nov 2023 14:12:44 +0000") Message-ID: User-Agent: Gnus/5.13 (Gnus v5.13) Emacs/26.3 (gnu/linux) MIME-Version: 1.0 Content-Type: text/plain X-Spam-Status: No, score=-22.6 required=5.0 tests=BAYES_00,GIT_PATCH_0,KAM_DMARC_NONE,KAM_DMARC_STATUS,KAM_LAZY_DOMAIN_SECURITY,SPF_HELO_NONE,SPF_NONE,TXREP,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: Victor Do Nascimento writes: > Given the optional LRCPC3 target support for Armv8.2-a cores onwards, > the +rcpc3 arch feature modifier is added to GCC's command-line options. > > gcc/ChangeLog: > > * config/aarch64/aarch64-option-extensions.def (rcpc3): New. > * config/aarch64/aarch64.h (AARCH64_ISA_RCPC3): Likewise. > (TARGET_RCPC3): Likewise. > * doc/invoke.texi (rcpc3): Document feature in AArch64 Options. > --- > gcc/config/aarch64/aarch64-option-extensions.def | 1 + > gcc/config/aarch64/aarch64.h | 4 ++++ > gcc/doc/invoke.texi | 4 ++++ > 3 files changed, 9 insertions(+) > > diff --git a/gcc/config/aarch64/aarch64-option-extensions.def b/gcc/config/aarch64/aarch64-option-extensions.def > index 825f3bf7758..2ab94799d34 100644 > --- a/gcc/config/aarch64/aarch64-option-extensions.def > +++ b/gcc/config/aarch64/aarch64-option-extensions.def > @@ -151,4 +151,5 @@ AARCH64_OPT_EXTENSION("mops", MOPS, (), (), (), "") > > AARCH64_OPT_EXTENSION("cssc", CSSC, (), (), (), "cssc") > > +AARCH64_OPT_EXTENSION("rcpc3", RCPC3, (), (), (), "rcpc3") > #undef AARCH64_OPT_EXTENSION > diff --git a/gcc/config/aarch64/aarch64.h b/gcc/config/aarch64/aarch64.h > index 2f0777a37ac..68bbaccef1a 100644 > --- a/gcc/config/aarch64/aarch64.h > +++ b/gcc/config/aarch64/aarch64.h > @@ -213,6 +213,7 @@ enum class aarch64_feature : unsigned char { > #define AARCH64_ISA_F64MM (aarch64_isa_flags & AARCH64_FL_F64MM) > #define AARCH64_ISA_BF16 (aarch64_isa_flags & AARCH64_FL_BF16) > #define AARCH64_ISA_SB (aarch64_isa_flags & AARCH64_FL_SB) > +#define AARCH64_ISA_RCPC3 (aarch64_isa_flags & AARCH64_FL_RCPC3) > #define AARCH64_ISA_V8R (aarch64_isa_flags & AARCH64_FL_V8R) > #define AARCH64_ISA_PAUTH (aarch64_isa_flags & AARCH64_FL_PAUTH) > #define AARCH64_ISA_V9A (aarch64_isa_flags & AARCH64_FL_V9A) > @@ -344,6 +345,9 @@ enum class aarch64_feature : unsigned char { > and sign-extending versions.*/ > #define TARGET_RCPC2 (AARCH64_ISA_RCPC8_4) > > +/* RCPC3 LDAP1/STL1 loads/stores from Armv8.2-a. */ > +#define TARGET_RCPC3 (AARCH64_ISA_RCPC3) The extension is more general than that, so maybe just: /* RCPC3 (Release Consistency) extensions, optional from Armv8.2-A. */ > + > /* Apply the workaround for Cortex-A53 erratum 835769. */ > #define TARGET_FIX_ERR_A53_835769 \ > ((aarch64_fix_a53_err835769 == 2) \ > diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi > index 6e776a0faa1..ba28eb195ce 100644 > --- a/gcc/doc/invoke.texi > +++ b/gcc/doc/invoke.texi > @@ -21028,6 +21028,10 @@ Enable the Flag Manipulation instructions Extension. > Enable the Pointer Authentication Extension. > @item cssc > Enable the Common Short Sequence Compression instructions. > +@item rcpc3 > +Enable the RCpc3 extension. This enables the use of the LDAP1 and > +STL1 instructions for loads/stores of 64-bit values to and from SIMD > +register lanes, passing these on to the assembler. Similarly here, it's probably enough to say: Enable the RCpc3 (Release Consistency) extension. OK with those changes, thanks. Richard