From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by sourceware.org (Postfix) with ESMTP id B92693858418 for ; Tue, 7 Dec 2021 13:38:40 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org B92693858418 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 6659611FB; Tue, 7 Dec 2021 05:38:40 -0800 (PST) Received: from localhost (unknown [10.32.98.88]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id C8CE43F5A1; Tue, 7 Dec 2021 05:38:39 -0800 (PST) From: Richard Sandiford To: Prathamesh Kulkarni Mail-Followup-To: Prathamesh Kulkarni , gcc Patches , rguenther@suse.de, richard.sandiford@arm.com Cc: gcc Patches , rguenther@suse.de Subject: Re: [SVE] PR96463 - Optimise svld1rq from vectors References: Date: Tue, 07 Dec 2021 13:38:38 +0000 In-Reply-To: (Prathamesh Kulkarni's message of "Tue, 7 Dec 2021 17:15:02 +0530") Message-ID: User-Agent: Gnus/5.13 (Gnus v5.13) Emacs/26.3 (gnu/linux) MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable X-Spam-Status: No, score=-6.4 required=5.0 tests=BAYES_00, KAM_DMARC_STATUS, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.4 X-Spam-Checker-Version: SpamAssassin 3.4.4 (2020-01-24) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 07 Dec 2021 13:38:42 -0000 Prathamesh Kulkarni writes: > On Thu, 2 Dec 2021 at 23:11, Richard Sandiford > wrote: >> >> Prathamesh Kulkarni writes: >> > Hi Richard, >> > I have attached a WIP untested patch for PR96463. >> > IIUC, the PR suggests to transform >> > lhs =3D svld1rq ({-1, -1, ...}, &v[0]) >> > into: >> > lhs =3D vec_perm_expr >> > if v is vector of 4 elements, and each element is 32 bits on little >> > endian target ? >> > >> > I am sorry if this sounds like a silly question, but I am not sure how >> > to convert a vector of type int32x4_t into svint32_t ? In the patch, I >> > simply used NOP_EXPR (which I expected to fail), and gave type error >> > during gimple verification: >> >> It should be possible in principle to have a VEC_PERM_EXPR in which >> the operands are Advanced SIMD vectors and the result is an SVE vector. >> >> E.g., the dup in the PR would be something like this: >> >> foo (int32x4_t a) >> { >> svint32_t _2; >> >> _2 =3D VEC_PERM_EXPR ; >> return _2; >> } >> >> where the final operand can be built using: >> >> int source_nelts =3D TYPE_VECTOR_SUBPARTS (=E2=80=A6rhs type=E2=80=A6)= .to_constant (); >> vec_perm_builder sel (TYPE_VECTOR_SUBPARTS (=E2=80=A6lhs type=E2=80=A6= ), source_nelts, 1); >> for (int i =3D 0; i < source_nelts; ++i) >> sel.quick_push (i); >> >> I'm not sure how well-tested that combination is though. It might need >> changes to target-independent code. > Hi Richard, > Thanks for the suggestions. > I tried the above approach in attached patch, but it still results in > ICE due to type mismatch: > > pr96463.c: In function =E2=80=98foo=E2=80=99: > pr96463.c:8:1: error: type mismatch in =E2=80=98vec_perm_expr=E2=80=99 > 8 | } > | ^ > svint32_t > int32x4_t > int32x4_t > svint32_t > _3 =3D VEC_PERM_EXPR ; > during GIMPLE pass: ccp > dump file: pr96463.c.032t.ccp1 > pr96463.c:8:1: internal compiler error: verify_gimple failed > > Should we perhaps add another tree code, that "extends" a fixed-width > vector into it's VLA equivalent ? No, I think this is just an extreme example of the combination not being well-tested. :-) Obviously it's worse than I thought. I think accepting this kind of VEC_PERM_EXPR is still the way to go. Richi, WDYT? Thanks, Richard