From: Richard Sandiford <richard.sandiford@arm.com>
To: Matthew Malcomson <Matthew.Malcomson@arm.com>
Cc: "gcc-patches\@gcc.gnu.org" <gcc-patches@gcc.gnu.org>,
nd <nd@arm.com>, Marcus Shawcroft <Marcus.Shawcroft@arm.com>,
Kyrylo Tkachov <Kyrylo.Tkachov@arm.com>,
Richard Earnshaw <Richard.Earnshaw@arm.com>
Subject: Re: [PATCH][AArch64] Enable CLI for Armv8.6-A f64mm
Date: Thu, 16 Jan 2020 17:43:00 -0000 [thread overview]
Message-ID: <mpt36cf2u7n.fsf@arm.com> (raw)
In-Reply-To: <AM6PR08MB4326D7DEE11B949234434854E0350@AM6PR08MB4326.eurprd08.prod.outlook.com> (Matthew Malcomson's message of "Mon, 13 Jan 2020 11:33:56 +0000")
Matthew Malcomson <Matthew.Malcomson@arm.com> writes:
> This patch is necessary for sve-ld1ro intrinsic I posted in
> https://gcc.gnu.org/ml/gcc-patches/2020-01/msg00466.html .
>
> I had mistakenly thought this option was already enabled upstream.
>
> This provides the option +f64mm, that turns on the 64 bit floating point
> matrix multiply extension. This extension is only available for
> AArch64. Turning on this extension also turns on the SVE extension.
>
> This extension is optional and only available at Armv8.2-A and onward.
>
> We also add the ACLE defined macro for this extension.
>
> Tested on aarch64 cross compiler from x86.
>
> gcc/ChangeLog:
>
> 2020-01-13 Matthew Malcomson <matthew.malcomson@arm.com>
>
> * config/aarch64/aarch64-c.c (_ARM_FEATURE_MATMUL_FLOAT64):
> Introduce this ACLE specified predefined macro.
> * config/aarch64/aarch64-option-extensions.def (f64mm): New.
> (fp): Disabling this disables f64mm.
> (simd): Disabling this disables f64mm.
> (fp16): Disabling this disables f64mm.
> (sve): Disabling this disables f64mm.
> * config/aarch64/aarch64.h (AARCH64_FL_F64MM): New.
> (AARCH64_ISA_F64MM): New.
> (TARGET_F64MM): New.
> * doc/invoke.texi (f64mm): Document new option.
Sorry for the slow reply, somehow missed this originally.
> diff --git a/gcc/config/aarch64/aarch64-option-extensions.def b/gcc/config/aarch64/aarch64-option-extensions.def
> index 5022a1b3552f35364e35b3955bf2c39a33ab0752..6057b33033a0f3a8be7d656dc1e459d4d93b2842 100644
> --- a/gcc/config/aarch64/aarch64-option-extensions.def
> +++ b/gcc/config/aarch64/aarch64-option-extensions.def
> @@ -53,26 +53,26 @@
> /* Enabling "fp" just enables "fp".
> Disabling "fp" also disables "simd", "crypto", "fp16", "aes", "sha2",
> "sha3", sm3/sm4, "sve", "sve2", "sve2-aes", "sve2-sha3", "sve2-sm4",
> - "sve2-bitperm", "i8mm" and "bf16". */
> + "sve2-bitperm", "i8mm", "f64mm", and "bf16". */
> AARCH64_OPT_EXTENSION("fp", AARCH64_FL_FP, 0, AARCH64_FL_SIMD | \
> AARCH64_FL_CRYPTO | AARCH64_FL_F16 | AARCH64_FL_AES | \
> AARCH64_FL_SHA2 | AARCH64_FL_SHA3 | AARCH64_FL_SM4 | \
> AARCH64_FL_SVE | AARCH64_FL_SVE2 | AARCH64_FL_SVE2_AES | \
> AARCH64_FL_SVE2_SHA3 | AARCH64_FL_SVE2_SM4 | \
> AARCH64_FL_SVE2_BITPERM | AARCH64_FL_I8MM | \
> - AARCH64_FL_BF16, false, "fp")
> + AARCH64_FL_F64MM | AARCH64_FL_BF16, false, "fp")
>
> /* Enabling "simd" also enables "fp".
> Disabling "simd" also disables "crypto", "dotprod", "aes", "sha2", "sha3",
> "sm3/sm4", "sve", "sve2", "sve2-aes", "sve2-sha3", "sve2-sm4",
> - "sve2-bitperm", and "i8mm". */
> + "sve2-bitperm", "i8mm", and "f64mm". */
> AARCH64_OPT_EXTENSION("simd", AARCH64_FL_SIMD, AARCH64_FL_FP, \
> AARCH64_FL_CRYPTO | AARCH64_FL_DOTPROD | \
> AARCH64_FL_AES | AARCH64_FL_SHA2 | AARCH64_FL_SHA3 | \
> AARCH64_FL_SM4 | AARCH64_FL_SVE | AARCH64_FL_SVE2 | \
> AARCH64_FL_SVE2_AES | AARCH64_FL_SVE2_SHA3 | \
> AARCH64_FL_SVE2_SM4 | AARCH64_FL_SVE2_BITPERM | \
> - AARCH64_FL_I8MM, false, \
> + AARCH64_FL_I8MM | AARCH64_FL_F64MM, false, \
> "asimd")
>
> /* Enabling "crypto" also enables "fp", "simd", "aes" and "sha2".
> @@ -92,12 +92,13 @@ AARCH64_OPT_EXTENSION("crc", AARCH64_FL_CRC, 0, 0, false, "crc32")
> AARCH64_OPT_EXTENSION("lse", AARCH64_FL_LSE, 0, 0, false, "atomics")
>
> /* Enabling "fp16" also enables "fp".
> - Disabling "fp16" disables "fp16", "fp16fml", "sve", "sve2", "sve2-aes",
> - "sve2-sha3", "sve2-sm4", and "bitperm". */
> + Disabling "fp16" disables "fp16", "fp16fml", "sve", "f64mm", "sve2",
> + "sve2-aes", "sve2-sha3", "sve2-sm4", and "bitperm". */
> AARCH64_OPT_EXTENSION("fp16", AARCH64_FL_F16, AARCH64_FL_FP, \
> - AARCH64_FL_F16FML | AARCH64_FL_SVE | AARCH64_FL_SVE2 | \
> - AARCH64_FL_SVE2_AES | AARCH64_FL_SVE2_SHA3 | \
> - AARCH64_FL_SVE2_SM4 | AARCH64_FL_SVE2_BITPERM, false, \
> + AARCH64_FL_F16FML | AARCH64_FL_SVE | AARCH64_FL_F64MM | \
> + AARCH64_FL_SVE2 | AARCH64_FL_SVE2_AES | \
> + AARCH64_FL_SVE2_SHA3 | AARCH64_FL_SVE2_SM4 | \
> + AARCH64_FL_SVE2_BITPERM, false, \
> "fphp asimdhp")
Minor (of course), but it'd probably better to keep the order of the
options consistent. Above "f64mm" came at the end, after "i8mm" and
the SVE options, so let's do the same here. Could you fix
s/"bitperm"/"sve2-bitperm" while you're there?
> diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi
> index 53df4b1fdf9884d0b7cb73341d717887e79fef9c..47668731efc25dbf32a3b6b38817d7762bbfa93f 100644
> --- a/gcc/doc/invoke.texi
> +++ b/gcc/doc/invoke.texi
> @@ -16130,7 +16130,7 @@ and the features that they enable by default:
> @item @samp{armv8.3-a} @tab Armv8.3-A @tab @samp{armv8.2-a}
> @item @samp{armv8.4-a} @tab Armv8.4-A @tab @samp{armv8.3-a}, @samp{+fp16fml}, @samp{+dotprod}
> @item @samp{armv8.5-a} @tab Armv8.5-A @tab @samp{armv8.4-a}, @samp{+sb}, @samp{+ssbs}, @samp{+predres}
> -@item @samp{armv8.6-a} @tab Armv8.6-A @tab @samp{armv8.5-a}, @samp{+bf16}, @samp{+i8mm}
> +@item @samp{armv8.6-a} @tab Armv8.6-A @tab @samp{armv8.5-a}, @samp{+bf16}, @samp{+i8mm}, @samp{+f64mm}
> @end multitable
The patch doesn't enable f64mm by default for Arm8.6-A.
OK without that hunk and with the change above, thanks.
Richard
prev parent reply other threads:[~2020-01-16 17:21 UTC|newest]
Thread overview: 2+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-01-13 12:40 Matthew Malcomson
2020-01-16 17:43 ` Richard Sandiford [this message]
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