* [PATCH 10/13] arm: Convert remaining MVE vcmp builtins to predicate qualifiers @ 2021-09-07 9:20 Christophe Lyon 2021-09-07 9:20 ` [PATCH 11/13] arm: Convert more MVE " Christophe Lyon ` (3 more replies) 0 siblings, 4 replies; 9+ messages in thread From: Christophe Lyon @ 2021-09-07 9:20 UTC (permalink / raw) To: gcc-patches This is mostly a mechanical change, only tested by the intrinsics expansion tests. 2021-09-02 Christophe Lyon <christophe.lyon@foss.st.com> gcc/ PR target/100757 PR target/101325 * config/arm/arm-builtins.c (BINOP_UNONE_NONE_NONE_QUALIFIERS): Delete. (TERNOP_UNONE_NONE_NONE_UNONE_QUALIFIERS): Change to ... (TERNOP_PRED_NONE_NONE_PRED_QUALIFIERS): ... this. (TERNOP_PRED_UNONE_UNONE_PRED_QUALIFIERS): New. * config/arm/arm_mve_builtins.def (vcmp*q_n_, vcmp*q_m_f): Use new predicated qualifiers. * config/arm/mve.md (mve_vcmp<mve_cmp_op>q_n_<mode>) (mve_vcmp*q_m_f<mode>): Use MVE_VPRED instead of HI. diff --git a/gcc/config/arm/arm-builtins.c b/gcc/config/arm/arm-builtins.c index 6e3638869f1..b3455d87d4f 100644 --- a/gcc/config/arm/arm-builtins.c +++ b/gcc/config/arm/arm-builtins.c @@ -487,12 +487,6 @@ arm_binop_none_none_unone_qualifiers[SIMD_MAX_BUILTIN_ARGS] #define BINOP_NONE_NONE_UNONE_QUALIFIERS \ (arm_binop_none_none_unone_qualifiers) -static enum arm_type_qualifiers -arm_binop_unone_none_none_qualifiers[SIMD_MAX_BUILTIN_ARGS] - = { qualifier_unsigned, qualifier_none, qualifier_none }; -#define BINOP_UNONE_NONE_NONE_QUALIFIERS \ - (arm_binop_unone_none_none_qualifiers) - static enum arm_type_qualifiers arm_binop_pred_none_none_qualifiers[SIMD_MAX_BUILTIN_ARGS] = { qualifier_predicate, qualifier_none, qualifier_none }; @@ -553,10 +547,10 @@ arm_ternop_unone_unone_imm_unone_qualifiers[SIMD_MAX_BUILTIN_ARGS] (arm_ternop_unone_unone_imm_unone_qualifiers) static enum arm_type_qualifiers -arm_ternop_unone_none_none_unone_qualifiers[SIMD_MAX_BUILTIN_ARGS] - = { qualifier_unsigned, qualifier_none, qualifier_none, qualifier_unsigned }; -#define TERNOP_UNONE_NONE_NONE_UNONE_QUALIFIERS \ - (arm_ternop_unone_none_none_unone_qualifiers) +arm_ternop_pred_none_none_pred_qualifiers[SIMD_MAX_BUILTIN_ARGS] + = { qualifier_predicate, qualifier_none, qualifier_none, qualifier_predicate }; +#define TERNOP_PRED_NONE_NONE_PRED_QUALIFIERS \ + (arm_ternop_pred_none_none_pred_qualifiers) static enum arm_type_qualifiers arm_ternop_none_none_none_imm_qualifiers[SIMD_MAX_BUILTIN_ARGS] @@ -602,6 +596,13 @@ arm_ternop_unone_unone_unone_pred_qualifiers[SIMD_MAX_BUILTIN_ARGS] #define TERNOP_UNONE_UNONE_UNONE_PRED_QUALIFIERS \ (arm_ternop_unone_unone_unone_pred_qualifiers) +static enum arm_type_qualifiers +arm_ternop_pred_unone_unone_pred_qualifiers[SIMD_MAX_BUILTIN_ARGS] + = { qualifier_predicate, qualifier_unsigned, qualifier_unsigned, + qualifier_predicate }; +#define TERNOP_PRED_UNONE_UNONE_PRED_QUALIFIERS \ + (arm_ternop_pred_unone_unone_pred_qualifiers) + static enum arm_type_qualifiers arm_ternop_none_none_none_none_qualifiers[SIMD_MAX_BUILTIN_ARGS] = { qualifier_none, qualifier_none, qualifier_none, qualifier_none }; diff --git a/gcc/config/arm/arm_mve_builtins.def b/gcc/config/arm/arm_mve_builtins.def index 58a05e61bd9..91ed2073918 100644 --- a/gcc/config/arm/arm_mve_builtins.def +++ b/gcc/config/arm/arm_mve_builtins.def @@ -118,9 +118,9 @@ VAR3 (BINOP_UNONE_UNONE_UNONE, vhaddq_u, v16qi, v8hi, v4si) VAR3 (BINOP_UNONE_UNONE_UNONE, vhaddq_n_u, v16qi, v8hi, v4si) VAR3 (BINOP_UNONE_UNONE_UNONE, veorq_u, v16qi, v8hi, v4si) VAR3 (BINOP_PRED_UNONE_UNONE, vcmphiq_, v16qi, v8hi, v4si) -VAR3 (BINOP_UNONE_UNONE_UNONE, vcmphiq_n_, v16qi, v8hi, v4si) +VAR3 (BINOP_PRED_UNONE_UNONE, vcmphiq_n_, v16qi, v8hi, v4si) VAR3 (BINOP_PRED_UNONE_UNONE, vcmpcsq_, v16qi, v8hi, v4si) -VAR3 (BINOP_UNONE_UNONE_UNONE, vcmpcsq_n_, v16qi, v8hi, v4si) +VAR3 (BINOP_PRED_UNONE_UNONE, vcmpcsq_n_, v16qi, v8hi, v4si) VAR3 (BINOP_UNONE_UNONE_UNONE, vbicq_u, v16qi, v8hi, v4si) VAR3 (BINOP_UNONE_UNONE_UNONE, vandq_u, v16qi, v8hi, v4si) VAR3 (BINOP_UNONE_UNONE_UNONE, vaddvq_p_u, v16qi, v8hi, v4si) @@ -142,17 +142,17 @@ VAR3 (BINOP_UNONE_UNONE_NONE, vbrsrq_n_u, v16qi, v8hi, v4si) VAR3 (BINOP_UNONE_UNONE_IMM, vshlq_n_u, v16qi, v8hi, v4si) VAR3 (BINOP_UNONE_UNONE_IMM, vrshrq_n_u, v16qi, v8hi, v4si) VAR3 (BINOP_UNONE_UNONE_IMM, vqshlq_n_u, v16qi, v8hi, v4si) -VAR3 (BINOP_UNONE_NONE_NONE, vcmpneq_n_, v16qi, v8hi, v4si) +VAR3 (BINOP_PRED_NONE_NONE, vcmpneq_n_, v16qi, v8hi, v4si) VAR3 (BINOP_PRED_NONE_NONE, vcmpltq_, v16qi, v8hi, v4si) -VAR3 (BINOP_UNONE_NONE_NONE, vcmpltq_n_, v16qi, v8hi, v4si) +VAR3 (BINOP_PRED_NONE_NONE, vcmpltq_n_, v16qi, v8hi, v4si) VAR3 (BINOP_PRED_NONE_NONE, vcmpleq_, v16qi, v8hi, v4si) -VAR3 (BINOP_UNONE_NONE_NONE, vcmpleq_n_, v16qi, v8hi, v4si) +VAR3 (BINOP_PRED_NONE_NONE, vcmpleq_n_, v16qi, v8hi, v4si) VAR3 (BINOP_PRED_NONE_NONE, vcmpgtq_, v16qi, v8hi, v4si) -VAR3 (BINOP_UNONE_NONE_NONE, vcmpgtq_n_, v16qi, v8hi, v4si) +VAR3 (BINOP_PRED_NONE_NONE, vcmpgtq_n_, v16qi, v8hi, v4si) VAR3 (BINOP_PRED_NONE_NONE, vcmpgeq_, v16qi, v8hi, v4si) -VAR3 (BINOP_UNONE_NONE_NONE, vcmpgeq_n_, v16qi, v8hi, v4si) +VAR3 (BINOP_PRED_NONE_NONE, vcmpgeq_n_, v16qi, v8hi, v4si) VAR3 (BINOP_PRED_NONE_NONE, vcmpeqq_, v16qi, v8hi, v4si) -VAR3 (BINOP_UNONE_NONE_NONE, vcmpeqq_n_, v16qi, v8hi, v4si) +VAR3 (BINOP_PRED_NONE_NONE, vcmpeqq_n_, v16qi, v8hi, v4si) VAR3 (BINOP_UNONE_NONE_IMM, vqshluq_n_s, v16qi, v8hi, v4si) VAR3 (BINOP_NONE_NONE_UNONE, vaddvq_p_s, v16qi, v8hi, v4si) VAR3 (BINOP_NONE_NONE_NONE, vsubq_s, v16qi, v8hi, v4si) @@ -218,17 +218,17 @@ VAR2 (BINOP_UNONE_UNONE_IMM, vshlltq_n_u, v16qi, v8hi) VAR2 (BINOP_UNONE_UNONE_IMM, vshllbq_n_u, v16qi, v8hi) VAR2 (BINOP_UNONE_UNONE_IMM, vorrq_n_u, v8hi, v4si) VAR2 (BINOP_UNONE_UNONE_IMM, vbicq_n_u, v8hi, v4si) -VAR2 (BINOP_UNONE_NONE_NONE, vcmpneq_n_f, v8hf, v4sf) +VAR2 (BINOP_PRED_NONE_NONE, vcmpneq_n_f, v8hf, v4sf) VAR2 (BINOP_PRED_NONE_NONE, vcmpneq_f, v8hf, v4sf) -VAR2 (BINOP_UNONE_NONE_NONE, vcmpltq_n_f, v8hf, v4sf) +VAR2 (BINOP_PRED_NONE_NONE, vcmpltq_n_f, v8hf, v4sf) VAR2 (BINOP_PRED_NONE_NONE, vcmpltq_f, v8hf, v4sf) -VAR2 (BINOP_UNONE_NONE_NONE, vcmpleq_n_f, v8hf, v4sf) +VAR2 (BINOP_PRED_NONE_NONE, vcmpleq_n_f, v8hf, v4sf) VAR2 (BINOP_PRED_NONE_NONE, vcmpleq_f, v8hf, v4sf) -VAR2 (BINOP_UNONE_NONE_NONE, vcmpgtq_n_f, v8hf, v4sf) +VAR2 (BINOP_PRED_NONE_NONE, vcmpgtq_n_f, v8hf, v4sf) VAR2 (BINOP_PRED_NONE_NONE, vcmpgtq_f, v8hf, v4sf) -VAR2 (BINOP_UNONE_NONE_NONE, vcmpgeq_n_f, v8hf, v4sf) +VAR2 (BINOP_PRED_NONE_NONE, vcmpgeq_n_f, v8hf, v4sf) VAR2 (BINOP_PRED_NONE_NONE, vcmpgeq_f, v8hf, v4sf) -VAR2 (BINOP_UNONE_NONE_NONE, vcmpeqq_n_f, v8hf, v4sf) +VAR2 (BINOP_PRED_NONE_NONE, vcmpeqq_n_f, v8hf, v4sf) VAR2 (BINOP_PRED_NONE_NONE, vcmpeqq_f, v8hf, v4sf) VAR2 (BINOP_NONE_NONE_NONE, vsubq_f, v8hf, v4sf) VAR2 (BINOP_NONE_NONE_NONE, vqmovntq_s, v8hi, v4si) @@ -285,7 +285,7 @@ VAR1 (TERNOP_NONE_NONE_NONE_NONE, vrmlaldavhaq_s, v4si) VAR1 (TERNOP_UNONE_UNONE_UNONE_UNONE, vrmlaldavhaq_u, v4si) VAR2 (TERNOP_NONE_NONE_UNONE_UNONE, vcvtq_m_to_f_u, v8hf, v4sf) VAR2 (TERNOP_NONE_NONE_NONE_UNONE, vcvtq_m_to_f_s, v8hf, v4sf) -VAR2 (TERNOP_UNONE_NONE_NONE_UNONE, vcmpeqq_m_f, v8hf, v4sf) +VAR2 (TERNOP_PRED_NONE_NONE_PRED, vcmpeqq_m_f, v8hf, v4sf) VAR3 (TERNOP_UNONE_NONE_UNONE_IMM, vshlcq_carry_s, v16qi, v8hi, v4si) VAR3 (TERNOP_UNONE_UNONE_UNONE_IMM, vshlcq_carry_u, v16qi, v8hi, v4si) VAR2 (TERNOP_UNONE_UNONE_NONE_IMM, vqrshrunbq_n_s, v8hi, v4si) @@ -306,14 +306,14 @@ VAR3 (TERNOP_UNONE_UNONE_UNONE_UNONE, vmladavaq_u, v16qi, v8hi, v4si) VAR3 (TERNOP_UNONE_UNONE_UNONE_UNONE, vminvq_p_u, v16qi, v8hi, v4si) VAR3 (TERNOP_UNONE_UNONE_UNONE_UNONE, vmaxvq_p_u, v16qi, v8hi, v4si) VAR3 (TERNOP_UNONE_UNONE_UNONE_UNONE, vdupq_m_n_u, v16qi, v8hi, v4si) -VAR3 (TERNOP_UNONE_UNONE_UNONE_UNONE, vcmpneq_m_u, v16qi, v8hi, v4si) -VAR3 (TERNOP_UNONE_UNONE_UNONE_UNONE, vcmpneq_m_n_u, v16qi, v8hi, v4si) -VAR3 (TERNOP_UNONE_UNONE_UNONE_UNONE, vcmphiq_m_u, v16qi, v8hi, v4si) -VAR3 (TERNOP_UNONE_UNONE_UNONE_UNONE, vcmphiq_m_n_u, v16qi, v8hi, v4si) -VAR3 (TERNOP_UNONE_UNONE_UNONE_UNONE, vcmpeqq_m_u, v16qi, v8hi, v4si) -VAR3 (TERNOP_UNONE_UNONE_UNONE_UNONE, vcmpeqq_m_n_u, v16qi, v8hi, v4si) -VAR3 (TERNOP_UNONE_UNONE_UNONE_UNONE, vcmpcsq_m_u, v16qi, v8hi, v4si) -VAR3 (TERNOP_UNONE_UNONE_UNONE_UNONE, vcmpcsq_m_n_u, v16qi, v8hi, v4si) +VAR3 (TERNOP_PRED_UNONE_UNONE_PRED, vcmpneq_m_u, v16qi, v8hi, v4si) +VAR3 (TERNOP_PRED_UNONE_UNONE_PRED, vcmpneq_m_n_u, v16qi, v8hi, v4si) +VAR3 (TERNOP_PRED_UNONE_UNONE_PRED, vcmphiq_m_u, v16qi, v8hi, v4si) +VAR3 (TERNOP_PRED_UNONE_UNONE_PRED, vcmphiq_m_n_u, v16qi, v8hi, v4si) +VAR3 (TERNOP_PRED_UNONE_UNONE_PRED, vcmpeqq_m_u, v16qi, v8hi, v4si) +VAR3 (TERNOP_PRED_UNONE_UNONE_PRED, vcmpeqq_m_n_u, v16qi, v8hi, v4si) +VAR3 (TERNOP_PRED_UNONE_UNONE_PRED, vcmpcsq_m_u, v16qi, v8hi, v4si) +VAR3 (TERNOP_PRED_UNONE_UNONE_PRED, vcmpcsq_m_n_u, v16qi, v8hi, v4si) VAR3 (TERNOP_UNONE_UNONE_UNONE_UNONE, vclzq_m_u, v16qi, v8hi, v4si) VAR3 (TERNOP_UNONE_UNONE_UNONE_UNONE, vaddvaq_p_u, v16qi, v8hi, v4si) VAR3 (TERNOP_UNONE_UNONE_UNONE_IMM, vsriq_n_u, v16qi, v8hi, v4si) @@ -326,18 +326,18 @@ VAR3 (TERNOP_UNONE_UNONE_NONE_UNONE, vminavq_p_s, v16qi, v8hi, v4si) VAR3 (TERNOP_UNONE_UNONE_NONE_UNONE, vminaq_m_s, v16qi, v8hi, v4si) VAR3 (TERNOP_UNONE_UNONE_NONE_UNONE, vmaxavq_p_s, v16qi, v8hi, v4si) VAR3 (TERNOP_UNONE_UNONE_NONE_UNONE, vmaxaq_m_s, v16qi, v8hi, v4si) -VAR3 (TERNOP_UNONE_NONE_NONE_UNONE, vcmpneq_m_s, v16qi, v8hi, v4si) -VAR3 (TERNOP_UNONE_NONE_NONE_UNONE, vcmpneq_m_n_s, v16qi, v8hi, v4si) -VAR3 (TERNOP_UNONE_NONE_NONE_UNONE, vcmpltq_m_s, v16qi, v8hi, v4si) -VAR3 (TERNOP_UNONE_NONE_NONE_UNONE, vcmpltq_m_n_s, v16qi, v8hi, v4si) -VAR3 (TERNOP_UNONE_NONE_NONE_UNONE, vcmpleq_m_s, v16qi, v8hi, v4si) -VAR3 (TERNOP_UNONE_NONE_NONE_UNONE, vcmpleq_m_n_s, v16qi, v8hi, v4si) -VAR3 (TERNOP_UNONE_NONE_NONE_UNONE, vcmpgtq_m_s, v16qi, v8hi, v4si) -VAR3 (TERNOP_UNONE_NONE_NONE_UNONE, vcmpgtq_m_n_s, v16qi, v8hi, v4si) -VAR3 (TERNOP_UNONE_NONE_NONE_UNONE, vcmpgeq_m_s, v16qi, v8hi, v4si) -VAR3 (TERNOP_UNONE_NONE_NONE_UNONE, vcmpgeq_m_n_s, v16qi, v8hi, v4si) -VAR3 (TERNOP_UNONE_NONE_NONE_UNONE, vcmpeqq_m_s, v16qi, v8hi, v4si) -VAR3 (TERNOP_UNONE_NONE_NONE_UNONE, vcmpeqq_m_n_s, v16qi, v8hi, v4si) +VAR3 (TERNOP_PRED_NONE_NONE_PRED, vcmpneq_m_s, v16qi, v8hi, v4si) +VAR3 (TERNOP_PRED_NONE_NONE_PRED, vcmpneq_m_n_s, v16qi, v8hi, v4si) +VAR3 (TERNOP_PRED_NONE_NONE_PRED, vcmpltq_m_s, v16qi, v8hi, v4si) +VAR3 (TERNOP_PRED_NONE_NONE_PRED, vcmpltq_m_n_s, v16qi, v8hi, v4si) +VAR3 (TERNOP_PRED_NONE_NONE_PRED, vcmpleq_m_s, v16qi, v8hi, v4si) +VAR3 (TERNOP_PRED_NONE_NONE_PRED, vcmpleq_m_n_s, v16qi, v8hi, v4si) +VAR3 (TERNOP_PRED_NONE_NONE_PRED, vcmpgtq_m_s, v16qi, v8hi, v4si) +VAR3 (TERNOP_PRED_NONE_NONE_PRED, vcmpgtq_m_n_s, v16qi, v8hi, v4si) +VAR3 (TERNOP_PRED_NONE_NONE_PRED, vcmpgeq_m_s, v16qi, v8hi, v4si) +VAR3 (TERNOP_PRED_NONE_NONE_PRED, vcmpgeq_m_n_s, v16qi, v8hi, v4si) +VAR3 (TERNOP_PRED_NONE_NONE_PRED, vcmpeqq_m_s, v16qi, v8hi, v4si) +VAR3 (TERNOP_PRED_NONE_NONE_PRED, vcmpeqq_m_n_s, v16qi, v8hi, v4si) VAR3 (TERNOP_NONE_NONE_NONE_UNONE, vshlq_m_r_s, v16qi, v8hi, v4si) VAR3 (TERNOP_NONE_NONE_NONE_UNONE, vrshlq_m_n_s, v16qi, v8hi, v4si) VAR3 (TERNOP_NONE_NONE_NONE_UNONE, vrev64q_m_s, v16qi, v8hi, v4si) @@ -405,17 +405,17 @@ VAR2 (TERNOP_UNONE_UNONE_NONE_IMM, vqshrunbq_n_s, v8hi, v4si) VAR2 (TERNOP_UNONE_UNONE_NONE_IMM, vqrshruntq_n_s, v8hi, v4si) VAR2 (TERNOP_UNONE_UNONE_IMM_UNONE, vorrq_m_n_u, v8hi, v4si) VAR2 (TERNOP_UNONE_UNONE_IMM_UNONE, vmvnq_m_n_u, v8hi, v4si) -VAR2 (TERNOP_UNONE_NONE_NONE_UNONE, vcmpneq_m_n_f, v8hf, v4sf) -VAR2 (TERNOP_UNONE_NONE_NONE_UNONE, vcmpneq_m_f, v8hf, v4sf) -VAR2 (TERNOP_UNONE_NONE_NONE_UNONE, vcmpltq_m_n_f, v8hf, v4sf) -VAR2 (TERNOP_UNONE_NONE_NONE_UNONE, vcmpltq_m_f, v8hf, v4sf) -VAR2 (TERNOP_UNONE_NONE_NONE_UNONE, vcmpleq_m_n_f, v8hf, v4sf) -VAR2 (TERNOP_UNONE_NONE_NONE_UNONE, vcmpleq_m_f, v8hf, v4sf) -VAR2 (TERNOP_UNONE_NONE_NONE_UNONE, vcmpgtq_m_n_f, v8hf, v4sf) -VAR2 (TERNOP_UNONE_NONE_NONE_UNONE, vcmpgtq_m_f, v8hf, v4sf) -VAR2 (TERNOP_UNONE_NONE_NONE_UNONE, vcmpgeq_m_n_f, v8hf, v4sf) -VAR2 (TERNOP_UNONE_NONE_NONE_UNONE, vcmpgeq_m_f, v8hf, v4sf) -VAR2 (TERNOP_UNONE_NONE_NONE_UNONE, vcmpeqq_m_n_f, v8hf, v4sf) +VAR2 (TERNOP_PRED_NONE_NONE_PRED, vcmpneq_m_n_f, v8hf, v4sf) +VAR2 (TERNOP_PRED_NONE_NONE_PRED, vcmpneq_m_f, v8hf, v4sf) +VAR2 (TERNOP_PRED_NONE_NONE_PRED, vcmpltq_m_n_f, v8hf, v4sf) +VAR2 (TERNOP_PRED_NONE_NONE_PRED, vcmpltq_m_f, v8hf, v4sf) +VAR2 (TERNOP_PRED_NONE_NONE_PRED, vcmpleq_m_n_f, v8hf, v4sf) +VAR2 (TERNOP_PRED_NONE_NONE_PRED, vcmpleq_m_f, v8hf, v4sf) +VAR2 (TERNOP_PRED_NONE_NONE_PRED, vcmpgtq_m_n_f, v8hf, v4sf) +VAR2 (TERNOP_PRED_NONE_NONE_PRED, vcmpgtq_m_f, v8hf, v4sf) +VAR2 (TERNOP_PRED_NONE_NONE_PRED, vcmpgeq_m_n_f, v8hf, v4sf) +VAR2 (TERNOP_PRED_NONE_NONE_PRED, vcmpgeq_m_f, v8hf, v4sf) +VAR2 (TERNOP_PRED_NONE_NONE_PRED, vcmpeqq_m_n_f, v8hf, v4sf) VAR2 (TERNOP_NONE_NONE_NONE_UNONE, vrndxq_m_f, v8hf, v4sf) VAR2 (TERNOP_NONE_NONE_NONE_UNONE, vrndq_m_f, v8hf, v4sf) VAR2 (TERNOP_NONE_NONE_NONE_UNONE, vrndpq_m_f, v8hf, v4sf) diff --git a/gcc/config/arm/mve.md b/gcc/config/arm/mve.md index d663c698cfb..4867aa79687 100644 --- a/gcc/config/arm/mve.md +++ b/gcc/config/arm/mve.md @@ -853,8 +853,8 @@ (define_insn "@mve_vcmp<mve_cmp_op>q_<mode>" ;; (define_insn "mve_vcmp<mve_cmp_op>q_n_<mode>" [ - (set (match_operand:HI 0 "vpr_register_operand" "=Up") - (MVE_COMPARISONS:HI (match_operand:MVE_2 1 "s_register_operand" "w") + (set (match_operand:<MVE_VPRED> 0 "vpr_register_operand" "=Up") + (MVE_COMPARISONS:<MVE_VPRED> (match_operand:MVE_2 1 "s_register_operand" "w") (match_operand:<V_elem> 2 "s_register_operand" "r"))) ] "TARGET_HAVE_MVE" @@ -1943,8 +1943,8 @@ (define_insn "@mve_vcmp<mve_cmp_op>q_f<mode>" ;; (define_insn "@mve_vcmp<mve_cmp_op>q_n_f<mode>" [ - (set (match_operand:HI 0 "vpr_register_operand" "=Up") - (MVE_FP_COMPARISONS:HI (match_operand:MVE_0 1 "s_register_operand" "w") + (set (match_operand:<MVE_VPRED> 0 "vpr_register_operand" "=Up") + (MVE_FP_COMPARISONS:<MVE_VPRED> (match_operand:MVE_0 1 "s_register_operand" "w") (match_operand:<V_elem> 2 "s_register_operand" "r"))) ] "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" @@ -2593,10 +2593,10 @@ (define_insn "mve_vbicq_m_n_<supf><mode>" ;; (define_insn "mve_vcmpeqq_m_f<mode>" [ - (set (match_operand:HI 0 "vpr_register_operand" "=Up") - (unspec:HI [(match_operand:MVE_0 1 "s_register_operand" "w") + (set (match_operand:<MVE_VPRED> 0 "vpr_register_operand" "=Up") + (unspec:<MVE_VPRED> [(match_operand:MVE_0 1 "s_register_operand" "w") (match_operand:MVE_0 2 "s_register_operand" "w") - (match_operand:HI 3 "vpr_register_operand" "Up")] + (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")] VCMPEQQ_M_F)) ] "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" @@ -2809,10 +2809,10 @@ (define_insn "mve_vclzq_m_<supf><mode>" ;; (define_insn "mve_vcmpcsq_m_n_u<mode>" [ - (set (match_operand:HI 0 "vpr_register_operand" "=Up") - (unspec:HI [(match_operand:MVE_2 1 "s_register_operand" "w") + (set (match_operand:<MVE_VPRED> 0 "vpr_register_operand" "=Up") + (unspec:<MVE_VPRED> [(match_operand:MVE_2 1 "s_register_operand" "w") (match_operand:<V_elem> 2 "s_register_operand" "r") - (match_operand:HI 3 "vpr_register_operand" "Up")] + (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")] VCMPCSQ_M_N_U)) ] "TARGET_HAVE_MVE" @@ -2825,10 +2825,10 @@ (define_insn "mve_vcmpcsq_m_n_u<mode>" ;; (define_insn "mve_vcmpcsq_m_u<mode>" [ - (set (match_operand:HI 0 "vpr_register_operand" "=Up") - (unspec:HI [(match_operand:MVE_2 1 "s_register_operand" "w") + (set (match_operand:<MVE_VPRED> 0 "vpr_register_operand" "=Up") + (unspec:<MVE_VPRED> [(match_operand:MVE_2 1 "s_register_operand" "w") (match_operand:MVE_2 2 "s_register_operand" "w") - (match_operand:HI 3 "vpr_register_operand" "Up")] + (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")] VCMPCSQ_M_U)) ] "TARGET_HAVE_MVE" @@ -2841,10 +2841,10 @@ (define_insn "mve_vcmpcsq_m_u<mode>" ;; (define_insn "mve_vcmpeqq_m_n_<supf><mode>" [ - (set (match_operand:HI 0 "vpr_register_operand" "=Up") - (unspec:HI [(match_operand:MVE_2 1 "s_register_operand" "w") + (set (match_operand:<MVE_VPRED> 0 "vpr_register_operand" "=Up") + (unspec:<MVE_VPRED> [(match_operand:MVE_2 1 "s_register_operand" "w") (match_operand:<V_elem> 2 "s_register_operand" "r") - (match_operand:HI 3 "vpr_register_operand" "Up")] + (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")] VCMPEQQ_M_N)) ] "TARGET_HAVE_MVE" @@ -2857,10 +2857,10 @@ (define_insn "mve_vcmpeqq_m_n_<supf><mode>" ;; (define_insn "mve_vcmpeqq_m_<supf><mode>" [ - (set (match_operand:HI 0 "vpr_register_operand" "=Up") - (unspec:HI [(match_operand:MVE_2 1 "s_register_operand" "w") + (set (match_operand:<MVE_VPRED> 0 "vpr_register_operand" "=Up") + (unspec:<MVE_VPRED> [(match_operand:MVE_2 1 "s_register_operand" "w") (match_operand:MVE_2 2 "s_register_operand" "w") - (match_operand:HI 3 "vpr_register_operand" "Up")] + (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")] VCMPEQQ_M)) ] "TARGET_HAVE_MVE" @@ -2873,10 +2873,10 @@ (define_insn "mve_vcmpeqq_m_<supf><mode>" ;; (define_insn "mve_vcmpgeq_m_n_s<mode>" [ - (set (match_operand:HI 0 "vpr_register_operand" "=Up") - (unspec:HI [(match_operand:MVE_2 1 "s_register_operand" "w") + (set (match_operand:<MVE_VPRED> 0 "vpr_register_operand" "=Up") + (unspec:<MVE_VPRED> [(match_operand:MVE_2 1 "s_register_operand" "w") (match_operand:<V_elem> 2 "s_register_operand" "r") - (match_operand:HI 3 "vpr_register_operand" "Up")] + (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")] VCMPGEQ_M_N_S)) ] "TARGET_HAVE_MVE" @@ -2889,10 +2889,10 @@ (define_insn "mve_vcmpgeq_m_n_s<mode>" ;; (define_insn "mve_vcmpgeq_m_s<mode>" [ - (set (match_operand:HI 0 "vpr_register_operand" "=Up") - (unspec:HI [(match_operand:MVE_2 1 "s_register_operand" "w") + (set (match_operand:<MVE_VPRED> 0 "vpr_register_operand" "=Up") + (unspec:<MVE_VPRED> [(match_operand:MVE_2 1 "s_register_operand" "w") (match_operand:MVE_2 2 "s_register_operand" "w") - (match_operand:HI 3 "vpr_register_operand" "Up")] + (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")] VCMPGEQ_M_S)) ] "TARGET_HAVE_MVE" @@ -2905,10 +2905,10 @@ (define_insn "mve_vcmpgeq_m_s<mode>" ;; (define_insn "mve_vcmpgtq_m_n_s<mode>" [ - (set (match_operand:HI 0 "vpr_register_operand" "=Up") - (unspec:HI [(match_operand:MVE_2 1 "s_register_operand" "w") + (set (match_operand:<MVE_VPRED> 0 "vpr_register_operand" "=Up") + (unspec:<MVE_VPRED> [(match_operand:MVE_2 1 "s_register_operand" "w") (match_operand:<V_elem> 2 "s_register_operand" "r") - (match_operand:HI 3 "vpr_register_operand" "Up")] + (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")] VCMPGTQ_M_N_S)) ] "TARGET_HAVE_MVE" @@ -2921,10 +2921,10 @@ (define_insn "mve_vcmpgtq_m_n_s<mode>" ;; (define_insn "mve_vcmpgtq_m_s<mode>" [ - (set (match_operand:HI 0 "vpr_register_operand" "=Up") - (unspec:HI [(match_operand:MVE_2 1 "s_register_operand" "w") + (set (match_operand:<MVE_VPRED> 0 "vpr_register_operand" "=Up") + (unspec:<MVE_VPRED> [(match_operand:MVE_2 1 "s_register_operand" "w") (match_operand:MVE_2 2 "s_register_operand" "w") - (match_operand:HI 3 "vpr_register_operand" "Up")] + (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")] VCMPGTQ_M_S)) ] "TARGET_HAVE_MVE" @@ -2937,10 +2937,10 @@ (define_insn "mve_vcmpgtq_m_s<mode>" ;; (define_insn "mve_vcmphiq_m_n_u<mode>" [ - (set (match_operand:HI 0 "vpr_register_operand" "=Up") - (unspec:HI [(match_operand:MVE_2 1 "s_register_operand" "w") + (set (match_operand:<MVE_VPRED> 0 "vpr_register_operand" "=Up") + (unspec:<MVE_VPRED> [(match_operand:MVE_2 1 "s_register_operand" "w") (match_operand:<V_elem> 2 "s_register_operand" "r") - (match_operand:HI 3 "vpr_register_operand" "Up")] + (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")] VCMPHIQ_M_N_U)) ] "TARGET_HAVE_MVE" @@ -2953,10 +2953,10 @@ (define_insn "mve_vcmphiq_m_n_u<mode>" ;; (define_insn "mve_vcmphiq_m_u<mode>" [ - (set (match_operand:HI 0 "vpr_register_operand" "=Up") - (unspec:HI [(match_operand:MVE_2 1 "s_register_operand" "w") + (set (match_operand:<MVE_VPRED> 0 "vpr_register_operand" "=Up") + (unspec:<MVE_VPRED> [(match_operand:MVE_2 1 "s_register_operand" "w") (match_operand:MVE_2 2 "s_register_operand" "w") - (match_operand:HI 3 "vpr_register_operand" "Up")] + (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")] VCMPHIQ_M_U)) ] "TARGET_HAVE_MVE" @@ -2969,10 +2969,10 @@ (define_insn "mve_vcmphiq_m_u<mode>" ;; (define_insn "mve_vcmpleq_m_n_s<mode>" [ - (set (match_operand:HI 0 "vpr_register_operand" "=Up") - (unspec:HI [(match_operand:MVE_2 1 "s_register_operand" "w") + (set (match_operand:<MVE_VPRED> 0 "vpr_register_operand" "=Up") + (unspec:<MVE_VPRED> [(match_operand:MVE_2 1 "s_register_operand" "w") (match_operand:<V_elem> 2 "s_register_operand" "r") - (match_operand:HI 3 "vpr_register_operand" "Up")] + (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")] VCMPLEQ_M_N_S)) ] "TARGET_HAVE_MVE" @@ -2985,10 +2985,10 @@ (define_insn "mve_vcmpleq_m_n_s<mode>" ;; (define_insn "mve_vcmpleq_m_s<mode>" [ - (set (match_operand:HI 0 "vpr_register_operand" "=Up") - (unspec:HI [(match_operand:MVE_2 1 "s_register_operand" "w") + (set (match_operand:<MVE_VPRED> 0 "vpr_register_operand" "=Up") + (unspec:<MVE_VPRED> [(match_operand:MVE_2 1 "s_register_operand" "w") (match_operand:MVE_2 2 "s_register_operand" "w") - (match_operand:HI 3 "vpr_register_operand" "Up")] + (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")] VCMPLEQ_M_S)) ] "TARGET_HAVE_MVE" @@ -3001,10 +3001,10 @@ (define_insn "mve_vcmpleq_m_s<mode>" ;; (define_insn "mve_vcmpltq_m_n_s<mode>" [ - (set (match_operand:HI 0 "vpr_register_operand" "=Up") - (unspec:HI [(match_operand:MVE_2 1 "s_register_operand" "w") + (set (match_operand:<MVE_VPRED> 0 "vpr_register_operand" "=Up") + (unspec:<MVE_VPRED> [(match_operand:MVE_2 1 "s_register_operand" "w") (match_operand:<V_elem> 2 "s_register_operand" "r") - (match_operand:HI 3 "vpr_register_operand" "Up")] + (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")] VCMPLTQ_M_N_S)) ] "TARGET_HAVE_MVE" @@ -3017,10 +3017,10 @@ (define_insn "mve_vcmpltq_m_n_s<mode>" ;; (define_insn "mve_vcmpltq_m_s<mode>" [ - (set (match_operand:HI 0 "vpr_register_operand" "=Up") - (unspec:HI [(match_operand:MVE_2 1 "s_register_operand" "w") + (set (match_operand:<MVE_VPRED> 0 "vpr_register_operand" "=Up") + (unspec:<MVE_VPRED> [(match_operand:MVE_2 1 "s_register_operand" "w") (match_operand:MVE_2 2 "s_register_operand" "w") - (match_operand:HI 3 "vpr_register_operand" "Up")] + (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")] VCMPLTQ_M_S)) ] "TARGET_HAVE_MVE" @@ -3033,10 +3033,10 @@ (define_insn "mve_vcmpltq_m_s<mode>" ;; (define_insn "mve_vcmpneq_m_n_<supf><mode>" [ - (set (match_operand:HI 0 "vpr_register_operand" "=Up") - (unspec:HI [(match_operand:MVE_2 1 "s_register_operand" "w") + (set (match_operand:<MVE_VPRED> 0 "vpr_register_operand" "=Up") + (unspec:<MVE_VPRED> [(match_operand:MVE_2 1 "s_register_operand" "w") (match_operand:<V_elem> 2 "s_register_operand" "r") - (match_operand:HI 3 "vpr_register_operand" "Up")] + (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")] VCMPNEQ_M_N)) ] "TARGET_HAVE_MVE" @@ -3049,10 +3049,10 @@ (define_insn "mve_vcmpneq_m_n_<supf><mode>" ;; (define_insn "mve_vcmpneq_m_<supf><mode>" [ - (set (match_operand:HI 0 "vpr_register_operand" "=Up") - (unspec:HI [(match_operand:MVE_2 1 "s_register_operand" "w") + (set (match_operand:<MVE_VPRED> 0 "vpr_register_operand" "=Up") + (unspec:<MVE_VPRED> [(match_operand:MVE_2 1 "s_register_operand" "w") (match_operand:MVE_2 2 "s_register_operand" "w") - (match_operand:HI 3 "vpr_register_operand" "Up")] + (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")] VCMPNEQ_M)) ] "TARGET_HAVE_MVE" @@ -3782,10 +3782,10 @@ (define_insn "mve_vcmlaq<mve_rot><mode>" ;; (define_insn "mve_vcmpeqq_m_n_f<mode>" [ - (set (match_operand:HI 0 "vpr_register_operand" "=Up") - (unspec:HI [(match_operand:MVE_0 1 "s_register_operand" "w") + (set (match_operand:<MVE_VPRED> 0 "vpr_register_operand" "=Up") + (unspec:<MVE_VPRED> [(match_operand:MVE_0 1 "s_register_operand" "w") (match_operand:<V_elem> 2 "s_register_operand" "r") - (match_operand:HI 3 "vpr_register_operand" "Up")] + (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")] VCMPEQQ_M_N_F)) ] "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" @@ -3798,10 +3798,10 @@ (define_insn "mve_vcmpeqq_m_n_f<mode>" ;; (define_insn "mve_vcmpgeq_m_f<mode>" [ - (set (match_operand:HI 0 "vpr_register_operand" "=Up") - (unspec:HI [(match_operand:MVE_0 1 "s_register_operand" "w") + (set (match_operand:<MVE_VPRED> 0 "vpr_register_operand" "=Up") + (unspec:<MVE_VPRED> [(match_operand:MVE_0 1 "s_register_operand" "w") (match_operand:MVE_0 2 "s_register_operand" "w") - (match_operand:HI 3 "vpr_register_operand" "Up")] + (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")] VCMPGEQ_M_F)) ] "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" @@ -3814,10 +3814,10 @@ (define_insn "mve_vcmpgeq_m_f<mode>" ;; (define_insn "mve_vcmpgeq_m_n_f<mode>" [ - (set (match_operand:HI 0 "vpr_register_operand" "=Up") - (unspec:HI [(match_operand:MVE_0 1 "s_register_operand" "w") + (set (match_operand:<MVE_VPRED> 0 "vpr_register_operand" "=Up") + (unspec:<MVE_VPRED> [(match_operand:MVE_0 1 "s_register_operand" "w") (match_operand:<V_elem> 2 "s_register_operand" "r") - (match_operand:HI 3 "vpr_register_operand" "Up")] + (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")] VCMPGEQ_M_N_F)) ] "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" @@ -3830,10 +3830,10 @@ (define_insn "mve_vcmpgeq_m_n_f<mode>" ;; (define_insn "mve_vcmpgtq_m_f<mode>" [ - (set (match_operand:HI 0 "vpr_register_operand" "=Up") - (unspec:HI [(match_operand:MVE_0 1 "s_register_operand" "w") + (set (match_operand:<MVE_VPRED> 0 "vpr_register_operand" "=Up") + (unspec:<MVE_VPRED> [(match_operand:MVE_0 1 "s_register_operand" "w") (match_operand:MVE_0 2 "s_register_operand" "w") - (match_operand:HI 3 "vpr_register_operand" "Up")] + (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")] VCMPGTQ_M_F)) ] "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" @@ -3846,10 +3846,10 @@ (define_insn "mve_vcmpgtq_m_f<mode>" ;; (define_insn "mve_vcmpgtq_m_n_f<mode>" [ - (set (match_operand:HI 0 "vpr_register_operand" "=Up") - (unspec:HI [(match_operand:MVE_0 1 "s_register_operand" "w") + (set (match_operand:<MVE_VPRED> 0 "vpr_register_operand" "=Up") + (unspec:<MVE_VPRED> [(match_operand:MVE_0 1 "s_register_operand" "w") (match_operand:<V_elem> 2 "s_register_operand" "r") - (match_operand:HI 3 "vpr_register_operand" "Up")] + (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")] VCMPGTQ_M_N_F)) ] "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" @@ -3862,10 +3862,10 @@ (define_insn "mve_vcmpgtq_m_n_f<mode>" ;; (define_insn "mve_vcmpleq_m_f<mode>" [ - (set (match_operand:HI 0 "vpr_register_operand" "=Up") - (unspec:HI [(match_operand:MVE_0 1 "s_register_operand" "w") + (set (match_operand:<MVE_VPRED> 0 "vpr_register_operand" "=Up") + (unspec:<MVE_VPRED> [(match_operand:MVE_0 1 "s_register_operand" "w") (match_operand:MVE_0 2 "s_register_operand" "w") - (match_operand:HI 3 "vpr_register_operand" "Up")] + (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")] VCMPLEQ_M_F)) ] "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" @@ -3878,10 +3878,10 @@ (define_insn "mve_vcmpleq_m_f<mode>" ;; (define_insn "mve_vcmpleq_m_n_f<mode>" [ - (set (match_operand:HI 0 "vpr_register_operand" "=Up") - (unspec:HI [(match_operand:MVE_0 1 "s_register_operand" "w") + (set (match_operand:<MVE_VPRED> 0 "vpr_register_operand" "=Up") + (unspec:<MVE_VPRED> [(match_operand:MVE_0 1 "s_register_operand" "w") (match_operand:<V_elem> 2 "s_register_operand" "r") - (match_operand:HI 3 "vpr_register_operand" "Up")] + (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")] VCMPLEQ_M_N_F)) ] "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" @@ -3894,10 +3894,10 @@ (define_insn "mve_vcmpleq_m_n_f<mode>" ;; (define_insn "mve_vcmpltq_m_f<mode>" [ - (set (match_operand:HI 0 "vpr_register_operand" "=Up") - (unspec:HI [(match_operand:MVE_0 1 "s_register_operand" "w") + (set (match_operand:<MVE_VPRED> 0 "vpr_register_operand" "=Up") + (unspec:<MVE_VPRED> [(match_operand:MVE_0 1 "s_register_operand" "w") (match_operand:MVE_0 2 "s_register_operand" "w") - (match_operand:HI 3 "vpr_register_operand" "Up")] + (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")] VCMPLTQ_M_F)) ] "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" @@ -3910,10 +3910,10 @@ (define_insn "mve_vcmpltq_m_f<mode>" ;; (define_insn "mve_vcmpltq_m_n_f<mode>" [ - (set (match_operand:HI 0 "vpr_register_operand" "=Up") - (unspec:HI [(match_operand:MVE_0 1 "s_register_operand" "w") + (set (match_operand:<MVE_VPRED> 0 "vpr_register_operand" "=Up") + (unspec:<MVE_VPRED> [(match_operand:MVE_0 1 "s_register_operand" "w") (match_operand:<V_elem> 2 "s_register_operand" "r") - (match_operand:HI 3 "vpr_register_operand" "Up")] + (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")] VCMPLTQ_M_N_F)) ] "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" @@ -3926,10 +3926,10 @@ (define_insn "mve_vcmpltq_m_n_f<mode>" ;; (define_insn "mve_vcmpneq_m_f<mode>" [ - (set (match_operand:HI 0 "vpr_register_operand" "=Up") - (unspec:HI [(match_operand:MVE_0 1 "s_register_operand" "w") + (set (match_operand:<MVE_VPRED> 0 "vpr_register_operand" "=Up") + (unspec:<MVE_VPRED> [(match_operand:MVE_0 1 "s_register_operand" "w") (match_operand:MVE_0 2 "s_register_operand" "w") - (match_operand:HI 3 "vpr_register_operand" "Up")] + (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")] VCMPNEQ_M_F)) ] "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" @@ -3942,10 +3942,10 @@ (define_insn "mve_vcmpneq_m_f<mode>" ;; (define_insn "mve_vcmpneq_m_n_f<mode>" [ - (set (match_operand:HI 0 "vpr_register_operand" "=Up") - (unspec:HI [(match_operand:MVE_0 1 "s_register_operand" "w") + (set (match_operand:<MVE_VPRED> 0 "vpr_register_operand" "=Up") + (unspec:<MVE_VPRED> [(match_operand:MVE_0 1 "s_register_operand" "w") (match_operand:<V_elem> 2 "s_register_operand" "r") - (match_operand:HI 3 "vpr_register_operand" "Up")] + (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")] VCMPNEQ_M_N_F)) ] "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" -- 2.25.1 ^ permalink raw reply [flat|nested] 9+ messages in thread
* [PATCH 11/13] arm: Convert more MVE builtins to predicate qualifiers 2021-09-07 9:20 [PATCH 10/13] arm: Convert remaining MVE vcmp builtins to predicate qualifiers Christophe Lyon @ 2021-09-07 9:20 ` Christophe Lyon 2021-10-11 14:17 ` Richard Sandiford 2021-09-07 9:20 ` [PATCH 12/13] arm: Convert more load/store " Christophe Lyon ` (2 subsequent siblings) 3 siblings, 1 reply; 9+ messages in thread From: Christophe Lyon @ 2021-09-07 9:20 UTC (permalink / raw) To: gcc-patches This patch covers all builtins that have an HI operand and use the <mode> iterator, thus we can replace HI whe <MVE_vpred>. 2021-09-02 Christophe Lyon <christophe.lyon@foss.st.com> gcc/ PR target/100757 PR target/101325 * config/arm/arm-builtins.c (TERNOP_UNONE_UNONE_NONE_UNONE_QUALIFIERS): Change to ... (TERNOP_UNONE_UNONE_NONE_PRED_QUALIFIERS): ... this. (TERNOP_UNONE_UNONE_IMM_UNONE_QUALIFIERS): Change to ... (TERNOP_UNONE_UNONE_IMM_PRED_QUALIFIERS): ... this. (TERNOP_NONE_NONE_IMM_UNONE_QUALIFIERS): Change to ... (TERNOP_NONE_NONE_IMM_PRED_QUALIFIERS): ... this. (TERNOP_NONE_NONE_UNONE_UNONE_QUALIFIERS): Change to ... (TERNOP_NONE_NONE_UNONE_PRED_QUALIFIERS): ... this. (QUADOP_UNONE_UNONE_NONE_NONE_UNONE_QUALIFIERS): Change to ... (QUADOP_UNONE_UNONE_NONE_NONE_PRED_QUALIFIERS): ... this. (QUADOP_NONE_NONE_NONE_NONE_PRED_QUALIFIERS): New. (QUADOP_NONE_NONE_NONE_IMM_UNONE_QUALIFIERS): Change to ... (QUADOP_NONE_NONE_NONE_IMM_PRED_QUALIFIERS): ... this. (QUADOP_UNONE_UNONE_UNONE_UNONE_PRED_QUALIFIERS): New. (QUADOP_UNONE_UNONE_NONE_IMM_UNONE_QUALIFIERS): Change to ... (QUADOP_UNONE_UNONE_NONE_IMM_PRED_QUALIFIERS): ... this. (QUADOP_NONE_NONE_UNONE_IMM_UNONE_QUALIFIERS): Change to ... (QUADOP_NONE_NONE_UNONE_IMM_PRED_QUALIFIERS): ... this. (QUADOP_UNONE_UNONE_UNONE_IMM_UNONE_QUALIFIERS): Change to ... (QUADOP_UNONE_UNONE_UNONE_IMM_PRED_QUALIFIERS): ... this. (QUADOP_UNONE_UNONE_UNONE_NONE_UNONE_QUALIFIERS): Change to ... (QUADOP_UNONE_UNONE_UNONE_NONE_PRED_QUALIFIERS): ... this. (STRS_P_QUALIFIERS): Use predicate qualifier. (STRU_P_QUALIFIERS): Likewise. (STRSU_P_QUALIFIERS): Likewise. (STRSS_P_QUALIFIERS): Likewise. (LDRGS_Z_QUALIFIERS): Likewise. (LDRGU_Z_QUALIFIERS): Likewise. (LDRS_Z_QUALIFIERS): Likewise. (LDRU_Z_QUALIFIERS): Likewise. (QUINOP_UNONE_UNONE_UNONE_UNONE_IMM_UNONE_QUALIFIERS): Change to ... (QUINOP_UNONE_UNONE_UNONE_UNONE_IMM_PRED_QUALIFIERS): ... this. (BINOP_NONE_NONE_PRED_QUALIFIERS): New. (BINOP_UNONE_UNONE_PRED_QUALIFIERS): New. * config/arm/arm_mve_builtins.def: Use new predicated qualifiers. * config/arm/mve.md: Use MVE_VPRED instead of HI. diff --git a/gcc/config/arm/arm-builtins.c b/gcc/config/arm/arm-builtins.c index b3455d87d4f..06ff9d2278a 100644 --- a/gcc/config/arm/arm-builtins.c +++ b/gcc/config/arm/arm-builtins.c @@ -533,18 +533,18 @@ arm_ternop_unone_unone_none_imm_qualifiers[SIMD_MAX_BUILTIN_ARGS] (arm_ternop_unone_unone_none_imm_qualifiers) static enum arm_type_qualifiers -arm_ternop_unone_unone_none_unone_qualifiers[SIMD_MAX_BUILTIN_ARGS] +arm_ternop_unone_unone_none_pred_qualifiers[SIMD_MAX_BUILTIN_ARGS] = { qualifier_unsigned, qualifier_unsigned, qualifier_none, - qualifier_unsigned }; -#define TERNOP_UNONE_UNONE_NONE_UNONE_QUALIFIERS \ - (arm_ternop_unone_unone_none_unone_qualifiers) + qualifier_predicate }; +#define TERNOP_UNONE_UNONE_NONE_PRED_QUALIFIERS \ + (arm_ternop_unone_unone_none_pred_qualifiers) static enum arm_type_qualifiers -arm_ternop_unone_unone_imm_unone_qualifiers[SIMD_MAX_BUILTIN_ARGS] +arm_ternop_unone_unone_imm_pred_qualifiers[SIMD_MAX_BUILTIN_ARGS] = { qualifier_unsigned, qualifier_unsigned, qualifier_immediate, - qualifier_unsigned }; -#define TERNOP_UNONE_UNONE_IMM_UNONE_QUALIFIERS \ - (arm_ternop_unone_unone_imm_unone_qualifiers) + qualifier_predicate }; +#define TERNOP_UNONE_UNONE_IMM_PRED_QUALIFIERS \ + (arm_ternop_unone_unone_imm_pred_qualifiers) static enum arm_type_qualifiers arm_ternop_pred_none_none_pred_qualifiers[SIMD_MAX_BUILTIN_ARGS] @@ -571,16 +571,16 @@ arm_ternop_none_none_none_pred_qualifiers[SIMD_MAX_BUILTIN_ARGS] (arm_ternop_none_none_none_pred_qualifiers) static enum arm_type_qualifiers -arm_ternop_none_none_imm_unone_qualifiers[SIMD_MAX_BUILTIN_ARGS] - = { qualifier_none, qualifier_none, qualifier_immediate, qualifier_unsigned }; -#define TERNOP_NONE_NONE_IMM_UNONE_QUALIFIERS \ - (arm_ternop_none_none_imm_unone_qualifiers) +arm_ternop_none_none_imm_pred_qualifiers[SIMD_MAX_BUILTIN_ARGS] + = { qualifier_none, qualifier_none, qualifier_immediate, qualifier_predicate }; +#define TERNOP_NONE_NONE_IMM_PRED_QUALIFIERS \ + (arm_ternop_none_none_imm_pred_qualifiers) static enum arm_type_qualifiers -arm_ternop_none_none_unone_unone_qualifiers[SIMD_MAX_BUILTIN_ARGS] - = { qualifier_none, qualifier_none, qualifier_unsigned, qualifier_unsigned }; -#define TERNOP_NONE_NONE_UNONE_UNONE_QUALIFIERS \ - (arm_ternop_none_none_unone_unone_qualifiers) +arm_ternop_none_none_unone_pred_qualifiers[SIMD_MAX_BUILTIN_ARGS] + = { qualifier_none, qualifier_none, qualifier_unsigned, qualifier_predicate }; +#define TERNOP_NONE_NONE_UNONE_PRED_QUALIFIERS \ + (arm_ternop_none_none_unone_pred_qualifiers) static enum arm_type_qualifiers arm_ternop_unone_unone_unone_unone_qualifiers[SIMD_MAX_BUILTIN_ARGS] @@ -610,11 +610,11 @@ arm_ternop_none_none_none_none_qualifiers[SIMD_MAX_BUILTIN_ARGS] (arm_ternop_none_none_none_none_qualifiers) static enum arm_type_qualifiers -arm_quadop_unone_unone_none_none_unone_qualifiers[SIMD_MAX_BUILTIN_ARGS] +arm_quadop_unone_unone_none_none_pred_qualifiers[SIMD_MAX_BUILTIN_ARGS] = { qualifier_unsigned, qualifier_unsigned, qualifier_none, qualifier_none, - qualifier_unsigned }; -#define QUADOP_UNONE_UNONE_NONE_NONE_UNONE_QUALIFIERS \ - (arm_quadop_unone_unone_none_none_unone_qualifiers) + qualifier_predicate }; +#define QUADOP_UNONE_UNONE_NONE_NONE_PRED_QUALIFIERS \ + (arm_quadop_unone_unone_none_none_pred_qualifiers) static enum arm_type_qualifiers arm_quadop_none_none_none_none_unone_qualifiers[SIMD_MAX_BUILTIN_ARGS] @@ -624,11 +624,18 @@ arm_quadop_none_none_none_none_unone_qualifiers[SIMD_MAX_BUILTIN_ARGS] (arm_quadop_none_none_none_none_unone_qualifiers) static enum arm_type_qualifiers -arm_quadop_none_none_none_imm_unone_qualifiers[SIMD_MAX_BUILTIN_ARGS] +arm_quadop_none_none_none_none_pred_qualifiers[SIMD_MAX_BUILTIN_ARGS] + = { qualifier_none, qualifier_none, qualifier_none, qualifier_none, + qualifier_predicate }; +#define QUADOP_NONE_NONE_NONE_NONE_PRED_QUALIFIERS \ + (arm_quadop_none_none_none_none_pred_qualifiers) + +static enum arm_type_qualifiers +arm_quadop_none_none_none_imm_pred_qualifiers[SIMD_MAX_BUILTIN_ARGS] = { qualifier_none, qualifier_none, qualifier_none, qualifier_immediate, - qualifier_unsigned }; -#define QUADOP_NONE_NONE_NONE_IMM_UNONE_QUALIFIERS \ - (arm_quadop_none_none_none_imm_unone_qualifiers) + qualifier_predicate }; +#define QUADOP_NONE_NONE_NONE_IMM_PRED_QUALIFIERS \ + (arm_quadop_none_none_none_imm_pred_qualifiers) static enum arm_type_qualifiers arm_quadop_unone_unone_unone_unone_unone_qualifiers[SIMD_MAX_BUILTIN_ARGS] @@ -638,32 +645,39 @@ arm_quadop_unone_unone_unone_unone_unone_qualifiers[SIMD_MAX_BUILTIN_ARGS] (arm_quadop_unone_unone_unone_unone_unone_qualifiers) static enum arm_type_qualifiers -arm_quadop_unone_unone_none_imm_unone_qualifiers[SIMD_MAX_BUILTIN_ARGS] +arm_quadop_unone_unone_unone_unone_pred_qualifiers[SIMD_MAX_BUILTIN_ARGS] + = { qualifier_unsigned, qualifier_unsigned, qualifier_unsigned, + qualifier_unsigned, qualifier_predicate }; +#define QUADOP_UNONE_UNONE_UNONE_UNONE_PRED_QUALIFIERS \ + (arm_quadop_unone_unone_unone_unone_pred_qualifiers) + +static enum arm_type_qualifiers +arm_quadop_unone_unone_none_imm_pred_qualifiers[SIMD_MAX_BUILTIN_ARGS] = { qualifier_unsigned, qualifier_unsigned, qualifier_none, - qualifier_immediate, qualifier_unsigned }; -#define QUADOP_UNONE_UNONE_NONE_IMM_UNONE_QUALIFIERS \ - (arm_quadop_unone_unone_none_imm_unone_qualifiers) + qualifier_immediate, qualifier_predicate }; +#define QUADOP_UNONE_UNONE_NONE_IMM_PRED_QUALIFIERS \ + (arm_quadop_unone_unone_none_imm_pred_qualifiers) static enum arm_type_qualifiers -arm_quadop_none_none_unone_imm_unone_qualifiers[SIMD_MAX_BUILTIN_ARGS] +arm_quadop_none_none_unone_imm_pred_qualifiers[SIMD_MAX_BUILTIN_ARGS] = { qualifier_none, qualifier_none, qualifier_unsigned, qualifier_immediate, - qualifier_unsigned }; -#define QUADOP_NONE_NONE_UNONE_IMM_UNONE_QUALIFIERS \ - (arm_quadop_none_none_unone_imm_unone_qualifiers) + qualifier_predicate }; +#define QUADOP_NONE_NONE_UNONE_IMM_PRED_QUALIFIERS \ + (arm_quadop_none_none_unone_imm_pred_qualifiers) static enum arm_type_qualifiers -arm_quadop_unone_unone_unone_imm_unone_qualifiers[SIMD_MAX_BUILTIN_ARGS] +arm_quadop_unone_unone_unone_imm_pred_qualifiers[SIMD_MAX_BUILTIN_ARGS] = { qualifier_unsigned, qualifier_unsigned, qualifier_unsigned, - qualifier_immediate, qualifier_unsigned }; -#define QUADOP_UNONE_UNONE_UNONE_IMM_UNONE_QUALIFIERS \ - (arm_quadop_unone_unone_unone_imm_unone_qualifiers) + qualifier_immediate, qualifier_predicate }; +#define QUADOP_UNONE_UNONE_UNONE_IMM_PRED_QUALIFIERS \ + (arm_quadop_unone_unone_unone_imm_pred_qualifiers) static enum arm_type_qualifiers -arm_quadop_unone_unone_unone_none_unone_qualifiers[SIMD_MAX_BUILTIN_ARGS] +arm_quadop_unone_unone_unone_none_pred_qualifiers[SIMD_MAX_BUILTIN_ARGS] = { qualifier_unsigned, qualifier_unsigned, qualifier_unsigned, - qualifier_none, qualifier_unsigned }; -#define QUADOP_UNONE_UNONE_UNONE_NONE_UNONE_QUALIFIERS \ - (arm_quadop_unone_unone_unone_none_unone_qualifiers) + qualifier_none, qualifier_predicate }; +#define QUADOP_UNONE_UNONE_UNONE_NONE_PRED_QUALIFIERS \ + (arm_quadop_unone_unone_unone_none_pred_qualifiers) static enum arm_type_qualifiers arm_strs_qualifiers[SIMD_MAX_BUILTIN_ARGS] @@ -700,25 +714,25 @@ arm_strsbu_qualifiers[SIMD_MAX_BUILTIN_ARGS] static enum arm_type_qualifiers arm_strs_p_qualifiers[SIMD_MAX_BUILTIN_ARGS] - = { qualifier_void, qualifier_pointer, qualifier_none, qualifier_unsigned}; + = { qualifier_void, qualifier_pointer, qualifier_none, qualifier_predicate}; #define STRS_P_QUALIFIERS (arm_strs_p_qualifiers) static enum arm_type_qualifiers arm_stru_p_qualifiers[SIMD_MAX_BUILTIN_ARGS] = { qualifier_void, qualifier_pointer, qualifier_unsigned, - qualifier_unsigned}; + qualifier_predicate}; #define STRU_P_QUALIFIERS (arm_stru_p_qualifiers) static enum arm_type_qualifiers arm_strsu_p_qualifiers[SIMD_MAX_BUILTIN_ARGS] = { qualifier_void, qualifier_pointer, qualifier_unsigned, - qualifier_unsigned, qualifier_unsigned}; + qualifier_unsigned, qualifier_predicate}; #define STRSU_P_QUALIFIERS (arm_strsu_p_qualifiers) static enum arm_type_qualifiers arm_strss_p_qualifiers[SIMD_MAX_BUILTIN_ARGS] = { qualifier_void, qualifier_pointer, qualifier_unsigned, - qualifier_none, qualifier_unsigned}; + qualifier_none, qualifier_predicate}; #define STRSS_P_QUALIFIERS (arm_strss_p_qualifiers) static enum arm_type_qualifiers @@ -778,31 +792,31 @@ arm_ldrgbu_z_qualifiers[SIMD_MAX_BUILTIN_ARGS] static enum arm_type_qualifiers arm_ldrgs_z_qualifiers[SIMD_MAX_BUILTIN_ARGS] = { qualifier_none, qualifier_pointer, qualifier_unsigned, - qualifier_unsigned}; + qualifier_predicate}; #define LDRGS_Z_QUALIFIERS (arm_ldrgs_z_qualifiers) static enum arm_type_qualifiers arm_ldrgu_z_qualifiers[SIMD_MAX_BUILTIN_ARGS] = { qualifier_unsigned, qualifier_pointer, qualifier_unsigned, - qualifier_unsigned}; + qualifier_predicate}; #define LDRGU_Z_QUALIFIERS (arm_ldrgu_z_qualifiers) static enum arm_type_qualifiers arm_ldrs_z_qualifiers[SIMD_MAX_BUILTIN_ARGS] - = { qualifier_none, qualifier_pointer, qualifier_unsigned}; + = { qualifier_none, qualifier_pointer, qualifier_predicate}; #define LDRS_Z_QUALIFIERS (arm_ldrs_z_qualifiers) static enum arm_type_qualifiers arm_ldru_z_qualifiers[SIMD_MAX_BUILTIN_ARGS] - = { qualifier_unsigned, qualifier_pointer, qualifier_unsigned}; + = { qualifier_unsigned, qualifier_pointer, qualifier_predicate}; #define LDRU_Z_QUALIFIERS (arm_ldru_z_qualifiers) static enum arm_type_qualifiers -arm_quinop_unone_unone_unone_unone_imm_unone_qualifiers[SIMD_MAX_BUILTIN_ARGS] +arm_quinop_unone_unone_unone_unone_imm_pred_qualifiers[SIMD_MAX_BUILTIN_ARGS] = { qualifier_unsigned, qualifier_unsigned, qualifier_unsigned, - qualifier_unsigned, qualifier_immediate, qualifier_unsigned }; -#define QUINOP_UNONE_UNONE_UNONE_UNONE_IMM_UNONE_QUALIFIERS \ - (arm_quinop_unone_unone_unone_unone_imm_unone_qualifiers) + qualifier_unsigned, qualifier_immediate, qualifier_predicate }; +#define QUINOP_UNONE_UNONE_UNONE_UNONE_IMM_PRED_QUALIFIERS \ + (arm_quinop_unone_unone_unone_unone_imm_pred_qualifiers) static enum arm_type_qualifiers arm_ldrgbwbxu_qualifiers[SIMD_MAX_BUILTIN_ARGS] @@ -879,6 +893,18 @@ arm_sqshl_qualifiers[SIMD_MAX_BUILTIN_ARGS] = { qualifier_unsigned, qualifier_unsigned, qualifier_const}; #define SQSHL_QUALIFIERS (arm_sqshl_qualifiers) +static enum arm_type_qualifiers +arm_binop_none_none_pred_qualifiers[SIMD_MAX_BUILTIN_ARGS] + = { qualifier_none, qualifier_none, qualifier_predicate }; +#define BINOP_NONE_NONE_PRED_QUALIFIERS \ + (arm_binop_none_none_pred_qualifiers) + +static enum arm_type_qualifiers +arm_binop_unone_unone_pred_qualifiers[SIMD_MAX_BUILTIN_ARGS] + = { qualifier_unsigned, qualifier_unsigned, qualifier_predicate }; +#define BINOP_UNONE_UNONE_PRED_QUALIFIERS \ + (arm_binop_unone_unone_pred_qualifiers) + /* End of Qualifier for MVE builtins. */ /* void ([T element type] *, T, immediate). */ diff --git a/gcc/config/arm/arm_mve_builtins.def b/gcc/config/arm/arm_mve_builtins.def index 91ed2073918..bb79edf83ca 100644 --- a/gcc/config/arm/arm_mve_builtins.def +++ b/gcc/config/arm/arm_mve_builtins.def @@ -123,7 +123,7 @@ VAR3 (BINOP_PRED_UNONE_UNONE, vcmpcsq_, v16qi, v8hi, v4si) VAR3 (BINOP_PRED_UNONE_UNONE, vcmpcsq_n_, v16qi, v8hi, v4si) VAR3 (BINOP_UNONE_UNONE_UNONE, vbicq_u, v16qi, v8hi, v4si) VAR3 (BINOP_UNONE_UNONE_UNONE, vandq_u, v16qi, v8hi, v4si) -VAR3 (BINOP_UNONE_UNONE_UNONE, vaddvq_p_u, v16qi, v8hi, v4si) +VAR3 (BINOP_UNONE_UNONE_PRED, vaddvq_p_u, v16qi, v8hi, v4si) VAR3 (BINOP_UNONE_UNONE_UNONE, vaddvaq_u, v16qi, v8hi, v4si) VAR3 (BINOP_UNONE_UNONE_UNONE, vaddq_n_u, v16qi, v8hi, v4si) VAR3 (BINOP_UNONE_UNONE_UNONE, vabdq_u, v16qi, v8hi, v4si) @@ -154,7 +154,7 @@ VAR3 (BINOP_PRED_NONE_NONE, vcmpgeq_n_, v16qi, v8hi, v4si) VAR3 (BINOP_PRED_NONE_NONE, vcmpeqq_, v16qi, v8hi, v4si) VAR3 (BINOP_PRED_NONE_NONE, vcmpeqq_n_, v16qi, v8hi, v4si) VAR3 (BINOP_UNONE_NONE_IMM, vqshluq_n_s, v16qi, v8hi, v4si) -VAR3 (BINOP_NONE_NONE_UNONE, vaddvq_p_s, v16qi, v8hi, v4si) +VAR3 (BINOP_NONE_NONE_PRED, vaddvq_p_s, v16qi, v8hi, v4si) VAR3 (BINOP_NONE_NONE_NONE, vsubq_s, v16qi, v8hi, v4si) VAR3 (BINOP_NONE_NONE_NONE, vsubq_n_s, v16qi, v8hi, v4si) VAR3 (BINOP_NONE_NONE_NONE, vshlq_r_s, v16qi, v8hi, v4si) @@ -277,35 +277,35 @@ VAR1 (BINOP_NONE_NONE_NONE, vrmlaldavhq_s, v4si) VAR1 (BINOP_NONE_NONE_NONE, vcvttq_f16_f32, v8hf) VAR1 (BINOP_NONE_NONE_NONE, vcvtbq_f16_f32, v8hf) VAR1 (BINOP_NONE_NONE_NONE, vaddlvaq_s, v4si) -VAR2 (TERNOP_NONE_NONE_IMM_UNONE, vbicq_m_n_s, v8hi, v4si) -VAR2 (TERNOP_UNONE_UNONE_IMM_UNONE, vbicq_m_n_u, v8hi, v4si) +VAR2 (TERNOP_NONE_NONE_IMM_PRED, vbicq_m_n_s, v8hi, v4si) +VAR2 (TERNOP_UNONE_UNONE_IMM_PRED, vbicq_m_n_u, v8hi, v4si) VAR2 (TERNOP_NONE_NONE_NONE_IMM, vqrshrnbq_n_s, v8hi, v4si) VAR2 (TERNOP_UNONE_UNONE_UNONE_IMM, vqrshrnbq_n_u, v8hi, v4si) VAR1 (TERNOP_NONE_NONE_NONE_NONE, vrmlaldavhaq_s, v4si) VAR1 (TERNOP_UNONE_UNONE_UNONE_UNONE, vrmlaldavhaq_u, v4si) -VAR2 (TERNOP_NONE_NONE_UNONE_UNONE, vcvtq_m_to_f_u, v8hf, v4sf) -VAR2 (TERNOP_NONE_NONE_NONE_UNONE, vcvtq_m_to_f_s, v8hf, v4sf) +VAR2 (TERNOP_NONE_NONE_UNONE_PRED, vcvtq_m_to_f_u, v8hf, v4sf) +VAR2 (TERNOP_NONE_NONE_NONE_PRED, vcvtq_m_to_f_s, v8hf, v4sf) VAR2 (TERNOP_PRED_NONE_NONE_PRED, vcmpeqq_m_f, v8hf, v4sf) VAR3 (TERNOP_UNONE_NONE_UNONE_IMM, vshlcq_carry_s, v16qi, v8hi, v4si) VAR3 (TERNOP_UNONE_UNONE_UNONE_IMM, vshlcq_carry_u, v16qi, v8hi, v4si) VAR2 (TERNOP_UNONE_UNONE_NONE_IMM, vqrshrunbq_n_s, v8hi, v4si) VAR3 (TERNOP_UNONE_UNONE_NONE_NONE, vabavq_s, v16qi, v8hi, v4si) VAR3 (TERNOP_UNONE_UNONE_UNONE_UNONE, vabavq_u, v16qi, v8hi, v4si) -VAR2 (TERNOP_UNONE_UNONE_NONE_UNONE, vcvtaq_m_u, v8hi, v4si) -VAR2 (TERNOP_NONE_NONE_NONE_UNONE, vcvtaq_m_s, v8hi, v4si) +VAR2 (TERNOP_UNONE_UNONE_NONE_PRED, vcvtaq_m_u, v8hi, v4si) +VAR2 (TERNOP_NONE_NONE_NONE_PRED, vcvtaq_m_s, v8hi, v4si) VAR3 (TERNOP_UNONE_UNONE_UNONE_IMM, vshlcq_vec_u, v16qi, v8hi, v4si) VAR3 (TERNOP_NONE_NONE_UNONE_IMM, vshlcq_vec_s, v16qi, v8hi, v4si) VAR4 (TERNOP_UNONE_UNONE_UNONE_PRED, vpselq_u, v16qi, v8hi, v4si, v2di) VAR4 (TERNOP_NONE_NONE_NONE_PRED, vpselq_s, v16qi, v8hi, v4si, v2di) -VAR3 (TERNOP_UNONE_UNONE_UNONE_UNONE, vrev64q_m_u, v16qi, v8hi, v4si) -VAR3 (TERNOP_UNONE_UNONE_UNONE_UNONE, vmvnq_m_u, v16qi, v8hi, v4si) +VAR3 (TERNOP_UNONE_UNONE_UNONE_PRED, vrev64q_m_u, v16qi, v8hi, v4si) +VAR3 (TERNOP_UNONE_UNONE_UNONE_PRED, vmvnq_m_u, v16qi, v8hi, v4si) VAR3 (TERNOP_UNONE_UNONE_UNONE_UNONE, vmlasq_n_u, v16qi, v8hi, v4si) VAR3 (TERNOP_UNONE_UNONE_UNONE_UNONE, vmlaq_n_u, v16qi, v8hi, v4si) -VAR3 (TERNOP_UNONE_UNONE_UNONE_UNONE, vmladavq_p_u, v16qi, v8hi, v4si) +VAR3 (TERNOP_UNONE_UNONE_UNONE_PRED, vmladavq_p_u, v16qi, v8hi, v4si) VAR3 (TERNOP_UNONE_UNONE_UNONE_UNONE, vmladavaq_u, v16qi, v8hi, v4si) -VAR3 (TERNOP_UNONE_UNONE_UNONE_UNONE, vminvq_p_u, v16qi, v8hi, v4si) -VAR3 (TERNOP_UNONE_UNONE_UNONE_UNONE, vmaxvq_p_u, v16qi, v8hi, v4si) -VAR3 (TERNOP_UNONE_UNONE_UNONE_UNONE, vdupq_m_n_u, v16qi, v8hi, v4si) +VAR3 (TERNOP_UNONE_UNONE_UNONE_PRED, vminvq_p_u, v16qi, v8hi, v4si) +VAR3 (TERNOP_UNONE_UNONE_UNONE_PRED, vmaxvq_p_u, v16qi, v8hi, v4si) +VAR3 (TERNOP_UNONE_UNONE_UNONE_PRED, vdupq_m_n_u, v16qi, v8hi, v4si) VAR3 (TERNOP_PRED_UNONE_UNONE_PRED, vcmpneq_m_u, v16qi, v8hi, v4si) VAR3 (TERNOP_PRED_UNONE_UNONE_PRED, vcmpneq_m_n_u, v16qi, v8hi, v4si) VAR3 (TERNOP_PRED_UNONE_UNONE_PRED, vcmphiq_m_u, v16qi, v8hi, v4si) @@ -314,18 +314,18 @@ VAR3 (TERNOP_PRED_UNONE_UNONE_PRED, vcmpeqq_m_u, v16qi, v8hi, v4si) VAR3 (TERNOP_PRED_UNONE_UNONE_PRED, vcmpeqq_m_n_u, v16qi, v8hi, v4si) VAR3 (TERNOP_PRED_UNONE_UNONE_PRED, vcmpcsq_m_u, v16qi, v8hi, v4si) VAR3 (TERNOP_PRED_UNONE_UNONE_PRED, vcmpcsq_m_n_u, v16qi, v8hi, v4si) -VAR3 (TERNOP_UNONE_UNONE_UNONE_UNONE, vclzq_m_u, v16qi, v8hi, v4si) -VAR3 (TERNOP_UNONE_UNONE_UNONE_UNONE, vaddvaq_p_u, v16qi, v8hi, v4si) +VAR3 (TERNOP_UNONE_UNONE_UNONE_PRED, vclzq_m_u, v16qi, v8hi, v4si) +VAR3 (TERNOP_UNONE_UNONE_UNONE_PRED, vaddvaq_p_u, v16qi, v8hi, v4si) VAR3 (TERNOP_UNONE_UNONE_UNONE_IMM, vsriq_n_u, v16qi, v8hi, v4si) VAR3 (TERNOP_UNONE_UNONE_UNONE_IMM, vsliq_n_u, v16qi, v8hi, v4si) -VAR3 (TERNOP_UNONE_UNONE_NONE_UNONE, vshlq_m_r_u, v16qi, v8hi, v4si) -VAR3 (TERNOP_UNONE_UNONE_NONE_UNONE, vrshlq_m_n_u, v16qi, v8hi, v4si) -VAR3 (TERNOP_UNONE_UNONE_NONE_UNONE, vqshlq_m_r_u, v16qi, v8hi, v4si) -VAR3 (TERNOP_UNONE_UNONE_NONE_UNONE, vqrshlq_m_n_u, v16qi, v8hi, v4si) -VAR3 (TERNOP_UNONE_UNONE_NONE_UNONE, vminavq_p_s, v16qi, v8hi, v4si) -VAR3 (TERNOP_UNONE_UNONE_NONE_UNONE, vminaq_m_s, v16qi, v8hi, v4si) -VAR3 (TERNOP_UNONE_UNONE_NONE_UNONE, vmaxavq_p_s, v16qi, v8hi, v4si) -VAR3 (TERNOP_UNONE_UNONE_NONE_UNONE, vmaxaq_m_s, v16qi, v8hi, v4si) +VAR3 (TERNOP_UNONE_UNONE_NONE_PRED, vshlq_m_r_u, v16qi, v8hi, v4si) +VAR3 (TERNOP_UNONE_UNONE_NONE_PRED, vrshlq_m_n_u, v16qi, v8hi, v4si) +VAR3 (TERNOP_UNONE_UNONE_NONE_PRED, vqshlq_m_r_u, v16qi, v8hi, v4si) +VAR3 (TERNOP_UNONE_UNONE_NONE_PRED, vqrshlq_m_n_u, v16qi, v8hi, v4si) +VAR3 (TERNOP_UNONE_UNONE_NONE_PRED, vminavq_p_s, v16qi, v8hi, v4si) +VAR3 (TERNOP_UNONE_UNONE_NONE_PRED, vminaq_m_s, v16qi, v8hi, v4si) +VAR3 (TERNOP_UNONE_UNONE_NONE_PRED, vmaxavq_p_s, v16qi, v8hi, v4si) +VAR3 (TERNOP_UNONE_UNONE_NONE_PRED, vmaxaq_m_s, v16qi, v8hi, v4si) VAR3 (TERNOP_PRED_NONE_NONE_PRED, vcmpneq_m_s, v16qi, v8hi, v4si) VAR3 (TERNOP_PRED_NONE_NONE_PRED, vcmpneq_m_n_s, v16qi, v8hi, v4si) VAR3 (TERNOP_PRED_NONE_NONE_PRED, vcmpltq_m_s, v16qi, v8hi, v4si) @@ -338,26 +338,26 @@ VAR3 (TERNOP_PRED_NONE_NONE_PRED, vcmpgeq_m_s, v16qi, v8hi, v4si) VAR3 (TERNOP_PRED_NONE_NONE_PRED, vcmpgeq_m_n_s, v16qi, v8hi, v4si) VAR3 (TERNOP_PRED_NONE_NONE_PRED, vcmpeqq_m_s, v16qi, v8hi, v4si) VAR3 (TERNOP_PRED_NONE_NONE_PRED, vcmpeqq_m_n_s, v16qi, v8hi, v4si) -VAR3 (TERNOP_NONE_NONE_NONE_UNONE, vshlq_m_r_s, v16qi, v8hi, v4si) -VAR3 (TERNOP_NONE_NONE_NONE_UNONE, vrshlq_m_n_s, v16qi, v8hi, v4si) -VAR3 (TERNOP_NONE_NONE_NONE_UNONE, vrev64q_m_s, v16qi, v8hi, v4si) -VAR3 (TERNOP_NONE_NONE_NONE_UNONE, vqshlq_m_r_s, v16qi, v8hi, v4si) -VAR3 (TERNOP_NONE_NONE_NONE_UNONE, vqrshlq_m_n_s, v16qi, v8hi, v4si) -VAR3 (TERNOP_NONE_NONE_NONE_UNONE, vqnegq_m_s, v16qi, v8hi, v4si) -VAR3 (TERNOP_NONE_NONE_NONE_UNONE, vqabsq_m_s, v16qi, v8hi, v4si) -VAR3 (TERNOP_NONE_NONE_NONE_UNONE, vnegq_m_s, v16qi, v8hi, v4si) -VAR3 (TERNOP_NONE_NONE_NONE_UNONE, vmvnq_m_s, v16qi, v8hi, v4si) -VAR3 (TERNOP_NONE_NONE_NONE_UNONE, vmlsdavxq_p_s, v16qi, v8hi, v4si) -VAR3 (TERNOP_NONE_NONE_NONE_UNONE, vmlsdavq_p_s, v16qi, v8hi, v4si) -VAR3 (TERNOP_NONE_NONE_NONE_UNONE, vmladavxq_p_s, v16qi, v8hi, v4si) -VAR3 (TERNOP_NONE_NONE_NONE_UNONE, vmladavq_p_s, v16qi, v8hi, v4si) -VAR3 (TERNOP_NONE_NONE_NONE_UNONE, vminvq_p_s, v16qi, v8hi, v4si) -VAR3 (TERNOP_NONE_NONE_NONE_UNONE, vmaxvq_p_s, v16qi, v8hi, v4si) -VAR3 (TERNOP_NONE_NONE_NONE_UNONE, vdupq_m_n_s, v16qi, v8hi, v4si) -VAR3 (TERNOP_NONE_NONE_NONE_UNONE, vclzq_m_s, v16qi, v8hi, v4si) -VAR3 (TERNOP_NONE_NONE_NONE_UNONE, vclsq_m_s, v16qi, v8hi, v4si) -VAR3 (TERNOP_NONE_NONE_NONE_UNONE, vaddvaq_p_s, v16qi, v8hi, v4si) -VAR3 (TERNOP_NONE_NONE_NONE_UNONE, vabsq_m_s, v16qi, v8hi, v4si) +VAR3 (TERNOP_NONE_NONE_NONE_PRED, vshlq_m_r_s, v16qi, v8hi, v4si) +VAR3 (TERNOP_NONE_NONE_NONE_PRED, vrshlq_m_n_s, v16qi, v8hi, v4si) +VAR3 (TERNOP_NONE_NONE_NONE_PRED, vrev64q_m_s, v16qi, v8hi, v4si) +VAR3 (TERNOP_NONE_NONE_NONE_PRED, vqshlq_m_r_s, v16qi, v8hi, v4si) +VAR3 (TERNOP_NONE_NONE_NONE_PRED, vqrshlq_m_n_s, v16qi, v8hi, v4si) +VAR3 (TERNOP_NONE_NONE_NONE_PRED, vqnegq_m_s, v16qi, v8hi, v4si) +VAR3 (TERNOP_NONE_NONE_NONE_PRED, vqabsq_m_s, v16qi, v8hi, v4si) +VAR3 (TERNOP_NONE_NONE_NONE_PRED, vnegq_m_s, v16qi, v8hi, v4si) +VAR3 (TERNOP_NONE_NONE_NONE_PRED, vmvnq_m_s, v16qi, v8hi, v4si) +VAR3 (TERNOP_NONE_NONE_NONE_PRED, vmlsdavxq_p_s, v16qi, v8hi, v4si) +VAR3 (TERNOP_NONE_NONE_NONE_PRED, vmlsdavq_p_s, v16qi, v8hi, v4si) +VAR3 (TERNOP_NONE_NONE_NONE_PRED, vmladavxq_p_s, v16qi, v8hi, v4si) +VAR3 (TERNOP_NONE_NONE_NONE_PRED, vmladavq_p_s, v16qi, v8hi, v4si) +VAR3 (TERNOP_NONE_NONE_NONE_PRED, vminvq_p_s, v16qi, v8hi, v4si) +VAR3 (TERNOP_NONE_NONE_NONE_PRED, vmaxvq_p_s, v16qi, v8hi, v4si) +VAR3 (TERNOP_NONE_NONE_NONE_PRED, vdupq_m_n_s, v16qi, v8hi, v4si) +VAR3 (TERNOP_NONE_NONE_NONE_PRED, vclzq_m_s, v16qi, v8hi, v4si) +VAR3 (TERNOP_NONE_NONE_NONE_PRED, vclsq_m_s, v16qi, v8hi, v4si) +VAR3 (TERNOP_NONE_NONE_NONE_PRED, vaddvaq_p_s, v16qi, v8hi, v4si) +VAR3 (TERNOP_NONE_NONE_NONE_PRED, vabsq_m_s, v16qi, v8hi, v4si) VAR3 (TERNOP_NONE_NONE_NONE_NONE, vqrdmlsdhxq_s, v16qi, v8hi, v4si) VAR3 (TERNOP_NONE_NONE_NONE_NONE, vqrdmlsdhq_s, v16qi, v8hi, v4si) VAR3 (TERNOP_NONE_NONE_NONE_NONE, vqrdmlashq_n_s, v16qi, v8hi, v4si) @@ -378,14 +378,14 @@ VAR3 (TERNOP_NONE_NONE_NONE_NONE, vmladavaxq_s, v16qi, v8hi, v4si) VAR3 (TERNOP_NONE_NONE_NONE_NONE, vmladavaq_s, v16qi, v8hi, v4si) VAR3 (TERNOP_NONE_NONE_NONE_IMM, vsriq_n_s, v16qi, v8hi, v4si) VAR3 (TERNOP_NONE_NONE_NONE_IMM, vsliq_n_s, v16qi, v8hi, v4si) -VAR2 (TERNOP_UNONE_UNONE_UNONE_UNONE, vrev32q_m_u, v16qi, v8hi) -VAR2 (TERNOP_UNONE_UNONE_UNONE_UNONE, vqmovntq_m_u, v8hi, v4si) -VAR2 (TERNOP_UNONE_UNONE_UNONE_UNONE, vqmovnbq_m_u, v8hi, v4si) -VAR2 (TERNOP_UNONE_UNONE_UNONE_UNONE, vmovntq_m_u, v8hi, v4si) -VAR2 (TERNOP_UNONE_UNONE_UNONE_UNONE, vmovnbq_m_u, v8hi, v4si) -VAR2 (TERNOP_UNONE_UNONE_UNONE_UNONE, vmovltq_m_u, v16qi, v8hi) -VAR2 (TERNOP_UNONE_UNONE_UNONE_UNONE, vmovlbq_m_u, v16qi, v8hi) -VAR2 (TERNOP_UNONE_UNONE_UNONE_UNONE, vmlaldavq_p_u, v8hi, v4si) +VAR2 (TERNOP_UNONE_UNONE_UNONE_PRED, vrev32q_m_u, v16qi, v8hi) +VAR2 (TERNOP_UNONE_UNONE_UNONE_PRED, vqmovntq_m_u, v8hi, v4si) +VAR2 (TERNOP_UNONE_UNONE_UNONE_PRED, vqmovnbq_m_u, v8hi, v4si) +VAR2 (TERNOP_UNONE_UNONE_UNONE_PRED, vmovntq_m_u, v8hi, v4si) +VAR2 (TERNOP_UNONE_UNONE_UNONE_PRED, vmovnbq_m_u, v8hi, v4si) +VAR2 (TERNOP_UNONE_UNONE_UNONE_PRED, vmovltq_m_u, v16qi, v8hi) +VAR2 (TERNOP_UNONE_UNONE_UNONE_PRED, vmovlbq_m_u, v16qi, v8hi) +VAR2 (TERNOP_UNONE_UNONE_UNONE_PRED, vmlaldavq_p_u, v8hi, v4si) VAR2 (TERNOP_UNONE_UNONE_UNONE_UNONE, vmlaldavaq_u, v8hi, v4si) VAR2 (TERNOP_UNONE_UNONE_UNONE_IMM, vshrntq_n_u, v8hi, v4si) VAR2 (TERNOP_UNONE_UNONE_UNONE_IMM, vshrnbq_n_u, v8hi, v4si) @@ -394,17 +394,17 @@ VAR2 (TERNOP_UNONE_UNONE_UNONE_IMM, vrshrnbq_n_u, v8hi, v4si) VAR2 (TERNOP_UNONE_UNONE_UNONE_IMM, vqshrntq_n_u, v8hi, v4si) VAR2 (TERNOP_UNONE_UNONE_UNONE_IMM, vqshrnbq_n_u, v8hi, v4si) VAR2 (TERNOP_UNONE_UNONE_UNONE_IMM, vqrshrntq_n_u, v8hi, v4si) -VAR2 (TERNOP_UNONE_UNONE_NONE_UNONE, vqmovuntq_m_s, v8hi, v4si) -VAR2 (TERNOP_UNONE_UNONE_NONE_UNONE, vqmovunbq_m_s, v8hi, v4si) -VAR2 (TERNOP_UNONE_UNONE_NONE_UNONE, vcvtq_m_from_f_u, v8hi, v4si) -VAR2 (TERNOP_UNONE_UNONE_NONE_UNONE, vcvtpq_m_u, v8hi, v4si) -VAR2 (TERNOP_UNONE_UNONE_NONE_UNONE, vcvtnq_m_u, v8hi, v4si) -VAR2 (TERNOP_UNONE_UNONE_NONE_UNONE, vcvtmq_m_u, v8hi, v4si) +VAR2 (TERNOP_UNONE_UNONE_NONE_PRED, vqmovuntq_m_s, v8hi, v4si) +VAR2 (TERNOP_UNONE_UNONE_NONE_PRED, vqmovunbq_m_s, v8hi, v4si) +VAR2 (TERNOP_UNONE_UNONE_NONE_PRED, vcvtq_m_from_f_u, v8hi, v4si) +VAR2 (TERNOP_UNONE_UNONE_NONE_PRED, vcvtpq_m_u, v8hi, v4si) +VAR2 (TERNOP_UNONE_UNONE_NONE_PRED, vcvtnq_m_u, v8hi, v4si) +VAR2 (TERNOP_UNONE_UNONE_NONE_PRED, vcvtmq_m_u, v8hi, v4si) VAR2 (TERNOP_UNONE_UNONE_NONE_IMM, vqshruntq_n_s, v8hi, v4si) VAR2 (TERNOP_UNONE_UNONE_NONE_IMM, vqshrunbq_n_s, v8hi, v4si) VAR2 (TERNOP_UNONE_UNONE_NONE_IMM, vqrshruntq_n_s, v8hi, v4si) -VAR2 (TERNOP_UNONE_UNONE_IMM_UNONE, vorrq_m_n_u, v8hi, v4si) -VAR2 (TERNOP_UNONE_UNONE_IMM_UNONE, vmvnq_m_n_u, v8hi, v4si) +VAR2 (TERNOP_UNONE_UNONE_IMM_PRED, vorrq_m_n_u, v8hi, v4si) +VAR2 (TERNOP_UNONE_UNONE_IMM_PRED, vmvnq_m_n_u, v8hi, v4si) VAR2 (TERNOP_PRED_NONE_NONE_PRED, vcmpneq_m_n_f, v8hf, v4sf) VAR2 (TERNOP_PRED_NONE_NONE_PRED, vcmpneq_m_f, v8hf, v4sf) VAR2 (TERNOP_PRED_NONE_NONE_PRED, vcmpltq_m_n_f, v8hf, v4sf) @@ -416,38 +416,38 @@ VAR2 (TERNOP_PRED_NONE_NONE_PRED, vcmpgtq_m_f, v8hf, v4sf) VAR2 (TERNOP_PRED_NONE_NONE_PRED, vcmpgeq_m_n_f, v8hf, v4sf) VAR2 (TERNOP_PRED_NONE_NONE_PRED, vcmpgeq_m_f, v8hf, v4sf) VAR2 (TERNOP_PRED_NONE_NONE_PRED, vcmpeqq_m_n_f, v8hf, v4sf) -VAR2 (TERNOP_NONE_NONE_NONE_UNONE, vrndxq_m_f, v8hf, v4sf) -VAR2 (TERNOP_NONE_NONE_NONE_UNONE, vrndq_m_f, v8hf, v4sf) -VAR2 (TERNOP_NONE_NONE_NONE_UNONE, vrndpq_m_f, v8hf, v4sf) -VAR2 (TERNOP_NONE_NONE_NONE_UNONE, vrndnq_m_f, v8hf, v4sf) -VAR2 (TERNOP_NONE_NONE_NONE_UNONE, vrndmq_m_f, v8hf, v4sf) -VAR2 (TERNOP_NONE_NONE_NONE_UNONE, vrndaq_m_f, v8hf, v4sf) -VAR2 (TERNOP_NONE_NONE_NONE_UNONE, vrev64q_m_f, v8hf, v4sf) -VAR2 (TERNOP_NONE_NONE_NONE_UNONE, vrev32q_m_s, v16qi, v8hi) -VAR2 (TERNOP_NONE_NONE_NONE_UNONE, vqmovntq_m_s, v8hi, v4si) -VAR2 (TERNOP_NONE_NONE_NONE_UNONE, vqmovnbq_m_s, v8hi, v4si) +VAR2 (TERNOP_NONE_NONE_NONE_PRED, vrndxq_m_f, v8hf, v4sf) +VAR2 (TERNOP_NONE_NONE_NONE_PRED, vrndq_m_f, v8hf, v4sf) +VAR2 (TERNOP_NONE_NONE_NONE_PRED, vrndpq_m_f, v8hf, v4sf) +VAR2 (TERNOP_NONE_NONE_NONE_PRED, vrndnq_m_f, v8hf, v4sf) +VAR2 (TERNOP_NONE_NONE_NONE_PRED, vrndmq_m_f, v8hf, v4sf) +VAR2 (TERNOP_NONE_NONE_NONE_PRED, vrndaq_m_f, v8hf, v4sf) +VAR2 (TERNOP_NONE_NONE_NONE_PRED, vrev64q_m_f, v8hf, v4sf) +VAR2 (TERNOP_NONE_NONE_NONE_PRED, vrev32q_m_s, v16qi, v8hi) +VAR2 (TERNOP_NONE_NONE_NONE_PRED, vqmovntq_m_s, v8hi, v4si) +VAR2 (TERNOP_NONE_NONE_NONE_PRED, vqmovnbq_m_s, v8hi, v4si) VAR2 (TERNOP_NONE_NONE_NONE_PRED, vpselq_f, v8hf, v4sf) -VAR2 (TERNOP_NONE_NONE_NONE_UNONE, vnegq_m_f, v8hf, v4sf) -VAR2 (TERNOP_NONE_NONE_NONE_UNONE, vmovntq_m_s, v8hi, v4si) -VAR2 (TERNOP_NONE_NONE_NONE_UNONE, vmovnbq_m_s, v8hi, v4si) -VAR2 (TERNOP_NONE_NONE_NONE_UNONE, vmovltq_m_s, v16qi, v8hi) -VAR2 (TERNOP_NONE_NONE_NONE_UNONE, vmovlbq_m_s, v16qi, v8hi) -VAR2 (TERNOP_NONE_NONE_NONE_UNONE, vmlsldavxq_p_s, v8hi, v4si) -VAR2 (TERNOP_NONE_NONE_NONE_UNONE, vmlsldavq_p_s, v8hi, v4si) -VAR2 (TERNOP_NONE_NONE_NONE_UNONE, vmlaldavxq_p_s, v8hi, v4si) -VAR2 (TERNOP_NONE_NONE_NONE_UNONE, vmlaldavq_p_s, v8hi, v4si) -VAR2 (TERNOP_NONE_NONE_NONE_UNONE, vminnmvq_p_f, v8hf, v4sf) -VAR2 (TERNOP_NONE_NONE_NONE_UNONE, vminnmavq_p_f, v8hf, v4sf) -VAR2 (TERNOP_NONE_NONE_NONE_UNONE, vminnmaq_m_f, v8hf, v4sf) -VAR2 (TERNOP_NONE_NONE_NONE_UNONE, vmaxnmvq_p_f, v8hf, v4sf) -VAR2 (TERNOP_NONE_NONE_NONE_UNONE, vmaxnmavq_p_f, v8hf, v4sf) -VAR2 (TERNOP_NONE_NONE_NONE_UNONE, vmaxnmaq_m_f, v8hf, v4sf) -VAR2 (TERNOP_NONE_NONE_NONE_UNONE, vdupq_m_n_f, v8hf, v4sf) -VAR2 (TERNOP_NONE_NONE_NONE_UNONE, vcvtq_m_from_f_s, v8hi, v4si) -VAR2 (TERNOP_NONE_NONE_NONE_UNONE, vcvtpq_m_s, v8hi, v4si) -VAR2 (TERNOP_NONE_NONE_NONE_UNONE, vcvtnq_m_s, v8hi, v4si) -VAR2 (TERNOP_NONE_NONE_NONE_UNONE, vcvtmq_m_s, v8hi, v4si) -VAR2 (TERNOP_NONE_NONE_NONE_UNONE, vabsq_m_f, v8hf, v4sf) +VAR2 (TERNOP_NONE_NONE_NONE_PRED, vnegq_m_f, v8hf, v4sf) +VAR2 (TERNOP_NONE_NONE_NONE_PRED, vmovntq_m_s, v8hi, v4si) +VAR2 (TERNOP_NONE_NONE_NONE_PRED, vmovnbq_m_s, v8hi, v4si) +VAR2 (TERNOP_NONE_NONE_NONE_PRED, vmovltq_m_s, v16qi, v8hi) +VAR2 (TERNOP_NONE_NONE_NONE_PRED, vmovlbq_m_s, v16qi, v8hi) +VAR2 (TERNOP_NONE_NONE_NONE_PRED, vmlsldavxq_p_s, v8hi, v4si) +VAR2 (TERNOP_NONE_NONE_NONE_PRED, vmlsldavq_p_s, v8hi, v4si) +VAR2 (TERNOP_NONE_NONE_NONE_PRED, vmlaldavxq_p_s, v8hi, v4si) +VAR2 (TERNOP_NONE_NONE_NONE_PRED, vmlaldavq_p_s, v8hi, v4si) +VAR2 (TERNOP_NONE_NONE_NONE_PRED, vminnmvq_p_f, v8hf, v4sf) +VAR2 (TERNOP_NONE_NONE_NONE_PRED, vminnmavq_p_f, v8hf, v4sf) +VAR2 (TERNOP_NONE_NONE_NONE_PRED, vminnmaq_m_f, v8hf, v4sf) +VAR2 (TERNOP_NONE_NONE_NONE_PRED, vmaxnmvq_p_f, v8hf, v4sf) +VAR2 (TERNOP_NONE_NONE_NONE_PRED, vmaxnmavq_p_f, v8hf, v4sf) +VAR2 (TERNOP_NONE_NONE_NONE_PRED, vmaxnmaq_m_f, v8hf, v4sf) +VAR2 (TERNOP_NONE_NONE_NONE_PRED, vdupq_m_n_f, v8hf, v4sf) +VAR2 (TERNOP_NONE_NONE_NONE_PRED, vcvtq_m_from_f_s, v8hi, v4si) +VAR2 (TERNOP_NONE_NONE_NONE_PRED, vcvtpq_m_s, v8hi, v4si) +VAR2 (TERNOP_NONE_NONE_NONE_PRED, vcvtnq_m_s, v8hi, v4si) +VAR2 (TERNOP_NONE_NONE_NONE_PRED, vcvtmq_m_s, v8hi, v4si) +VAR2 (TERNOP_NONE_NONE_NONE_PRED, vabsq_m_f, v8hf, v4sf) VAR2 (TERNOP_NONE_NONE_NONE_NONE, vmlsldavaxq_s, v8hi, v4si) VAR2 (TERNOP_NONE_NONE_NONE_NONE, vmlsldavaq_s, v8hi, v4si) VAR2 (TERNOP_NONE_NONE_NONE_NONE, vmlaldavaxq_s, v8hi, v4si) @@ -463,8 +463,8 @@ VAR2 (TERNOP_NONE_NONE_NONE_IMM, vrshrnbq_n_s, v8hi, v4si) VAR2 (TERNOP_NONE_NONE_NONE_IMM, vqshrntq_n_s, v8hi, v4si) VAR2 (TERNOP_NONE_NONE_NONE_IMM, vqshrnbq_n_s, v8hi, v4si) VAR2 (TERNOP_NONE_NONE_NONE_IMM, vqrshrntq_n_s, v8hi, v4si) -VAR2 (TERNOP_NONE_NONE_IMM_UNONE, vorrq_m_n_s, v8hi, v4si) -VAR2 (TERNOP_NONE_NONE_IMM_UNONE, vmvnq_m_n_s, v8hi, v4si) +VAR2 (TERNOP_NONE_NONE_IMM_PRED, vorrq_m_n_s, v8hi, v4si) +VAR2 (TERNOP_NONE_NONE_IMM_PRED, vmvnq_m_n_s, v8hi, v4si) VAR1 (TERNOP_UNONE_UNONE_UNONE_UNONE, vrmlaldavhq_p_u, v4si) VAR1 (TERNOP_UNONE_UNONE_UNONE_UNONE, vrev16q_m_u, v16qi) VAR1 (TERNOP_UNONE_UNONE_UNONE_UNONE, vaddlvaq_p_u, v4si) @@ -482,189 +482,189 @@ VAR1 (TERNOP_NONE_NONE_NONE_UNONE, vaddlvaq_p_s, v4si) VAR1 (TERNOP_NONE_NONE_NONE_NONE, vrmlsldavhaxq_s, v4si) VAR1 (TERNOP_NONE_NONE_NONE_NONE, vrmlsldavhaq_s, v4si) VAR1 (TERNOP_NONE_NONE_NONE_NONE, vrmlaldavhaxq_s, v4si) -VAR3 (QUADOP_NONE_NONE_NONE_IMM_UNONE, vsriq_m_n_s, v16qi, v8hi, v4si) -VAR3 (QUADOP_UNONE_UNONE_UNONE_IMM_UNONE, vsriq_m_n_u, v16qi, v8hi, v4si) -VAR3 (QUADOP_NONE_NONE_NONE_NONE_UNONE, vsubq_m_s, v16qi, v8hi, v4si) -VAR3 (QUADOP_UNONE_UNONE_UNONE_UNONE_UNONE, vsubq_m_u, v16qi, v8hi, v4si) -VAR2 (QUADOP_NONE_NONE_UNONE_IMM_UNONE, vcvtq_m_n_to_f_u, v8hf, v4sf) -VAR2 (QUADOP_NONE_NONE_NONE_IMM_UNONE, vcvtq_m_n_to_f_s, v8hf, v4sf) -VAR3 (QUADOP_UNONE_UNONE_NONE_IMM_UNONE, vqshluq_m_n_s, v16qi, v8hi, v4si) -VAR3 (QUADOP_UNONE_UNONE_NONE_NONE_UNONE, vabavq_p_s, v16qi, v8hi, v4si) -VAR3 (QUADOP_UNONE_UNONE_UNONE_UNONE_UNONE, vabavq_p_u, v16qi, v8hi, v4si) -VAR3 (QUADOP_UNONE_UNONE_UNONE_NONE_UNONE, vshlq_m_u, v16qi, v8hi, v4si) -VAR3 (QUADOP_NONE_NONE_NONE_NONE_UNONE, vshlq_m_s, v16qi, v8hi, v4si) -VAR3 (QUADOP_UNONE_UNONE_UNONE_UNONE_UNONE, vsubq_m_n_u, v16qi, v8hi, v4si) -VAR3 (QUADOP_UNONE_UNONE_UNONE_UNONE_UNONE, vrmulhq_m_u, v16qi, v8hi, v4si) -VAR3 (QUADOP_UNONE_UNONE_UNONE_UNONE_UNONE, vrhaddq_m_u, v16qi, v8hi, v4si) -VAR3 (QUADOP_UNONE_UNONE_UNONE_UNONE_UNONE, vqsubq_m_u, v16qi, v8hi, v4si) -VAR3 (QUADOP_UNONE_UNONE_UNONE_UNONE_UNONE, vqsubq_m_n_u, v16qi, v8hi, v4si) -VAR3 (QUADOP_UNONE_UNONE_UNONE_UNONE_UNONE, vqaddq_m_u, v16qi, v8hi, v4si) -VAR3 (QUADOP_UNONE_UNONE_UNONE_UNONE_UNONE, vqaddq_m_n_u, v16qi, v8hi, v4si) -VAR3 (QUADOP_UNONE_UNONE_UNONE_UNONE_UNONE, vorrq_m_u, v16qi, v8hi, v4si) -VAR3 (QUADOP_UNONE_UNONE_UNONE_UNONE_UNONE, vornq_m_u, v16qi, v8hi, v4si) -VAR3 (QUADOP_UNONE_UNONE_UNONE_UNONE_UNONE, vmulq_m_u, v16qi, v8hi, v4si) -VAR3 (QUADOP_UNONE_UNONE_UNONE_UNONE_UNONE, vmulq_m_n_u, v16qi, v8hi, v4si) -VAR3 (QUADOP_UNONE_UNONE_UNONE_UNONE_UNONE, vmulltq_int_m_u, v16qi, v8hi, v4si) -VAR3 (QUADOP_UNONE_UNONE_UNONE_UNONE_UNONE, vmullbq_int_m_u, v16qi, v8hi, v4si) -VAR3 (QUADOP_UNONE_UNONE_UNONE_UNONE_UNONE, vmulhq_m_u, v16qi, v8hi, v4si) -VAR3 (QUADOP_UNONE_UNONE_UNONE_UNONE_UNONE, vmlasq_m_n_u, v16qi, v8hi, v4si) -VAR3 (QUADOP_UNONE_UNONE_UNONE_UNONE_UNONE, vmlaq_m_n_u, v16qi, v8hi, v4si) -VAR3 (QUADOP_UNONE_UNONE_UNONE_UNONE_UNONE, vmladavaq_p_u, v16qi, v8hi, v4si) -VAR3 (QUADOP_UNONE_UNONE_UNONE_UNONE_UNONE, vminq_m_u, v16qi, v8hi, v4si) -VAR3 (QUADOP_UNONE_UNONE_UNONE_UNONE_UNONE, vmaxq_m_u, v16qi, v8hi, v4si) -VAR3 (QUADOP_UNONE_UNONE_UNONE_UNONE_UNONE, vhsubq_m_u, v16qi, v8hi, v4si) -VAR3 (QUADOP_UNONE_UNONE_UNONE_UNONE_UNONE, vhsubq_m_n_u, v16qi, v8hi, v4si) -VAR3 (QUADOP_UNONE_UNONE_UNONE_UNONE_UNONE, vhaddq_m_u, v16qi, v8hi, v4si) -VAR3 (QUADOP_UNONE_UNONE_UNONE_UNONE_UNONE, vhaddq_m_n_u, v16qi, v8hi, v4si) -VAR3 (QUADOP_UNONE_UNONE_UNONE_UNONE_UNONE, veorq_m_u, v16qi, v8hi, v4si) -VAR3 (QUADOP_UNONE_UNONE_UNONE_UNONE_UNONE, vcaddq_rot90_m_u, v16qi, v8hi, v4si) -VAR3 (QUADOP_UNONE_UNONE_UNONE_UNONE_UNONE, vcaddq_rot270_m_u, v16qi, v8hi, v4si) -VAR3 (QUADOP_UNONE_UNONE_UNONE_UNONE_UNONE, vbicq_m_u, v16qi, v8hi, v4si) -VAR3 (QUADOP_UNONE_UNONE_UNONE_UNONE_UNONE, vandq_m_u, v16qi, v8hi, v4si) -VAR3 (QUADOP_UNONE_UNONE_UNONE_UNONE_UNONE, vaddq_m_u, v16qi, v8hi, v4si) -VAR3 (QUADOP_UNONE_UNONE_UNONE_UNONE_UNONE, vaddq_m_n_u, v16qi, v8hi, v4si) -VAR3 (QUADOP_UNONE_UNONE_UNONE_UNONE_UNONE, vabdq_m_u, v16qi, v8hi, v4si) -VAR3 (QUADOP_UNONE_UNONE_UNONE_NONE_UNONE, vrshlq_m_u, v16qi, v8hi, v4si) -VAR3 (QUADOP_UNONE_UNONE_UNONE_NONE_UNONE, vqshlq_m_u, v16qi, v8hi, v4si) -VAR3 (QUADOP_UNONE_UNONE_UNONE_NONE_UNONE, vqrshlq_m_u, v16qi, v8hi, v4si) -VAR3 (QUADOP_UNONE_UNONE_UNONE_NONE_UNONE, vbrsrq_m_n_u, v16qi, v8hi, v4si) -VAR3 (QUADOP_UNONE_UNONE_UNONE_IMM_UNONE, vsliq_m_n_u, v16qi, v8hi, v4si) -VAR3 (QUADOP_UNONE_UNONE_UNONE_IMM_UNONE, vshrq_m_n_u, v16qi, v8hi, v4si) -VAR3 (QUADOP_UNONE_UNONE_UNONE_IMM_UNONE, vshlq_m_n_u, v16qi, v8hi, v4si) -VAR3 (QUADOP_UNONE_UNONE_UNONE_IMM_UNONE, vrshrq_m_n_u, v16qi, v8hi, v4si) -VAR3 (QUADOP_UNONE_UNONE_UNONE_IMM_UNONE, vqshlq_m_n_u, v16qi, v8hi, v4si) -VAR3 (QUADOP_NONE_NONE_NONE_NONE_UNONE, vsubq_m_n_s, v16qi, v8hi, v4si) -VAR3 (QUADOP_NONE_NONE_NONE_NONE_UNONE, vrshlq_m_s, v16qi, v8hi, v4si) -VAR3 (QUADOP_NONE_NONE_NONE_NONE_UNONE, vrmulhq_m_s, v16qi, v8hi, v4si) -VAR3 (QUADOP_NONE_NONE_NONE_NONE_UNONE, vrhaddq_m_s, v16qi, v8hi, v4si) -VAR3 (QUADOP_NONE_NONE_NONE_NONE_UNONE, vqsubq_m_s, v16qi, v8hi, v4si) -VAR3 (QUADOP_NONE_NONE_NONE_NONE_UNONE, vqsubq_m_n_s, v16qi, v8hi, v4si) -VAR3 (QUADOP_NONE_NONE_NONE_NONE_UNONE, vqshlq_m_s, v16qi, v8hi, v4si) -VAR3 (QUADOP_NONE_NONE_NONE_NONE_UNONE, vqrshlq_m_s, v16qi, v8hi, v4si) -VAR3 (QUADOP_NONE_NONE_NONE_NONE_UNONE, vqrdmulhq_m_s, v16qi, v8hi, v4si) -VAR3 (QUADOP_NONE_NONE_NONE_NONE_UNONE, vqrdmulhq_m_n_s, v16qi, v8hi, v4si) -VAR3 (QUADOP_NONE_NONE_NONE_NONE_UNONE, vqrdmlsdhxq_m_s, v16qi, v8hi, v4si) -VAR3 (QUADOP_NONE_NONE_NONE_NONE_UNONE, vqrdmlsdhq_m_s, v16qi, v8hi, v4si) -VAR3 (QUADOP_NONE_NONE_NONE_NONE_UNONE, vqrdmlashq_m_n_s, v16qi, v8hi, v4si) -VAR3 (QUADOP_NONE_NONE_NONE_NONE_UNONE, vqrdmlahq_m_n_s, v16qi, v8hi, v4si) -VAR3 (QUADOP_NONE_NONE_NONE_NONE_UNONE, vqrdmladhxq_m_s, v16qi, v8hi, v4si) -VAR3 (QUADOP_NONE_NONE_NONE_NONE_UNONE, vqrdmladhq_m_s, v16qi, v8hi, v4si) -VAR3 (QUADOP_NONE_NONE_NONE_NONE_UNONE, vqdmulhq_m_s, v16qi, v8hi, v4si) -VAR3 (QUADOP_NONE_NONE_NONE_NONE_UNONE, vqdmulhq_m_n_s, v16qi, v8hi, v4si) -VAR3 (QUADOP_NONE_NONE_NONE_NONE_UNONE, vqdmlsdhxq_m_s, v16qi, v8hi, v4si) -VAR3 (QUADOP_NONE_NONE_NONE_NONE_UNONE, vqdmlsdhq_m_s, v16qi, v8hi, v4si) -VAR3 (QUADOP_NONE_NONE_NONE_NONE_UNONE, vqdmlahq_m_n_s, v16qi, v8hi, v4si) -VAR3 (QUADOP_NONE_NONE_NONE_NONE_UNONE, vqdmlashq_m_n_s, v16qi, v8hi, v4si) -VAR3 (QUADOP_NONE_NONE_NONE_NONE_UNONE, vqdmladhxq_m_s, v16qi, v8hi, v4si) -VAR3 (QUADOP_NONE_NONE_NONE_NONE_UNONE, vqdmladhq_m_s, v16qi, v8hi, v4si) -VAR3 (QUADOP_NONE_NONE_NONE_NONE_UNONE, vqaddq_m_s, v16qi, v8hi, v4si) -VAR3 (QUADOP_NONE_NONE_NONE_NONE_UNONE, vqaddq_m_n_s, v16qi, v8hi, v4si) -VAR3 (QUADOP_NONE_NONE_NONE_NONE_UNONE, vorrq_m_s, v16qi, v8hi, v4si) -VAR3 (QUADOP_NONE_NONE_NONE_NONE_UNONE, vornq_m_s, v16qi, v8hi, v4si) -VAR3 (QUADOP_NONE_NONE_NONE_NONE_UNONE, vmulq_m_s, v16qi, v8hi, v4si) -VAR3 (QUADOP_NONE_NONE_NONE_NONE_UNONE, vmulq_m_n_s, v16qi, v8hi, v4si) -VAR3 (QUADOP_NONE_NONE_NONE_NONE_UNONE, vmulltq_int_m_s, v16qi, v8hi, v4si) -VAR3 (QUADOP_NONE_NONE_NONE_NONE_UNONE, vmullbq_int_m_s, v16qi, v8hi, v4si) -VAR3 (QUADOP_NONE_NONE_NONE_NONE_UNONE, vmulhq_m_s, v16qi, v8hi, v4si) -VAR3 (QUADOP_NONE_NONE_NONE_NONE_UNONE, vmlsdavaxq_p_s, v16qi, v8hi, v4si) -VAR3 (QUADOP_NONE_NONE_NONE_NONE_UNONE, vmlsdavaq_p_s, v16qi, v8hi, v4si) -VAR3 (QUADOP_NONE_NONE_NONE_NONE_UNONE, vmlasq_m_n_s, v16qi, v8hi, v4si) -VAR3 (QUADOP_NONE_NONE_NONE_NONE_UNONE, vmlaq_m_n_s, v16qi, v8hi, v4si) -VAR3 (QUADOP_NONE_NONE_NONE_NONE_UNONE, vmladavaxq_p_s, v16qi, v8hi, v4si) -VAR3 (QUADOP_NONE_NONE_NONE_NONE_UNONE, vmladavaq_p_s, v16qi, v8hi, v4si) -VAR3 (QUADOP_NONE_NONE_NONE_NONE_UNONE, vminq_m_s, v16qi, v8hi, v4si) -VAR3 (QUADOP_NONE_NONE_NONE_NONE_UNONE, vmaxq_m_s, v16qi, v8hi, v4si) -VAR3 (QUADOP_NONE_NONE_NONE_NONE_UNONE, vhsubq_m_s, v16qi, v8hi, v4si) -VAR3 (QUADOP_NONE_NONE_NONE_NONE_UNONE, vhsubq_m_n_s, v16qi, v8hi, v4si) -VAR3 (QUADOP_NONE_NONE_NONE_NONE_UNONE, vhcaddq_rot90_m_s, v16qi, v8hi, v4si) -VAR3 (QUADOP_NONE_NONE_NONE_NONE_UNONE, vhcaddq_rot270_m_s, v16qi, v8hi, v4si) -VAR3 (QUADOP_NONE_NONE_NONE_NONE_UNONE, vhaddq_m_s, v16qi, v8hi, v4si) -VAR3 (QUADOP_NONE_NONE_NONE_NONE_UNONE, vhaddq_m_n_s, v16qi, v8hi, v4si) -VAR3 (QUADOP_NONE_NONE_NONE_NONE_UNONE, veorq_m_s, v16qi, v8hi, v4si) -VAR3 (QUADOP_NONE_NONE_NONE_NONE_UNONE, vcaddq_rot90_m_s, v16qi, v8hi, v4si) -VAR3 (QUADOP_NONE_NONE_NONE_NONE_UNONE, vcaddq_rot270_m_s, v16qi, v8hi, v4si) -VAR3 (QUADOP_NONE_NONE_NONE_NONE_UNONE, vbrsrq_m_n_s, v16qi, v8hi, v4si) -VAR3 (QUADOP_NONE_NONE_NONE_NONE_UNONE, vbicq_m_s, v16qi, v8hi, v4si) -VAR3 (QUADOP_NONE_NONE_NONE_NONE_UNONE, vandq_m_s, v16qi, v8hi, v4si) -VAR3 (QUADOP_NONE_NONE_NONE_NONE_UNONE, vaddq_m_s, v16qi, v8hi, v4si) -VAR3 (QUADOP_NONE_NONE_NONE_NONE_UNONE, vaddq_m_n_s, v16qi, v8hi, v4si) -VAR3 (QUADOP_NONE_NONE_NONE_NONE_UNONE, vabdq_m_s, v16qi, v8hi, v4si) -VAR3 (QUADOP_NONE_NONE_NONE_IMM_UNONE, vsliq_m_n_s, v16qi, v8hi, v4si) -VAR3 (QUADOP_NONE_NONE_NONE_IMM_UNONE, vshrq_m_n_s, v16qi, v8hi, v4si) -VAR3 (QUADOP_NONE_NONE_NONE_IMM_UNONE, vshlq_m_n_s, v16qi, v8hi, v4si) -VAR3 (QUADOP_NONE_NONE_NONE_IMM_UNONE, vrshrq_m_n_s, v16qi, v8hi, v4si) -VAR3 (QUADOP_NONE_NONE_NONE_IMM_UNONE, vqshlq_m_n_s, v16qi, v8hi, v4si) -VAR2 (QUADOP_UNONE_UNONE_UNONE_UNONE_UNONE, vmulltq_poly_m_p, v16qi, v8hi) -VAR2 (QUADOP_UNONE_UNONE_UNONE_UNONE_UNONE, vmullbq_poly_m_p, v16qi, v8hi) -VAR2 (QUADOP_UNONE_UNONE_UNONE_UNONE_UNONE, vmlaldavaq_p_u, v8hi, v4si) -VAR2 (QUADOP_UNONE_UNONE_UNONE_IMM_UNONE, vshrntq_m_n_u, v8hi, v4si) -VAR2 (QUADOP_UNONE_UNONE_UNONE_IMM_UNONE, vshrnbq_m_n_u, v8hi, v4si) -VAR2 (QUADOP_UNONE_UNONE_UNONE_IMM_UNONE, vshlltq_m_n_u, v16qi, v8hi) -VAR2 (QUADOP_UNONE_UNONE_UNONE_IMM_UNONE, vshllbq_m_n_u, v16qi, v8hi) -VAR2 (QUADOP_UNONE_UNONE_UNONE_IMM_UNONE, vrshrntq_m_n_u, v8hi, v4si) -VAR2 (QUADOP_UNONE_UNONE_UNONE_IMM_UNONE, vrshrnbq_m_n_u, v8hi, v4si) -VAR2 (QUADOP_UNONE_UNONE_UNONE_IMM_UNONE, vqshrntq_m_n_u, v8hi, v4si) -VAR2 (QUADOP_UNONE_UNONE_UNONE_IMM_UNONE, vqshrnbq_m_n_u, v8hi, v4si) -VAR2 (QUADOP_UNONE_UNONE_UNONE_IMM_UNONE, vqrshrntq_m_n_u, v8hi, v4si) -VAR2 (QUADOP_UNONE_UNONE_UNONE_IMM_UNONE, vqrshrnbq_m_n_u, v8hi, v4si) -VAR2 (QUADOP_UNONE_UNONE_NONE_IMM_UNONE, vqshruntq_m_n_s, v8hi, v4si) -VAR2 (QUADOP_UNONE_UNONE_NONE_IMM_UNONE, vqshrunbq_m_n_s, v8hi, v4si) -VAR2 (QUADOP_UNONE_UNONE_NONE_IMM_UNONE, vqrshruntq_m_n_s, v8hi, v4si) -VAR2 (QUADOP_UNONE_UNONE_NONE_IMM_UNONE, vqrshrunbq_m_n_s, v8hi, v4si) -VAR2 (QUADOP_NONE_NONE_NONE_NONE_UNONE, vqdmulltq_m_s, v8hi, v4si) -VAR2 (QUADOP_NONE_NONE_NONE_NONE_UNONE, vqdmulltq_m_n_s, v8hi, v4si) -VAR2 (QUADOP_NONE_NONE_NONE_NONE_UNONE, vqdmullbq_m_s, v8hi, v4si) -VAR2 (QUADOP_NONE_NONE_NONE_NONE_UNONE, vqdmullbq_m_n_s, v8hi, v4si) -VAR2 (QUADOP_NONE_NONE_NONE_NONE_UNONE, vmlsldavaxq_p_s, v8hi, v4si) -VAR2 (QUADOP_NONE_NONE_NONE_NONE_UNONE, vmlsldavaq_p_s, v8hi, v4si) -VAR2 (QUADOP_NONE_NONE_NONE_NONE_UNONE, vmlaldavaxq_p_s, v8hi, v4si) -VAR2 (QUADOP_NONE_NONE_NONE_NONE_UNONE, vmlaldavaq_p_s, v8hi, v4si) -VAR2 (QUADOP_NONE_NONE_NONE_IMM_UNONE, vshrntq_m_n_s, v8hi, v4si) -VAR2 (QUADOP_NONE_NONE_NONE_IMM_UNONE, vshrnbq_m_n_s, v8hi, v4si) -VAR2 (QUADOP_NONE_NONE_NONE_IMM_UNONE, vshlltq_m_n_s, v16qi, v8hi) -VAR2 (QUADOP_NONE_NONE_NONE_IMM_UNONE, vshllbq_m_n_s, v16qi, v8hi) -VAR2 (QUADOP_NONE_NONE_NONE_IMM_UNONE, vrshrntq_m_n_s, v8hi, v4si) -VAR2 (QUADOP_NONE_NONE_NONE_IMM_UNONE, vrshrnbq_m_n_s, v8hi, v4si) -VAR2 (QUADOP_NONE_NONE_NONE_IMM_UNONE, vqshrntq_m_n_s, v8hi, v4si) -VAR2 (QUADOP_NONE_NONE_NONE_IMM_UNONE, vqshrnbq_m_n_s, v8hi, v4si) -VAR2 (QUADOP_NONE_NONE_NONE_IMM_UNONE, vqrshrntq_m_n_s, v8hi, v4si) -VAR2 (QUADOP_NONE_NONE_NONE_IMM_UNONE, vqrshrnbq_m_n_s, v8hi, v4si) +VAR3 (QUADOP_NONE_NONE_NONE_IMM_PRED, vsriq_m_n_s, v16qi, v8hi, v4si) +VAR3 (QUADOP_UNONE_UNONE_UNONE_IMM_PRED, vsriq_m_n_u, v16qi, v8hi, v4si) +VAR3 (QUADOP_NONE_NONE_NONE_NONE_PRED, vsubq_m_s, v16qi, v8hi, v4si) +VAR3 (QUADOP_UNONE_UNONE_UNONE_UNONE_PRED, vsubq_m_u, v16qi, v8hi, v4si) +VAR2 (QUADOP_NONE_NONE_UNONE_IMM_PRED, vcvtq_m_n_to_f_u, v8hf, v4sf) +VAR2 (QUADOP_NONE_NONE_NONE_IMM_PRED, vcvtq_m_n_to_f_s, v8hf, v4sf) +VAR3 (QUADOP_UNONE_UNONE_NONE_IMM_PRED, vqshluq_m_n_s, v16qi, v8hi, v4si) +VAR3 (QUADOP_UNONE_UNONE_NONE_NONE_PRED, vabavq_p_s, v16qi, v8hi, v4si) +VAR3 (QUADOP_UNONE_UNONE_UNONE_UNONE_PRED, vabavq_p_u, v16qi, v8hi, v4si) +VAR3 (QUADOP_UNONE_UNONE_UNONE_NONE_PRED, vshlq_m_u, v16qi, v8hi, v4si) +VAR3 (QUADOP_NONE_NONE_NONE_NONE_PRED, vshlq_m_s, v16qi, v8hi, v4si) +VAR3 (QUADOP_UNONE_UNONE_UNONE_UNONE_PRED, vsubq_m_n_u, v16qi, v8hi, v4si) +VAR3 (QUADOP_UNONE_UNONE_UNONE_UNONE_PRED, vrmulhq_m_u, v16qi, v8hi, v4si) +VAR3 (QUADOP_UNONE_UNONE_UNONE_UNONE_PRED, vrhaddq_m_u, v16qi, v8hi, v4si) +VAR3 (QUADOP_UNONE_UNONE_UNONE_UNONE_PRED, vqsubq_m_u, v16qi, v8hi, v4si) +VAR3 (QUADOP_UNONE_UNONE_UNONE_UNONE_PRED, vqsubq_m_n_u, v16qi, v8hi, v4si) +VAR3 (QUADOP_UNONE_UNONE_UNONE_UNONE_PRED, vqaddq_m_u, v16qi, v8hi, v4si) +VAR3 (QUADOP_UNONE_UNONE_UNONE_UNONE_PRED, vqaddq_m_n_u, v16qi, v8hi, v4si) +VAR3 (QUADOP_UNONE_UNONE_UNONE_UNONE_PRED, vorrq_m_u, v16qi, v8hi, v4si) +VAR3 (QUADOP_UNONE_UNONE_UNONE_UNONE_PRED, vornq_m_u, v16qi, v8hi, v4si) +VAR3 (QUADOP_UNONE_UNONE_UNONE_UNONE_PRED, vmulq_m_u, v16qi, v8hi, v4si) +VAR3 (QUADOP_UNONE_UNONE_UNONE_UNONE_PRED, vmulq_m_n_u, v16qi, v8hi, v4si) +VAR3 (QUADOP_UNONE_UNONE_UNONE_UNONE_PRED, vmulltq_int_m_u, v16qi, v8hi, v4si) +VAR3 (QUADOP_UNONE_UNONE_UNONE_UNONE_PRED, vmullbq_int_m_u, v16qi, v8hi, v4si) +VAR3 (QUADOP_UNONE_UNONE_UNONE_UNONE_PRED, vmulhq_m_u, v16qi, v8hi, v4si) +VAR3 (QUADOP_UNONE_UNONE_UNONE_UNONE_PRED, vmlasq_m_n_u, v16qi, v8hi, v4si) +VAR3 (QUADOP_UNONE_UNONE_UNONE_UNONE_PRED, vmlaq_m_n_u, v16qi, v8hi, v4si) +VAR3 (QUADOP_UNONE_UNONE_UNONE_UNONE_PRED, vmladavaq_p_u, v16qi, v8hi, v4si) +VAR3 (QUADOP_UNONE_UNONE_UNONE_UNONE_PRED, vminq_m_u, v16qi, v8hi, v4si) +VAR3 (QUADOP_UNONE_UNONE_UNONE_UNONE_PRED, vmaxq_m_u, v16qi, v8hi, v4si) +VAR3 (QUADOP_UNONE_UNONE_UNONE_UNONE_PRED, vhsubq_m_u, v16qi, v8hi, v4si) +VAR3 (QUADOP_UNONE_UNONE_UNONE_UNONE_PRED, vhsubq_m_n_u, v16qi, v8hi, v4si) +VAR3 (QUADOP_UNONE_UNONE_UNONE_UNONE_PRED, vhaddq_m_u, v16qi, v8hi, v4si) +VAR3 (QUADOP_UNONE_UNONE_UNONE_UNONE_PRED, vhaddq_m_n_u, v16qi, v8hi, v4si) +VAR3 (QUADOP_UNONE_UNONE_UNONE_UNONE_PRED, veorq_m_u, v16qi, v8hi, v4si) +VAR3 (QUADOP_UNONE_UNONE_UNONE_UNONE_PRED, vcaddq_rot90_m_u, v16qi, v8hi, v4si) +VAR3 (QUADOP_UNONE_UNONE_UNONE_UNONE_PRED, vcaddq_rot270_m_u, v16qi, v8hi, v4si) +VAR3 (QUADOP_UNONE_UNONE_UNONE_UNONE_PRED, vbicq_m_u, v16qi, v8hi, v4si) +VAR3 (QUADOP_UNONE_UNONE_UNONE_UNONE_PRED, vandq_m_u, v16qi, v8hi, v4si) +VAR3 (QUADOP_UNONE_UNONE_UNONE_UNONE_PRED, vaddq_m_u, v16qi, v8hi, v4si) +VAR3 (QUADOP_UNONE_UNONE_UNONE_UNONE_PRED, vaddq_m_n_u, v16qi, v8hi, v4si) +VAR3 (QUADOP_UNONE_UNONE_UNONE_UNONE_PRED, vabdq_m_u, v16qi, v8hi, v4si) +VAR3 (QUADOP_UNONE_UNONE_UNONE_NONE_PRED, vrshlq_m_u, v16qi, v8hi, v4si) +VAR3 (QUADOP_UNONE_UNONE_UNONE_NONE_PRED, vqshlq_m_u, v16qi, v8hi, v4si) +VAR3 (QUADOP_UNONE_UNONE_UNONE_NONE_PRED, vqrshlq_m_u, v16qi, v8hi, v4si) +VAR3 (QUADOP_UNONE_UNONE_UNONE_NONE_PRED, vbrsrq_m_n_u, v16qi, v8hi, v4si) +VAR3 (QUADOP_UNONE_UNONE_UNONE_IMM_PRED, vsliq_m_n_u, v16qi, v8hi, v4si) +VAR3 (QUADOP_UNONE_UNONE_UNONE_IMM_PRED, vshrq_m_n_u, v16qi, v8hi, v4si) +VAR3 (QUADOP_UNONE_UNONE_UNONE_IMM_PRED, vshlq_m_n_u, v16qi, v8hi, v4si) +VAR3 (QUADOP_UNONE_UNONE_UNONE_IMM_PRED, vrshrq_m_n_u, v16qi, v8hi, v4si) +VAR3 (QUADOP_UNONE_UNONE_UNONE_IMM_PRED, vqshlq_m_n_u, v16qi, v8hi, v4si) +VAR3 (QUADOP_NONE_NONE_NONE_NONE_PRED, vsubq_m_n_s, v16qi, v8hi, v4si) +VAR3 (QUADOP_NONE_NONE_NONE_NONE_PRED, vrshlq_m_s, v16qi, v8hi, v4si) +VAR3 (QUADOP_NONE_NONE_NONE_NONE_PRED, vrmulhq_m_s, v16qi, v8hi, v4si) +VAR3 (QUADOP_NONE_NONE_NONE_NONE_PRED, vrhaddq_m_s, v16qi, v8hi, v4si) +VAR3 (QUADOP_NONE_NONE_NONE_NONE_PRED, vqsubq_m_s, v16qi, v8hi, v4si) +VAR3 (QUADOP_NONE_NONE_NONE_NONE_PRED, vqsubq_m_n_s, v16qi, v8hi, v4si) +VAR3 (QUADOP_NONE_NONE_NONE_NONE_PRED, vqshlq_m_s, v16qi, v8hi, v4si) +VAR3 (QUADOP_NONE_NONE_NONE_NONE_PRED, vqrshlq_m_s, v16qi, v8hi, v4si) +VAR3 (QUADOP_NONE_NONE_NONE_NONE_PRED, vqrdmulhq_m_s, v16qi, v8hi, v4si) +VAR3 (QUADOP_NONE_NONE_NONE_NONE_PRED, vqrdmulhq_m_n_s, v16qi, v8hi, v4si) +VAR3 (QUADOP_NONE_NONE_NONE_NONE_PRED, vqrdmlsdhxq_m_s, v16qi, v8hi, v4si) +VAR3 (QUADOP_NONE_NONE_NONE_NONE_PRED, vqrdmlsdhq_m_s, v16qi, v8hi, v4si) +VAR3 (QUADOP_NONE_NONE_NONE_NONE_PRED, vqrdmlashq_m_n_s, v16qi, v8hi, v4si) +VAR3 (QUADOP_NONE_NONE_NONE_NONE_PRED, vqrdmlahq_m_n_s, v16qi, v8hi, v4si) +VAR3 (QUADOP_NONE_NONE_NONE_NONE_PRED, vqrdmladhxq_m_s, v16qi, v8hi, v4si) +VAR3 (QUADOP_NONE_NONE_NONE_NONE_PRED, vqrdmladhq_m_s, v16qi, v8hi, v4si) +VAR3 (QUADOP_NONE_NONE_NONE_NONE_PRED, vqdmulhq_m_s, v16qi, v8hi, v4si) +VAR3 (QUADOP_NONE_NONE_NONE_NONE_PRED, vqdmulhq_m_n_s, v16qi, v8hi, v4si) +VAR3 (QUADOP_NONE_NONE_NONE_NONE_PRED, vqdmlsdhxq_m_s, v16qi, v8hi, v4si) +VAR3 (QUADOP_NONE_NONE_NONE_NONE_PRED, vqdmlsdhq_m_s, v16qi, v8hi, v4si) +VAR3 (QUADOP_NONE_NONE_NONE_NONE_PRED, vqdmlahq_m_n_s, v16qi, v8hi, v4si) +VAR3 (QUADOP_NONE_NONE_NONE_NONE_PRED, vqdmlashq_m_n_s, v16qi, v8hi, v4si) +VAR3 (QUADOP_NONE_NONE_NONE_NONE_PRED, vqdmladhxq_m_s, v16qi, v8hi, v4si) +VAR3 (QUADOP_NONE_NONE_NONE_NONE_PRED, vqdmladhq_m_s, v16qi, v8hi, v4si) +VAR3 (QUADOP_NONE_NONE_NONE_NONE_PRED, vqaddq_m_s, v16qi, v8hi, v4si) +VAR3 (QUADOP_NONE_NONE_NONE_NONE_PRED, vqaddq_m_n_s, v16qi, v8hi, v4si) +VAR3 (QUADOP_NONE_NONE_NONE_NONE_PRED, vorrq_m_s, v16qi, v8hi, v4si) +VAR3 (QUADOP_NONE_NONE_NONE_NONE_PRED, vornq_m_s, v16qi, v8hi, v4si) +VAR3 (QUADOP_NONE_NONE_NONE_NONE_PRED, vmulq_m_s, v16qi, v8hi, v4si) +VAR3 (QUADOP_NONE_NONE_NONE_NONE_PRED, vmulq_m_n_s, v16qi, v8hi, v4si) +VAR3 (QUADOP_NONE_NONE_NONE_NONE_PRED, vmulltq_int_m_s, v16qi, v8hi, v4si) +VAR3 (QUADOP_NONE_NONE_NONE_NONE_PRED, vmullbq_int_m_s, v16qi, v8hi, v4si) +VAR3 (QUADOP_NONE_NONE_NONE_NONE_PRED, vmulhq_m_s, v16qi, v8hi, v4si) +VAR3 (QUADOP_NONE_NONE_NONE_NONE_PRED, vmlsdavaxq_p_s, v16qi, v8hi, v4si) +VAR3 (QUADOP_NONE_NONE_NONE_NONE_PRED, vmlsdavaq_p_s, v16qi, v8hi, v4si) +VAR3 (QUADOP_NONE_NONE_NONE_NONE_PRED, vmlasq_m_n_s, v16qi, v8hi, v4si) +VAR3 (QUADOP_NONE_NONE_NONE_NONE_PRED, vmlaq_m_n_s, v16qi, v8hi, v4si) +VAR3 (QUADOP_NONE_NONE_NONE_NONE_PRED, vmladavaxq_p_s, v16qi, v8hi, v4si) +VAR3 (QUADOP_NONE_NONE_NONE_NONE_PRED, vmladavaq_p_s, v16qi, v8hi, v4si) +VAR3 (QUADOP_NONE_NONE_NONE_NONE_PRED, vminq_m_s, v16qi, v8hi, v4si) +VAR3 (QUADOP_NONE_NONE_NONE_NONE_PRED, vmaxq_m_s, v16qi, v8hi, v4si) +VAR3 (QUADOP_NONE_NONE_NONE_NONE_PRED, vhsubq_m_s, v16qi, v8hi, v4si) +VAR3 (QUADOP_NONE_NONE_NONE_NONE_PRED, vhsubq_m_n_s, v16qi, v8hi, v4si) +VAR3 (QUADOP_NONE_NONE_NONE_NONE_PRED, vhcaddq_rot90_m_s, v16qi, v8hi, v4si) +VAR3 (QUADOP_NONE_NONE_NONE_NONE_PRED, vhcaddq_rot270_m_s, v16qi, v8hi, v4si) +VAR3 (QUADOP_NONE_NONE_NONE_NONE_PRED, vhaddq_m_s, v16qi, v8hi, v4si) +VAR3 (QUADOP_NONE_NONE_NONE_NONE_PRED, vhaddq_m_n_s, v16qi, v8hi, v4si) +VAR3 (QUADOP_NONE_NONE_NONE_NONE_PRED, veorq_m_s, v16qi, v8hi, v4si) +VAR3 (QUADOP_NONE_NONE_NONE_NONE_PRED, vcaddq_rot90_m_s, v16qi, v8hi, v4si) +VAR3 (QUADOP_NONE_NONE_NONE_NONE_PRED, vcaddq_rot270_m_s, v16qi, v8hi, v4si) +VAR3 (QUADOP_NONE_NONE_NONE_NONE_PRED, vbrsrq_m_n_s, v16qi, v8hi, v4si) +VAR3 (QUADOP_NONE_NONE_NONE_NONE_PRED, vbicq_m_s, v16qi, v8hi, v4si) +VAR3 (QUADOP_NONE_NONE_NONE_NONE_PRED, vandq_m_s, v16qi, v8hi, v4si) +VAR3 (QUADOP_NONE_NONE_NONE_NONE_PRED, vaddq_m_s, v16qi, v8hi, v4si) +VAR3 (QUADOP_NONE_NONE_NONE_NONE_PRED, vaddq_m_n_s, v16qi, v8hi, v4si) +VAR3 (QUADOP_NONE_NONE_NONE_NONE_PRED, vabdq_m_s, v16qi, v8hi, v4si) +VAR3 (QUADOP_NONE_NONE_NONE_IMM_PRED, vsliq_m_n_s, v16qi, v8hi, v4si) +VAR3 (QUADOP_NONE_NONE_NONE_IMM_PRED, vshrq_m_n_s, v16qi, v8hi, v4si) +VAR3 (QUADOP_NONE_NONE_NONE_IMM_PRED, vshlq_m_n_s, v16qi, v8hi, v4si) +VAR3 (QUADOP_NONE_NONE_NONE_IMM_PRED, vrshrq_m_n_s, v16qi, v8hi, v4si) +VAR3 (QUADOP_NONE_NONE_NONE_IMM_PRED, vqshlq_m_n_s, v16qi, v8hi, v4si) +VAR2 (QUADOP_UNONE_UNONE_UNONE_UNONE_PRED, vmulltq_poly_m_p, v16qi, v8hi) +VAR2 (QUADOP_UNONE_UNONE_UNONE_UNONE_PRED, vmullbq_poly_m_p, v16qi, v8hi) +VAR2 (QUADOP_UNONE_UNONE_UNONE_UNONE_PRED, vmlaldavaq_p_u, v8hi, v4si) +VAR2 (QUADOP_UNONE_UNONE_UNONE_IMM_PRED, vshrntq_m_n_u, v8hi, v4si) +VAR2 (QUADOP_UNONE_UNONE_UNONE_IMM_PRED, vshrnbq_m_n_u, v8hi, v4si) +VAR2 (QUADOP_UNONE_UNONE_UNONE_IMM_PRED, vshlltq_m_n_u, v16qi, v8hi) +VAR2 (QUADOP_UNONE_UNONE_UNONE_IMM_PRED, vshllbq_m_n_u, v16qi, v8hi) +VAR2 (QUADOP_UNONE_UNONE_UNONE_IMM_PRED, vrshrntq_m_n_u, v8hi, v4si) +VAR2 (QUADOP_UNONE_UNONE_UNONE_IMM_PRED, vrshrnbq_m_n_u, v8hi, v4si) +VAR2 (QUADOP_UNONE_UNONE_UNONE_IMM_PRED, vqshrntq_m_n_u, v8hi, v4si) +VAR2 (QUADOP_UNONE_UNONE_UNONE_IMM_PRED, vqshrnbq_m_n_u, v8hi, v4si) +VAR2 (QUADOP_UNONE_UNONE_UNONE_IMM_PRED, vqrshrntq_m_n_u, v8hi, v4si) +VAR2 (QUADOP_UNONE_UNONE_UNONE_IMM_PRED, vqrshrnbq_m_n_u, v8hi, v4si) +VAR2 (QUADOP_UNONE_UNONE_NONE_IMM_PRED, vqshruntq_m_n_s, v8hi, v4si) +VAR2 (QUADOP_UNONE_UNONE_NONE_IMM_PRED, vqshrunbq_m_n_s, v8hi, v4si) +VAR2 (QUADOP_UNONE_UNONE_NONE_IMM_PRED, vqrshruntq_m_n_s, v8hi, v4si) +VAR2 (QUADOP_UNONE_UNONE_NONE_IMM_PRED, vqrshrunbq_m_n_s, v8hi, v4si) +VAR2 (QUADOP_NONE_NONE_NONE_NONE_PRED, vqdmulltq_m_s, v8hi, v4si) +VAR2 (QUADOP_NONE_NONE_NONE_NONE_PRED, vqdmulltq_m_n_s, v8hi, v4si) +VAR2 (QUADOP_NONE_NONE_NONE_NONE_PRED, vqdmullbq_m_s, v8hi, v4si) +VAR2 (QUADOP_NONE_NONE_NONE_NONE_PRED, vqdmullbq_m_n_s, v8hi, v4si) +VAR2 (QUADOP_NONE_NONE_NONE_NONE_PRED, vmlsldavaxq_p_s, v8hi, v4si) +VAR2 (QUADOP_NONE_NONE_NONE_NONE_PRED, vmlsldavaq_p_s, v8hi, v4si) +VAR2 (QUADOP_NONE_NONE_NONE_NONE_PRED, vmlaldavaxq_p_s, v8hi, v4si) +VAR2 (QUADOP_NONE_NONE_NONE_NONE_PRED, vmlaldavaq_p_s, v8hi, v4si) +VAR2 (QUADOP_NONE_NONE_NONE_IMM_PRED, vshrntq_m_n_s, v8hi, v4si) +VAR2 (QUADOP_NONE_NONE_NONE_IMM_PRED, vshrnbq_m_n_s, v8hi, v4si) +VAR2 (QUADOP_NONE_NONE_NONE_IMM_PRED, vshlltq_m_n_s, v16qi, v8hi) +VAR2 (QUADOP_NONE_NONE_NONE_IMM_PRED, vshllbq_m_n_s, v16qi, v8hi) +VAR2 (QUADOP_NONE_NONE_NONE_IMM_PRED, vrshrntq_m_n_s, v8hi, v4si) +VAR2 (QUADOP_NONE_NONE_NONE_IMM_PRED, vrshrnbq_m_n_s, v8hi, v4si) +VAR2 (QUADOP_NONE_NONE_NONE_IMM_PRED, vqshrntq_m_n_s, v8hi, v4si) +VAR2 (QUADOP_NONE_NONE_NONE_IMM_PRED, vqshrnbq_m_n_s, v8hi, v4si) +VAR2 (QUADOP_NONE_NONE_NONE_IMM_PRED, vqrshrntq_m_n_s, v8hi, v4si) +VAR2 (QUADOP_NONE_NONE_NONE_IMM_PRED, vqrshrnbq_m_n_s, v8hi, v4si) VAR1 (QUADOP_UNONE_UNONE_UNONE_UNONE_UNONE, vrmlaldavhaq_p_u, v4si) VAR1 (QUADOP_NONE_NONE_NONE_NONE_UNONE, vrmlsldavhaxq_p_s, v4si) VAR1 (QUADOP_NONE_NONE_NONE_NONE_UNONE, vrmlsldavhaq_p_s, v4si) VAR1 (QUADOP_NONE_NONE_NONE_NONE_UNONE, vrmlaldavhaxq_p_s, v4si) VAR1 (QUADOP_NONE_NONE_NONE_NONE_UNONE, vrmlaldavhaq_p_s, v4si) -VAR2 (QUADOP_UNONE_UNONE_NONE_IMM_UNONE, vcvtq_m_n_from_f_u, v8hi, v4si) -VAR2 (QUADOP_NONE_NONE_NONE_IMM_UNONE, vcvtq_m_n_from_f_s, v8hi, v4si) -VAR2 (QUADOP_NONE_NONE_NONE_NONE_UNONE, vbrsrq_m_n_f, v8hf, v4sf) -VAR2 (QUADOP_NONE_NONE_NONE_NONE_UNONE, vsubq_m_n_f, v8hf, v4sf) -VAR2 (QUADOP_NONE_NONE_NONE_NONE_UNONE, vsubq_m_f, v8hf, v4sf) -VAR2 (QUADOP_NONE_NONE_NONE_NONE_UNONE, vorrq_m_f, v8hf, v4sf) -VAR2 (QUADOP_NONE_NONE_NONE_NONE_UNONE, vornq_m_f, v8hf, v4sf) -VAR2 (QUADOP_NONE_NONE_NONE_NONE_UNONE, vmulq_m_n_f, v8hf, v4sf) -VAR2 (QUADOP_NONE_NONE_NONE_NONE_UNONE, vmulq_m_f, v8hf, v4sf) -VAR2 (QUADOP_NONE_NONE_NONE_NONE_UNONE, vminnmq_m_f, v8hf, v4sf) -VAR2 (QUADOP_NONE_NONE_NONE_NONE_UNONE, vmaxnmq_m_f, v8hf, v4sf) -VAR2 (QUADOP_NONE_NONE_NONE_NONE_UNONE, vfmsq_m_f, v8hf, v4sf) -VAR2 (QUADOP_NONE_NONE_NONE_NONE_UNONE, vfmasq_m_n_f, v8hf, v4sf) -VAR2 (QUADOP_NONE_NONE_NONE_NONE_UNONE, vfmaq_m_n_f, v8hf, v4sf) -VAR2 (QUADOP_NONE_NONE_NONE_NONE_UNONE, vfmaq_m_f, v8hf, v4sf) -VAR2 (QUADOP_NONE_NONE_NONE_NONE_UNONE, veorq_m_f, v8hf, v4sf) -VAR2 (QUADOP_NONE_NONE_NONE_NONE_UNONE, vcmulq_rot90_m_f, v8hf, v4sf) -VAR2 (QUADOP_NONE_NONE_NONE_NONE_UNONE, vcmulq_rot270_m_f, v8hf, v4sf) -VAR2 (QUADOP_NONE_NONE_NONE_NONE_UNONE, vcmulq_rot180_m_f, v8hf, v4sf) -VAR2 (QUADOP_NONE_NONE_NONE_NONE_UNONE, vcmulq_m_f, v8hf, v4sf) -VAR2 (QUADOP_NONE_NONE_NONE_NONE_UNONE, vcmlaq_rot90_m_f, v8hf, v4sf) -VAR2 (QUADOP_NONE_NONE_NONE_NONE_UNONE, vcmlaq_rot270_m_f, v8hf, v4sf) -VAR2 (QUADOP_NONE_NONE_NONE_NONE_UNONE, vcmlaq_rot180_m_f, v8hf, v4sf) -VAR2 (QUADOP_NONE_NONE_NONE_NONE_UNONE, vcmlaq_m_f, v8hf, v4sf) -VAR2 (QUADOP_NONE_NONE_NONE_NONE_UNONE, vcaddq_rot90_m_f, v8hf, v4sf) -VAR2 (QUADOP_NONE_NONE_NONE_NONE_UNONE, vcaddq_rot270_m_f, v8hf, v4sf) -VAR2 (QUADOP_NONE_NONE_NONE_NONE_UNONE, vbicq_m_f, v8hf, v4sf) -VAR2 (QUADOP_NONE_NONE_NONE_NONE_UNONE, vandq_m_f, v8hf, v4sf) -VAR2 (QUADOP_NONE_NONE_NONE_NONE_UNONE, vaddq_m_n_f, v8hf, v4sf) -VAR2 (QUADOP_NONE_NONE_NONE_NONE_UNONE, vaddq_m_f, v8hf, v4sf) -VAR2 (QUADOP_NONE_NONE_NONE_NONE_UNONE, vabdq_m_f, v8hf, v4sf) +VAR2 (QUADOP_UNONE_UNONE_NONE_IMM_PRED, vcvtq_m_n_from_f_u, v8hi, v4si) +VAR2 (QUADOP_NONE_NONE_NONE_IMM_PRED, vcvtq_m_n_from_f_s, v8hi, v4si) +VAR2 (QUADOP_NONE_NONE_NONE_NONE_PRED, vbrsrq_m_n_f, v8hf, v4sf) +VAR2 (QUADOP_NONE_NONE_NONE_NONE_PRED, vsubq_m_n_f, v8hf, v4sf) +VAR2 (QUADOP_NONE_NONE_NONE_NONE_PRED, vsubq_m_f, v8hf, v4sf) +VAR2 (QUADOP_NONE_NONE_NONE_NONE_PRED, vorrq_m_f, v8hf, v4sf) +VAR2 (QUADOP_NONE_NONE_NONE_NONE_PRED, vornq_m_f, v8hf, v4sf) +VAR2 (QUADOP_NONE_NONE_NONE_NONE_PRED, vmulq_m_n_f, v8hf, v4sf) +VAR2 (QUADOP_NONE_NONE_NONE_NONE_PRED, vmulq_m_f, v8hf, v4sf) +VAR2 (QUADOP_NONE_NONE_NONE_NONE_PRED, vminnmq_m_f, v8hf, v4sf) +VAR2 (QUADOP_NONE_NONE_NONE_NONE_PRED, vmaxnmq_m_f, v8hf, v4sf) +VAR2 (QUADOP_NONE_NONE_NONE_NONE_PRED, vfmsq_m_f, v8hf, v4sf) +VAR2 (QUADOP_NONE_NONE_NONE_NONE_PRED, vfmasq_m_n_f, v8hf, v4sf) +VAR2 (QUADOP_NONE_NONE_NONE_NONE_PRED, vfmaq_m_n_f, v8hf, v4sf) +VAR2 (QUADOP_NONE_NONE_NONE_NONE_PRED, vfmaq_m_f, v8hf, v4sf) +VAR2 (QUADOP_NONE_NONE_NONE_NONE_PRED, veorq_m_f, v8hf, v4sf) +VAR2 (QUADOP_NONE_NONE_NONE_NONE_PRED, vcmulq_rot90_m_f, v8hf, v4sf) +VAR2 (QUADOP_NONE_NONE_NONE_NONE_PRED, vcmulq_rot270_m_f, v8hf, v4sf) +VAR2 (QUADOP_NONE_NONE_NONE_NONE_PRED, vcmulq_rot180_m_f, v8hf, v4sf) +VAR2 (QUADOP_NONE_NONE_NONE_NONE_PRED, vcmulq_m_f, v8hf, v4sf) +VAR2 (QUADOP_NONE_NONE_NONE_NONE_PRED, vcmlaq_rot90_m_f, v8hf, v4sf) +VAR2 (QUADOP_NONE_NONE_NONE_NONE_PRED, vcmlaq_rot270_m_f, v8hf, v4sf) +VAR2 (QUADOP_NONE_NONE_NONE_NONE_PRED, vcmlaq_rot180_m_f, v8hf, v4sf) +VAR2 (QUADOP_NONE_NONE_NONE_NONE_PRED, vcmlaq_m_f, v8hf, v4sf) +VAR2 (QUADOP_NONE_NONE_NONE_NONE_PRED, vcaddq_rot90_m_f, v8hf, v4sf) +VAR2 (QUADOP_NONE_NONE_NONE_NONE_PRED, vcaddq_rot270_m_f, v8hf, v4sf) +VAR2 (QUADOP_NONE_NONE_NONE_NONE_PRED, vbicq_m_f, v8hf, v4sf) +VAR2 (QUADOP_NONE_NONE_NONE_NONE_PRED, vandq_m_f, v8hf, v4sf) +VAR2 (QUADOP_NONE_NONE_NONE_NONE_PRED, vaddq_m_n_f, v8hf, v4sf) +VAR2 (QUADOP_NONE_NONE_NONE_NONE_PRED, vaddq_m_f, v8hf, v4sf) +VAR2 (QUADOP_NONE_NONE_NONE_NONE_PRED, vabdq_m_f, v8hf, v4sf) VAR3 (STRS, vstrbq_s, v16qi, v8hi, v4si) VAR3 (STRU, vstrbq_u, v16qi, v8hi, v4si) VAR3 (STRSS, vstrbq_scatter_offset_s, v16qi, v8hi, v4si) @@ -797,14 +797,14 @@ VAR1 (STRSU_P, vstrwq_scatter_offset_p_u, v4si) VAR1 (STRSU_P, vstrwq_scatter_shifted_offset_p_u, v4si) VAR3 (TERNOP_UNONE_UNONE_UNONE_IMM, viwdupq_wb_u, v16qi, v4si, v8hi) VAR3 (TERNOP_UNONE_UNONE_UNONE_IMM, vdwdupq_wb_u, v16qi, v4si, v8hi) -VAR3 (QUINOP_UNONE_UNONE_UNONE_UNONE_IMM_UNONE, viwdupq_m_wb_u, v16qi, v8hi, v4si) -VAR3 (QUINOP_UNONE_UNONE_UNONE_UNONE_IMM_UNONE, vdwdupq_m_wb_u, v16qi, v8hi, v4si) -VAR3 (QUINOP_UNONE_UNONE_UNONE_UNONE_IMM_UNONE, viwdupq_m_n_u, v16qi, v8hi, v4si) -VAR3 (QUINOP_UNONE_UNONE_UNONE_UNONE_IMM_UNONE, vdwdupq_m_n_u, v16qi, v8hi, v4si) +VAR3 (QUINOP_UNONE_UNONE_UNONE_UNONE_IMM_PRED, viwdupq_m_wb_u, v16qi, v8hi, v4si) +VAR3 (QUINOP_UNONE_UNONE_UNONE_UNONE_IMM_PRED, vdwdupq_m_wb_u, v16qi, v8hi, v4si) +VAR3 (QUINOP_UNONE_UNONE_UNONE_UNONE_IMM_PRED, viwdupq_m_n_u, v16qi, v8hi, v4si) +VAR3 (QUINOP_UNONE_UNONE_UNONE_UNONE_IMM_PRED, vdwdupq_m_n_u, v16qi, v8hi, v4si) VAR3 (BINOP_UNONE_UNONE_IMM, vddupq_n_u, v16qi, v8hi, v4si) VAR3 (BINOP_UNONE_UNONE_IMM, vidupq_n_u, v16qi, v8hi, v4si) -VAR3 (QUADOP_UNONE_UNONE_UNONE_IMM_UNONE, vddupq_m_n_u, v16qi, v8hi, v4si) -VAR3 (QUADOP_UNONE_UNONE_UNONE_IMM_UNONE, vidupq_m_n_u, v16qi, v8hi, v4si) +VAR3 (QUADOP_UNONE_UNONE_UNONE_IMM_PRED, vddupq_m_n_u, v16qi, v8hi, v4si) +VAR3 (QUADOP_UNONE_UNONE_UNONE_IMM_PRED, vidupq_m_n_u, v16qi, v8hi, v4si) VAR3 (TERNOP_UNONE_UNONE_UNONE_IMM, vdwdupq_n_u, v16qi, v4si, v8hi) VAR3 (TERNOP_UNONE_UNONE_UNONE_IMM, viwdupq_n_u, v16qi, v4si, v8hi) VAR1 (STRSBWBU, vstrwq_scatter_base_wb_u, v4si) @@ -870,10 +870,10 @@ VAR1 (UQSHL, urshr_, si) VAR1 (UQSHL, urshrl_, di) VAR1 (UQSHL, uqshl_, si) VAR1 (UQSHL, uqshll_, di) -VAR3 (QUADOP_NONE_NONE_UNONE_IMM_UNONE, vshlcq_m_vec_s, v16qi, v8hi, v4si) -VAR3 (QUADOP_NONE_NONE_UNONE_IMM_UNONE, vshlcq_m_carry_s, v16qi, v8hi, v4si) -VAR3 (QUADOP_UNONE_UNONE_UNONE_IMM_UNONE, vshlcq_m_vec_u, v16qi, v8hi, v4si) -VAR3 (QUADOP_UNONE_UNONE_UNONE_IMM_UNONE, vshlcq_m_carry_u, v16qi, v8hi, v4si) +VAR3 (QUADOP_NONE_NONE_UNONE_IMM_PRED, vshlcq_m_vec_s, v16qi, v8hi, v4si) +VAR3 (QUADOP_NONE_NONE_UNONE_IMM_PRED, vshlcq_m_carry_s, v16qi, v8hi, v4si) +VAR3 (QUADOP_UNONE_UNONE_UNONE_IMM_PRED, vshlcq_m_vec_u, v16qi, v8hi, v4si) +VAR3 (QUADOP_UNONE_UNONE_UNONE_IMM_PRED, vshlcq_m_carry_u, v16qi, v8hi, v4si) /* optabs without any suffixes. */ VAR5 (BINOP_NONE_NONE_NONE, vcaddq_rot90, v16qi, v8hi, v4si, v8hf, v4sf) diff --git a/gcc/config/arm/mve.md b/gcc/config/arm/mve.md index 4867aa79687..2f36d47c800 100644 --- a/gcc/config/arm/mve.md +++ b/gcc/config/arm/mve.md @@ -130,7 +130,7 @@ (define_insn "mve_vrndq_m_f<mode>" (set (match_operand:MVE_0 0 "s_register_operand" "=w") (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0") (match_operand:MVE_0 2 "s_register_operand" "w") - (match_operand:HI 3 "vpr_register_operand" "Up")] + (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")] VRNDQ_M_F)) ] "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" @@ -918,7 +918,7 @@ (define_insn "mve_vaddvq_p_<supf><mode>" [ (set (match_operand:SI 0 "s_register_operand" "=Te") (unspec:SI [(match_operand:MVE_2 1 "s_register_operand" "w") - (match_operand:HI 2 "vpr_register_operand" "Up")] + (match_operand:<MVE_VPRED> 2 "vpr_register_operand" "Up")] VADDVQ_P)) ] "TARGET_HAVE_MVE" @@ -2581,7 +2581,7 @@ (define_insn "mve_vbicq_m_n_<supf><mode>" (set (match_operand:MVE_5 0 "s_register_operand" "=w") (unspec:MVE_5 [(match_operand:MVE_5 1 "s_register_operand" "0") (match_operand:SI 2 "immediate_operand" "i") - (match_operand:HI 3 "vpr_register_operand" "Up")] + (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")] VBICQ_M_N)) ] "TARGET_HAVE_MVE" @@ -2611,7 +2611,7 @@ (define_insn "mve_vcvtaq_m_<supf><mode>" (set (match_operand:MVE_5 0 "s_register_operand" "=w") (unspec:MVE_5 [(match_operand:MVE_5 1 "s_register_operand" "0") (match_operand:<MVE_CNVT> 2 "s_register_operand" "w") - (match_operand:HI 3 "vpr_register_operand" "Up")] + (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")] VCVTAQ_M)) ] "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" @@ -2626,7 +2626,7 @@ (define_insn "mve_vcvtq_m_to_f_<supf><mode>" (set (match_operand:MVE_0 0 "s_register_operand" "=w") (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0") (match_operand:<MVE_CNVT> 2 "s_register_operand" "w") - (match_operand:HI 3 "vpr_register_operand" "Up")] + (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")] VCVTQ_M_TO_F)) ] "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" @@ -2748,7 +2748,7 @@ (define_insn "mve_vabsq_m_s<mode>" (set (match_operand:MVE_2 0 "s_register_operand" "=w") (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") (match_operand:MVE_2 2 "s_register_operand" "w") - (match_operand:HI 3 "vpr_register_operand" "Up")] + (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")] VABSQ_M_S)) ] "TARGET_HAVE_MVE" @@ -2764,7 +2764,7 @@ (define_insn "mve_vaddvaq_p_<supf><mode>" (set (match_operand:SI 0 "s_register_operand" "=Te") (unspec:SI [(match_operand:SI 1 "s_register_operand" "0") (match_operand:MVE_2 2 "s_register_operand" "w") - (match_operand:HI 3 "vpr_register_operand" "Up")] + (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")] VADDVAQ_P)) ] "TARGET_HAVE_MVE" @@ -2780,7 +2780,7 @@ (define_insn "mve_vclsq_m_s<mode>" (set (match_operand:MVE_2 0 "s_register_operand" "=w") (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") (match_operand:MVE_2 2 "s_register_operand" "w") - (match_operand:HI 3 "vpr_register_operand" "Up")] + (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")] VCLSQ_M_S)) ] "TARGET_HAVE_MVE" @@ -2796,7 +2796,7 @@ (define_insn "mve_vclzq_m_<supf><mode>" (set (match_operand:MVE_2 0 "s_register_operand" "=w") (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") (match_operand:MVE_2 2 "s_register_operand" "w") - (match_operand:HI 3 "vpr_register_operand" "Up")] + (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")] VCLZQ_M)) ] "TARGET_HAVE_MVE" @@ -3068,7 +3068,7 @@ (define_insn "mve_vdupq_m_n_<supf><mode>" (set (match_operand:MVE_2 0 "s_register_operand" "=w") (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") (match_operand:<V_elem> 2 "s_register_operand" "r") - (match_operand:HI 3 "vpr_register_operand" "Up")] + (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")] VDUPQ_M_N)) ] "TARGET_HAVE_MVE" @@ -3084,7 +3084,7 @@ (define_insn "mve_vmaxaq_m_s<mode>" (set (match_operand:MVE_2 0 "s_register_operand" "=w") (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") (match_operand:MVE_2 2 "s_register_operand" "w") - (match_operand:HI 3 "vpr_register_operand" "Up")] + (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")] VMAXAQ_M_S)) ] "TARGET_HAVE_MVE" @@ -3100,7 +3100,7 @@ (define_insn "mve_vmaxavq_p_s<mode>" (set (match_operand:<V_elem> 0 "s_register_operand" "=r") (unspec:<V_elem> [(match_operand:<V_elem> 1 "s_register_operand" "0") (match_operand:MVE_2 2 "s_register_operand" "w") - (match_operand:HI 3 "vpr_register_operand" "Up")] + (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")] VMAXAVQ_P_S)) ] "TARGET_HAVE_MVE" @@ -3116,7 +3116,7 @@ (define_insn "mve_vmaxvq_p_<supf><mode>" (set (match_operand:<V_elem> 0 "s_register_operand" "=r") (unspec:<V_elem> [(match_operand:<V_elem> 1 "s_register_operand" "0") (match_operand:MVE_2 2 "s_register_operand" "w") - (match_operand:HI 3 "vpr_register_operand" "Up")] + (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")] VMAXVQ_P)) ] "TARGET_HAVE_MVE" @@ -3132,7 +3132,7 @@ (define_insn "mve_vminaq_m_s<mode>" (set (match_operand:MVE_2 0 "s_register_operand" "=w") (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") (match_operand:MVE_2 2 "s_register_operand" "w") - (match_operand:HI 3 "vpr_register_operand" "Up")] + (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")] VMINAQ_M_S)) ] "TARGET_HAVE_MVE" @@ -3148,7 +3148,7 @@ (define_insn "mve_vminavq_p_s<mode>" (set (match_operand:<V_elem> 0 "s_register_operand" "=r") (unspec:<V_elem> [(match_operand:<V_elem> 1 "s_register_operand" "0") (match_operand:MVE_2 2 "s_register_operand" "w") - (match_operand:HI 3 "vpr_register_operand" "Up")] + (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")] VMINAVQ_P_S)) ] "TARGET_HAVE_MVE" @@ -3164,7 +3164,7 @@ (define_insn "mve_vminvq_p_<supf><mode>" (set (match_operand:<V_elem> 0 "s_register_operand" "=r") (unspec:<V_elem> [(match_operand:<V_elem> 1 "s_register_operand" "0") (match_operand:MVE_2 2 "s_register_operand" "w") - (match_operand:HI 3 "vpr_register_operand" "Up")] + (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")] VMINVQ_P)) ] "TARGET_HAVE_MVE" @@ -3196,7 +3196,7 @@ (define_insn "mve_vmladavq_p_<supf><mode>" (set (match_operand:SI 0 "s_register_operand" "=Te") (unspec:SI [(match_operand:MVE_2 1 "s_register_operand" "w") (match_operand:MVE_2 2 "s_register_operand" "w") - (match_operand:HI 3 "vpr_register_operand" "Up")] + (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")] VMLADAVQ_P)) ] "TARGET_HAVE_MVE" @@ -3212,7 +3212,7 @@ (define_insn "mve_vmladavxq_p_s<mode>" (set (match_operand:SI 0 "s_register_operand" "=Te") (unspec:SI [(match_operand:MVE_2 1 "s_register_operand" "w") (match_operand:MVE_2 2 "s_register_operand" "w") - (match_operand:HI 3 "vpr_register_operand" "Up")] + (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")] VMLADAVXQ_P_S)) ] "TARGET_HAVE_MVE" @@ -3260,7 +3260,7 @@ (define_insn "mve_vmlsdavq_p_s<mode>" (set (match_operand:SI 0 "s_register_operand" "=Te") (unspec:SI [(match_operand:MVE_2 1 "s_register_operand" "w") (match_operand:MVE_2 2 "s_register_operand" "w") - (match_operand:HI 3 "vpr_register_operand" "Up")] + (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")] VMLSDAVQ_P_S)) ] "TARGET_HAVE_MVE" @@ -3276,7 +3276,7 @@ (define_insn "mve_vmlsdavxq_p_s<mode>" (set (match_operand:SI 0 "s_register_operand" "=Te") (unspec:SI [(match_operand:MVE_2 1 "s_register_operand" "w") (match_operand:MVE_2 2 "s_register_operand" "w") - (match_operand:HI 3 "vpr_register_operand" "Up")] + (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")] VMLSDAVXQ_P_S)) ] "TARGET_HAVE_MVE" @@ -3292,7 +3292,7 @@ (define_insn "mve_vmvnq_m_<supf><mode>" (set (match_operand:MVE_2 0 "s_register_operand" "=w") (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") (match_operand:MVE_2 2 "s_register_operand" "w") - (match_operand:HI 3 "vpr_register_operand" "Up")] + (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")] VMVNQ_M)) ] "TARGET_HAVE_MVE" @@ -3308,7 +3308,7 @@ (define_insn "mve_vnegq_m_s<mode>" (set (match_operand:MVE_2 0 "s_register_operand" "=w") (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") (match_operand:MVE_2 2 "s_register_operand" "w") - (match_operand:HI 3 "vpr_register_operand" "Up")] + (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")] VNEGQ_M_S)) ] "TARGET_HAVE_MVE" @@ -3352,7 +3352,7 @@ (define_insn "mve_vqabsq_m_s<mode>" (set (match_operand:MVE_2 0 "s_register_operand" "=w") (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") (match_operand:MVE_2 2 "s_register_operand" "w") - (match_operand:HI 3 "vpr_register_operand" "Up")] + (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")] VQABSQ_M_S)) ] "TARGET_HAVE_MVE" @@ -3400,7 +3400,7 @@ (define_insn "mve_vqnegq_m_s<mode>" (set (match_operand:MVE_2 0 "s_register_operand" "=w") (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") (match_operand:MVE_2 2 "s_register_operand" "w") - (match_operand:HI 3 "vpr_register_operand" "Up")] + (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")] VQNEGQ_M_S)) ] "TARGET_HAVE_MVE" @@ -3512,7 +3512,7 @@ (define_insn "mve_vqrshlq_m_n_<supf><mode>" (set (match_operand:MVE_2 0 "s_register_operand" "=w") (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") (match_operand:SI 2 "s_register_operand" "r") - (match_operand:HI 3 "vpr_register_operand" "Up")] + (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")] VQRSHLQ_M_N)) ] "TARGET_HAVE_MVE" @@ -3528,7 +3528,7 @@ (define_insn "mve_vqshlq_m_r_<supf><mode>" (set (match_operand:MVE_2 0 "s_register_operand" "=w") (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") (match_operand:SI 2 "s_register_operand" "r") - (match_operand:HI 3 "vpr_register_operand" "Up")] + (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")] VQSHLQ_M_R)) ] "TARGET_HAVE_MVE" @@ -3544,7 +3544,7 @@ (define_insn "mve_vrev64q_m_<supf><mode>" (set (match_operand:MVE_2 0 "s_register_operand" "=w") (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") (match_operand:MVE_2 2 "s_register_operand" "w") - (match_operand:HI 3 "vpr_register_operand" "Up")] + (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")] VREV64Q_M)) ] "TARGET_HAVE_MVE" @@ -3560,7 +3560,7 @@ (define_insn "mve_vrshlq_m_n_<supf><mode>" (set (match_operand:MVE_2 0 "s_register_operand" "=w") (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") (match_operand:SI 2 "s_register_operand" "r") - (match_operand:HI 3 "vpr_register_operand" "Up")] + (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")] VRSHLQ_M_N)) ] "TARGET_HAVE_MVE" @@ -3576,7 +3576,7 @@ (define_insn "mve_vshlq_m_r_<supf><mode>" (set (match_operand:MVE_2 0 "s_register_operand" "=w") (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") (match_operand:SI 2 "s_register_operand" "r") - (match_operand:HI 3 "vpr_register_operand" "Up")] + (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")] VSHLQ_M_R)) ] "TARGET_HAVE_MVE" @@ -3735,7 +3735,7 @@ (define_insn "mve_vabsq_m_f<mode>" (set (match_operand:MVE_0 0 "s_register_operand" "=w") (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0") (match_operand:MVE_0 2 "s_register_operand" "w") - (match_operand:HI 3 "vpr_register_operand" "Up")] + (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")] VABSQ_M_F)) ] "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" @@ -4025,7 +4025,7 @@ (define_insn "mve_vdupq_m_n_f<mode>" (set (match_operand:MVE_0 0 "s_register_operand" "=w") (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0") (match_operand:<V_elem> 2 "s_register_operand" "r") - (match_operand:HI 3 "vpr_register_operand" "Up")] + (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")] VDUPQ_M_N_F)) ] "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" @@ -4104,7 +4104,7 @@ (define_insn "mve_vmaxnmaq_m_f<mode>" (set (match_operand:MVE_0 0 "s_register_operand" "=w") (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0") (match_operand:MVE_0 2 "s_register_operand" "w") - (match_operand:HI 3 "vpr_register_operand" "Up")] + (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")] VMAXNMAQ_M_F)) ] "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" @@ -4119,7 +4119,7 @@ (define_insn "mve_vmaxnmavq_p_f<mode>" (set (match_operand:<V_elem> 0 "s_register_operand" "=r") (unspec:<V_elem> [(match_operand:<V_elem> 1 "s_register_operand" "0") (match_operand:MVE_0 2 "s_register_operand" "w") - (match_operand:HI 3 "vpr_register_operand" "Up")] + (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")] VMAXNMAVQ_P_F)) ] "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" @@ -4135,7 +4135,7 @@ (define_insn "mve_vmaxnmvq_p_f<mode>" (set (match_operand:<V_elem> 0 "s_register_operand" "=r") (unspec:<V_elem> [(match_operand:<V_elem> 1 "s_register_operand" "0") (match_operand:MVE_0 2 "s_register_operand" "w") - (match_operand:HI 3 "vpr_register_operand" "Up")] + (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")] VMAXNMVQ_P_F)) ] "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" @@ -4150,7 +4150,7 @@ (define_insn "mve_vminnmaq_m_f<mode>" (set (match_operand:MVE_0 0 "s_register_operand" "=w") (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0") (match_operand:MVE_0 2 "s_register_operand" "w") - (match_operand:HI 3 "vpr_register_operand" "Up")] + (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")] VMINNMAQ_M_F)) ] "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" @@ -4166,7 +4166,7 @@ (define_insn "mve_vminnmavq_p_f<mode>" (set (match_operand:<V_elem> 0 "s_register_operand" "=r") (unspec:<V_elem> [(match_operand:<V_elem> 1 "s_register_operand" "0") (match_operand:MVE_0 2 "s_register_operand" "w") - (match_operand:HI 3 "vpr_register_operand" "Up")] + (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")] VMINNMAVQ_P_F)) ] "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" @@ -4181,7 +4181,7 @@ (define_insn "mve_vminnmvq_p_f<mode>" (set (match_operand:<V_elem> 0 "s_register_operand" "=r") (unspec:<V_elem> [(match_operand:<V_elem> 1 "s_register_operand" "0") (match_operand:MVE_0 2 "s_register_operand" "w") - (match_operand:HI 3 "vpr_register_operand" "Up")] + (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")] VMINNMVQ_P_F)) ] "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" @@ -4229,7 +4229,7 @@ (define_insn "mve_vmlaldavq_p_<supf><mode>" (set (match_operand:DI 0 "s_register_operand" "=r") (unspec:DI [(match_operand:MVE_5 1 "s_register_operand" "w") (match_operand:MVE_5 2 "s_register_operand" "w") - (match_operand:HI 3 "vpr_register_operand" "Up")] + (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")] VMLALDAVQ_P)) ] "TARGET_HAVE_MVE" @@ -4245,7 +4245,7 @@ (define_insn "mve_vmlaldavxq_p_s<mode>" (set (match_operand:DI 0 "s_register_operand" "=r") (unspec:DI [(match_operand:MVE_5 1 "s_register_operand" "w") (match_operand:MVE_5 2 "s_register_operand" "w") - (match_operand:HI 3 "vpr_register_operand" "Up")] + (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")] VMLALDAVXQ_P_S)) ] "TARGET_HAVE_MVE" @@ -4292,7 +4292,7 @@ (define_insn "mve_vmlsldavq_p_s<mode>" (set (match_operand:DI 0 "s_register_operand" "=r") (unspec:DI [(match_operand:MVE_5 1 "s_register_operand" "w") (match_operand:MVE_5 2 "s_register_operand" "w") - (match_operand:HI 3 "vpr_register_operand" "Up")] + (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")] VMLSLDAVQ_P_S)) ] "TARGET_HAVE_MVE" @@ -4308,7 +4308,7 @@ (define_insn "mve_vmlsldavxq_p_s<mode>" (set (match_operand:DI 0 "s_register_operand" "=r") (unspec:DI [(match_operand:MVE_5 1 "s_register_operand" "w") (match_operand:MVE_5 2 "s_register_operand" "w") - (match_operand:HI 3 "vpr_register_operand" "Up")] + (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")] VMLSLDAVXQ_P_S)) ] "TARGET_HAVE_MVE" @@ -4323,7 +4323,7 @@ (define_insn "mve_vmovlbq_m_<supf><mode>" (set (match_operand:<V_double_width> 0 "s_register_operand" "=w") (unspec:<V_double_width> [(match_operand:<V_double_width> 1 "s_register_operand" "0") (match_operand:MVE_3 2 "s_register_operand" "w") - (match_operand:HI 3 "vpr_register_operand" "Up")] + (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")] VMOVLBQ_M)) ] "TARGET_HAVE_MVE" @@ -4338,7 +4338,7 @@ (define_insn "mve_vmovltq_m_<supf><mode>" (set (match_operand:<V_double_width> 0 "s_register_operand" "=w") (unspec:<V_double_width> [(match_operand:<V_double_width> 1 "s_register_operand" "0") (match_operand:MVE_3 2 "s_register_operand" "w") - (match_operand:HI 3 "vpr_register_operand" "Up")] + (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")] VMOVLTQ_M)) ] "TARGET_HAVE_MVE" @@ -4353,7 +4353,7 @@ (define_insn "mve_vmovnbq_m_<supf><mode>" (set (match_operand:<V_narrow_pack> 0 "s_register_operand" "=w") (unspec:<V_narrow_pack> [(match_operand:<V_narrow_pack> 1 "s_register_operand" "0") (match_operand:MVE_5 2 "s_register_operand" "w") - (match_operand:HI 3 "vpr_register_operand" "Up")] + (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")] VMOVNBQ_M)) ] "TARGET_HAVE_MVE" @@ -4369,7 +4369,7 @@ (define_insn "mve_vmovntq_m_<supf><mode>" (set (match_operand:<V_narrow_pack> 0 "s_register_operand" "=w") (unspec:<V_narrow_pack> [(match_operand:<V_narrow_pack> 1 "s_register_operand" "0") (match_operand:MVE_5 2 "s_register_operand" "w") - (match_operand:HI 3 "vpr_register_operand" "Up")] + (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")] VMOVNTQ_M)) ] "TARGET_HAVE_MVE" @@ -4385,7 +4385,7 @@ (define_insn "mve_vmvnq_m_n_<supf><mode>" (set (match_operand:MVE_5 0 "s_register_operand" "=w") (unspec:MVE_5 [(match_operand:MVE_5 1 "s_register_operand" "0") (match_operand:SI 2 "immediate_operand" "i") - (match_operand:HI 3 "vpr_register_operand" "Up")] + (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")] VMVNQ_M_N)) ] "TARGET_HAVE_MVE" @@ -4400,7 +4400,7 @@ (define_insn "mve_vnegq_m_f<mode>" (set (match_operand:MVE_0 0 "s_register_operand" "=w") (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0") (match_operand:MVE_0 2 "s_register_operand" "w") - (match_operand:HI 3 "vpr_register_operand" "Up")] + (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")] VNEGQ_M_F)) ] "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" @@ -4416,7 +4416,7 @@ (define_insn "mve_vorrq_m_n_<supf><mode>" (set (match_operand:MVE_5 0 "s_register_operand" "=w") (unspec:MVE_5 [(match_operand:MVE_5 1 "s_register_operand" "0") (match_operand:SI 2 "immediate_operand" "i") - (match_operand:HI 3 "vpr_register_operand" "Up")] + (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")] VORRQ_M_N)) ] "TARGET_HAVE_MVE" @@ -4447,7 +4447,7 @@ (define_insn "mve_vqmovnbq_m_<supf><mode>" (set (match_operand:<V_narrow_pack> 0 "s_register_operand" "=w") (unspec:<V_narrow_pack> [(match_operand:<V_narrow_pack> 1 "s_register_operand" "0") (match_operand:MVE_5 2 "s_register_operand" "w") - (match_operand:HI 3 "vpr_register_operand" "Up")] + (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")] VQMOVNBQ_M)) ] "TARGET_HAVE_MVE" @@ -4463,7 +4463,7 @@ (define_insn "mve_vqmovntq_m_<supf><mode>" (set (match_operand:<V_narrow_pack> 0 "s_register_operand" "=w") (unspec:<V_narrow_pack> [(match_operand:<V_narrow_pack> 1 "s_register_operand" "0") (match_operand:MVE_5 2 "s_register_operand" "w") - (match_operand:HI 3 "vpr_register_operand" "Up")] + (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")] VQMOVNTQ_M)) ] "TARGET_HAVE_MVE" @@ -4479,7 +4479,7 @@ (define_insn "mve_vqmovunbq_m_s<mode>" (set (match_operand:<V_narrow_pack> 0 "s_register_operand" "=w") (unspec:<V_narrow_pack> [(match_operand:<V_narrow_pack> 1 "s_register_operand" "0") (match_operand:MVE_5 2 "s_register_operand" "w") - (match_operand:HI 3 "vpr_register_operand" "Up")] + (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")] VQMOVUNBQ_M_S)) ] "TARGET_HAVE_MVE" @@ -4495,7 +4495,7 @@ (define_insn "mve_vqmovuntq_m_s<mode>" (set (match_operand:<V_narrow_pack> 0 "s_register_operand" "=w") (unspec:<V_narrow_pack> [(match_operand:<V_narrow_pack> 1 "s_register_operand" "0") (match_operand:MVE_5 2 "s_register_operand" "w") - (match_operand:HI 3 "vpr_register_operand" "Up")] + (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")] VQMOVUNTQ_M_S)) ] "TARGET_HAVE_MVE" @@ -4623,7 +4623,7 @@ (define_insn "mve_vrev32q_m_<supf><mode>" (set (match_operand:MVE_3 0 "s_register_operand" "=w") (unspec:MVE_3 [(match_operand:MVE_3 1 "s_register_operand" "0") (match_operand:MVE_3 2 "s_register_operand" "w") - (match_operand:HI 3 "vpr_register_operand" "Up")] + (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")] VREV32Q_M)) ] "TARGET_HAVE_MVE" @@ -4639,7 +4639,7 @@ (define_insn "mve_vrev64q_m_f<mode>" (set (match_operand:MVE_0 0 "s_register_operand" "=w") (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0") (match_operand:MVE_0 2 "s_register_operand" "w") - (match_operand:HI 3 "vpr_register_operand" "Up")] + (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")] VREV64Q_M_F)) ] "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" @@ -4735,7 +4735,7 @@ (define_insn "mve_vrndaq_m_f<mode>" (set (match_operand:MVE_0 0 "s_register_operand" "=w") (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0") (match_operand:MVE_0 2 "s_register_operand" "w") - (match_operand:HI 3 "vpr_register_operand" "Up")] + (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")] VRNDAQ_M_F)) ] "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" @@ -4751,7 +4751,7 @@ (define_insn "mve_vrndmq_m_f<mode>" (set (match_operand:MVE_0 0 "s_register_operand" "=w") (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0") (match_operand:MVE_0 2 "s_register_operand" "w") - (match_operand:HI 3 "vpr_register_operand" "Up")] + (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")] VRNDMQ_M_F)) ] "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" @@ -4767,7 +4767,7 @@ (define_insn "mve_vrndnq_m_f<mode>" (set (match_operand:MVE_0 0 "s_register_operand" "=w") (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0") (match_operand:MVE_0 2 "s_register_operand" "w") - (match_operand:HI 3 "vpr_register_operand" "Up")] + (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")] VRNDNQ_M_F)) ] "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" @@ -4783,7 +4783,7 @@ (define_insn "mve_vrndpq_m_f<mode>" (set (match_operand:MVE_0 0 "s_register_operand" "=w") (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0") (match_operand:MVE_0 2 "s_register_operand" "w") - (match_operand:HI 3 "vpr_register_operand" "Up")] + (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")] VRNDPQ_M_F)) ] "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" @@ -4799,7 +4799,7 @@ (define_insn "mve_vrndxq_m_f<mode>" (set (match_operand:MVE_0 0 "s_register_operand" "=w") (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0") (match_operand:MVE_0 2 "s_register_operand" "w") - (match_operand:HI 3 "vpr_register_operand" "Up")] + (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")] VRNDXQ_M_F)) ] "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" @@ -4879,7 +4879,7 @@ (define_insn "mve_vcvtmq_m_<supf><mode>" (set (match_operand:MVE_5 0 "s_register_operand" "=w") (unspec:MVE_5 [(match_operand:MVE_5 1 "s_register_operand" "0") (match_operand:<MVE_CNVT> 2 "s_register_operand" "w") - (match_operand:HI 3 "vpr_register_operand" "Up")] + (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")] VCVTMQ_M)) ] "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" @@ -4895,7 +4895,7 @@ (define_insn "mve_vcvtpq_m_<supf><mode>" (set (match_operand:MVE_5 0 "s_register_operand" "=w") (unspec:MVE_5 [(match_operand:MVE_5 1 "s_register_operand" "0") (match_operand:<MVE_CNVT> 2 "s_register_operand" "w") - (match_operand:HI 3 "vpr_register_operand" "Up")] + (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")] VCVTPQ_M)) ] "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" @@ -4911,7 +4911,7 @@ (define_insn "mve_vcvtnq_m_<supf><mode>" (set (match_operand:MVE_5 0 "s_register_operand" "=w") (unspec:MVE_5 [(match_operand:MVE_5 1 "s_register_operand" "0") (match_operand:<MVE_CNVT> 2 "s_register_operand" "w") - (match_operand:HI 3 "vpr_register_operand" "Up")] + (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")] VCVTNQ_M)) ] "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" @@ -4928,7 +4928,7 @@ (define_insn "mve_vcvtq_m_n_from_f_<supf><mode>" (unspec:MVE_5 [(match_operand:MVE_5 1 "s_register_operand" "0") (match_operand:<MVE_CNVT> 2 "s_register_operand" "w") (match_operand:SI 3 "<MVE_pred2>" "<MVE_constraint2>") - (match_operand:HI 4 "vpr_register_operand" "Up")] + (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")] VCVTQ_M_N_FROM_F)) ] "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" @@ -4960,7 +4960,7 @@ (define_insn "mve_vcvtq_m_from_f_<supf><mode>" (set (match_operand:MVE_5 0 "s_register_operand" "=w") (unspec:MVE_5 [(match_operand:MVE_5 1 "s_register_operand" "0") (match_operand:<MVE_CNVT> 2 "s_register_operand" "w") - (match_operand:HI 3 "vpr_register_operand" "Up")] + (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")] VCVTQ_M_FROM_F)) ] "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" @@ -5009,7 +5009,7 @@ (define_insn "mve_vabavq_p_<supf><mode>" (unspec:SI [(match_operand:SI 1 "s_register_operand" "0") (match_operand:MVE_2 2 "s_register_operand" "w") (match_operand:MVE_2 3 "s_register_operand" "w") - (match_operand:HI 4 "vpr_register_operand" "Up")] + (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")] VABAVQ_P)) ] "TARGET_HAVE_MVE" @@ -5026,7 +5026,7 @@ (define_insn "mve_vqshluq_m_n_s<mode>" (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") (match_operand:MVE_2 2 "s_register_operand" "w") (match_operand:SI 3 "mve_imm_7" "Ra") - (match_operand:HI 4 "vpr_register_operand" "Up")] + (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")] VQSHLUQ_M_N_S)) ] "TARGET_HAVE_MVE" @@ -5042,7 +5042,7 @@ (define_insn "mve_vshlq_m_<supf><mode>" (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") (match_operand:MVE_2 2 "s_register_operand" "w") (match_operand:MVE_2 3 "s_register_operand" "w") - (match_operand:HI 4 "vpr_register_operand" "Up")] + (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")] VSHLQ_M)) ] "TARGET_HAVE_MVE" @@ -5058,7 +5058,7 @@ (define_insn "mve_vsriq_m_n_<supf><mode>" (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") (match_operand:MVE_2 2 "s_register_operand" "w") (match_operand:SI 3 "mve_imm_selective_upto_8" "Rg") - (match_operand:HI 4 "vpr_register_operand" "Up")] + (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")] VSRIQ_M_N)) ] "TARGET_HAVE_MVE" @@ -5074,7 +5074,7 @@ (define_insn "mve_vsubq_m_<supf><mode>" (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") (match_operand:MVE_2 2 "s_register_operand" "w") (match_operand:MVE_2 3 "s_register_operand" "w") - (match_operand:HI 4 "vpr_register_operand" "Up")] + (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")] VSUBQ_M)) ] "TARGET_HAVE_MVE" @@ -5090,7 +5090,7 @@ (define_insn "mve_vcvtq_m_n_to_f_<supf><mode>" (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0") (match_operand:<MVE_CNVT> 2 "s_register_operand" "w") (match_operand:SI 3 "<MVE_pred2>" "<MVE_constraint2>") - (match_operand:HI 4 "vpr_register_operand" "Up")] + (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")] VCVTQ_M_N_TO_F)) ] "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" @@ -5106,7 +5106,7 @@ (define_insn "mve_vabdq_m_<supf><mode>" (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") (match_operand:MVE_2 2 "s_register_operand" "w") (match_operand:MVE_2 3 "s_register_operand" "w") - (match_operand:HI 4 "vpr_register_operand" "Up")] + (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")] VABDQ_M)) ] "TARGET_HAVE_MVE" @@ -5123,7 +5123,7 @@ (define_insn "mve_vaddq_m_n_<supf><mode>" (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") (match_operand:MVE_2 2 "s_register_operand" "w") (match_operand:<V_elem> 3 "s_register_operand" "r") - (match_operand:HI 4 "vpr_register_operand" "Up")] + (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")] VADDQ_M_N)) ] "TARGET_HAVE_MVE" @@ -5140,7 +5140,7 @@ (define_insn "mve_vaddq_m_<supf><mode>" (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") (match_operand:MVE_2 2 "s_register_operand" "w") (match_operand:MVE_2 3 "s_register_operand" "w") - (match_operand:HI 4 "vpr_register_operand" "Up")] + (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")] VADDQ_M)) ] "TARGET_HAVE_MVE" @@ -5157,7 +5157,7 @@ (define_insn "mve_vandq_m_<supf><mode>" (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") (match_operand:MVE_2 2 "s_register_operand" "w") (match_operand:MVE_2 3 "s_register_operand" "w") - (match_operand:HI 4 "vpr_register_operand" "Up")] + (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")] VANDQ_M)) ] "TARGET_HAVE_MVE" @@ -5174,7 +5174,7 @@ (define_insn "mve_vbicq_m_<supf><mode>" (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") (match_operand:MVE_2 2 "s_register_operand" "w") (match_operand:MVE_2 3 "s_register_operand" "w") - (match_operand:HI 4 "vpr_register_operand" "Up")] + (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")] VBICQ_M)) ] "TARGET_HAVE_MVE" @@ -5191,7 +5191,7 @@ (define_insn "mve_vbrsrq_m_n_<supf><mode>" (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") (match_operand:MVE_2 2 "s_register_operand" "w") (match_operand:SI 3 "s_register_operand" "r") - (match_operand:HI 4 "vpr_register_operand" "Up")] + (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")] VBRSRQ_M_N)) ] "TARGET_HAVE_MVE" @@ -5208,7 +5208,7 @@ (define_insn "mve_vcaddq_rot270_m_<supf><mode>" (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") (match_operand:MVE_2 2 "s_register_operand" "w") (match_operand:MVE_2 3 "s_register_operand" "w") - (match_operand:HI 4 "vpr_register_operand" "Up")] + (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")] VCADDQ_ROT270_M)) ] "TARGET_HAVE_MVE" @@ -5225,7 +5225,7 @@ (define_insn "mve_vcaddq_rot90_m_<supf><mode>" (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") (match_operand:MVE_2 2 "s_register_operand" "w") (match_operand:MVE_2 3 "s_register_operand" "w") - (match_operand:HI 4 "vpr_register_operand" "Up")] + (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")] VCADDQ_ROT90_M)) ] "TARGET_HAVE_MVE" @@ -5242,7 +5242,7 @@ (define_insn "mve_veorq_m_<supf><mode>" (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") (match_operand:MVE_2 2 "s_register_operand" "w") (match_operand:MVE_2 3 "s_register_operand" "w") - (match_operand:HI 4 "vpr_register_operand" "Up")] + (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")] VEORQ_M)) ] "TARGET_HAVE_MVE" @@ -5259,7 +5259,7 @@ (define_insn "mve_vhaddq_m_n_<supf><mode>" (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") (match_operand:MVE_2 2 "s_register_operand" "w") (match_operand:<V_elem> 3 "s_register_operand" "r") - (match_operand:HI 4 "vpr_register_operand" "Up")] + (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")] VHADDQ_M_N)) ] "TARGET_HAVE_MVE" @@ -5276,7 +5276,7 @@ (define_insn "mve_vhaddq_m_<supf><mode>" (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") (match_operand:MVE_2 2 "s_register_operand" "w") (match_operand:MVE_2 3 "s_register_operand" "w") - (match_operand:HI 4 "vpr_register_operand" "Up")] + (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")] VHADDQ_M)) ] "TARGET_HAVE_MVE" @@ -5293,7 +5293,7 @@ (define_insn "mve_vhsubq_m_n_<supf><mode>" (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") (match_operand:MVE_2 2 "s_register_operand" "w") (match_operand:<V_elem> 3 "s_register_operand" "r") - (match_operand:HI 4 "vpr_register_operand" "Up")] + (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")] VHSUBQ_M_N)) ] "TARGET_HAVE_MVE" @@ -5310,7 +5310,7 @@ (define_insn "mve_vhsubq_m_<supf><mode>" (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") (match_operand:MVE_2 2 "s_register_operand" "w") (match_operand:MVE_2 3 "s_register_operand" "w") - (match_operand:HI 4 "vpr_register_operand" "Up")] + (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")] VHSUBQ_M)) ] "TARGET_HAVE_MVE" @@ -5327,7 +5327,7 @@ (define_insn "mve_vmaxq_m_<supf><mode>" (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") (match_operand:MVE_2 2 "s_register_operand" "w") (match_operand:MVE_2 3 "s_register_operand" "w") - (match_operand:HI 4 "vpr_register_operand" "Up")] + (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")] VMAXQ_M)) ] "TARGET_HAVE_MVE" @@ -5344,7 +5344,7 @@ (define_insn "mve_vminq_m_<supf><mode>" (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") (match_operand:MVE_2 2 "s_register_operand" "w") (match_operand:MVE_2 3 "s_register_operand" "w") - (match_operand:HI 4 "vpr_register_operand" "Up")] + (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")] VMINQ_M)) ] "TARGET_HAVE_MVE" @@ -5361,7 +5361,7 @@ (define_insn "mve_vmladavaq_p_<supf><mode>" (unspec:SI [(match_operand:SI 1 "s_register_operand" "0") (match_operand:MVE_2 2 "s_register_operand" "w") (match_operand:MVE_2 3 "s_register_operand" "w") - (match_operand:HI 4 "vpr_register_operand" "Up")] + (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")] VMLADAVAQ_P)) ] "TARGET_HAVE_MVE" @@ -5378,7 +5378,7 @@ (define_insn "mve_vmlaq_m_n_<supf><mode>" (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") (match_operand:MVE_2 2 "s_register_operand" "w") (match_operand:<V_elem> 3 "s_register_operand" "r") - (match_operand:HI 4 "vpr_register_operand" "Up")] + (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")] VMLAQ_M_N)) ] "TARGET_HAVE_MVE" @@ -5395,7 +5395,7 @@ (define_insn "mve_vmlasq_m_n_<supf><mode>" (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") (match_operand:MVE_2 2 "s_register_operand" "w") (match_operand:<V_elem> 3 "s_register_operand" "r") - (match_operand:HI 4 "vpr_register_operand" "Up")] + (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")] VMLASQ_M_N)) ] "TARGET_HAVE_MVE" @@ -5412,7 +5412,7 @@ (define_insn "mve_vmulhq_m_<supf><mode>" (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") (match_operand:MVE_2 2 "s_register_operand" "w") (match_operand:MVE_2 3 "s_register_operand" "w") - (match_operand:HI 4 "vpr_register_operand" "Up")] + (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")] VMULHQ_M)) ] "TARGET_HAVE_MVE" @@ -5429,7 +5429,7 @@ (define_insn "mve_vmullbq_int_m_<supf><mode>" (unspec:<V_double_width> [(match_operand:<V_double_width> 1 "s_register_operand" "0") (match_operand:MVE_2 2 "s_register_operand" "w") (match_operand:MVE_2 3 "s_register_operand" "w") - (match_operand:HI 4 "vpr_register_operand" "Up")] + (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")] VMULLBQ_INT_M)) ] "TARGET_HAVE_MVE" @@ -5446,7 +5446,7 @@ (define_insn "mve_vmulltq_int_m_<supf><mode>" (unspec:<V_double_width> [(match_operand:<V_double_width> 1 "s_register_operand" "0") (match_operand:MVE_2 2 "s_register_operand" "w") (match_operand:MVE_2 3 "s_register_operand" "w") - (match_operand:HI 4 "vpr_register_operand" "Up")] + (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")] VMULLTQ_INT_M)) ] "TARGET_HAVE_MVE" @@ -5463,7 +5463,7 @@ (define_insn "mve_vmulq_m_n_<supf><mode>" (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") (match_operand:MVE_2 2 "s_register_operand" "w") (match_operand:<V_elem> 3 "s_register_operand" "r") - (match_operand:HI 4 "vpr_register_operand" "Up")] + (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")] VMULQ_M_N)) ] "TARGET_HAVE_MVE" @@ -5480,7 +5480,7 @@ (define_insn "mve_vmulq_m_<supf><mode>" (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") (match_operand:MVE_2 2 "s_register_operand" "w") (match_operand:MVE_2 3 "s_register_operand" "w") - (match_operand:HI 4 "vpr_register_operand" "Up")] + (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")] VMULQ_M)) ] "TARGET_HAVE_MVE" @@ -5497,7 +5497,7 @@ (define_insn "mve_vornq_m_<supf><mode>" (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") (match_operand:MVE_2 2 "s_register_operand" "w") (match_operand:MVE_2 3 "s_register_operand" "w") - (match_operand:HI 4 "vpr_register_operand" "Up")] + (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")] VORNQ_M)) ] "TARGET_HAVE_MVE" @@ -5514,7 +5514,7 @@ (define_insn "mve_vorrq_m_<supf><mode>" (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") (match_operand:MVE_2 2 "s_register_operand" "w") (match_operand:MVE_2 3 "s_register_operand" "w") - (match_operand:HI 4 "vpr_register_operand" "Up")] + (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")] VORRQ_M)) ] "TARGET_HAVE_MVE" @@ -5531,7 +5531,7 @@ (define_insn "mve_vqaddq_m_n_<supf><mode>" (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") (match_operand:MVE_2 2 "s_register_operand" "w") (match_operand:<V_elem> 3 "s_register_operand" "r") - (match_operand:HI 4 "vpr_register_operand" "Up")] + (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")] VQADDQ_M_N)) ] "TARGET_HAVE_MVE" @@ -5548,7 +5548,7 @@ (define_insn "mve_vqaddq_m_<supf><mode>" (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") (match_operand:MVE_2 2 "s_register_operand" "w") (match_operand:MVE_2 3 "s_register_operand" "w") - (match_operand:HI 4 "vpr_register_operand" "Up")] + (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")] VQADDQ_M)) ] "TARGET_HAVE_MVE" @@ -5565,7 +5565,7 @@ (define_insn "mve_vqdmlahq_m_n_s<mode>" (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") (match_operand:MVE_2 2 "s_register_operand" "w") (match_operand:<V_elem> 3 "s_register_operand" "r") - (match_operand:HI 4 "vpr_register_operand" "Up")] + (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")] VQDMLAHQ_M_N_S)) ] "TARGET_HAVE_MVE" @@ -5582,7 +5582,7 @@ (define_insn "mve_vqdmlashq_m_n_s<mode>" (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") (match_operand:MVE_2 2 "s_register_operand" "w") (match_operand:<V_elem> 3 "s_register_operand" "r") - (match_operand:HI 4 "vpr_register_operand" "Up")] + (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")] VQDMLASHQ_M_N_S)) ] "TARGET_HAVE_MVE" @@ -5599,7 +5599,7 @@ (define_insn "mve_vqrdmlahq_m_n_s<mode>" (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") (match_operand:MVE_2 2 "s_register_operand" "w") (match_operand:<V_elem> 3 "s_register_operand" "r") - (match_operand:HI 4 "vpr_register_operand" "Up")] + (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")] VQRDMLAHQ_M_N_S)) ] "TARGET_HAVE_MVE" @@ -5616,7 +5616,7 @@ (define_insn "mve_vqrdmlashq_m_n_s<mode>" (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") (match_operand:MVE_2 2 "s_register_operand" "w") (match_operand:<V_elem> 3 "s_register_operand" "r") - (match_operand:HI 4 "vpr_register_operand" "Up")] + (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")] VQRDMLASHQ_M_N_S)) ] "TARGET_HAVE_MVE" @@ -5633,7 +5633,7 @@ (define_insn "mve_vqrshlq_m_<supf><mode>" (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") (match_operand:MVE_2 2 "s_register_operand" "w") (match_operand:MVE_2 3 "s_register_operand" "w") - (match_operand:HI 4 "vpr_register_operand" "Up")] + (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")] VQRSHLQ_M)) ] "TARGET_HAVE_MVE" @@ -5650,7 +5650,7 @@ (define_insn "mve_vqshlq_m_n_<supf><mode>" (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") (match_operand:MVE_2 2 "s_register_operand" "w") (match_operand:SI 3 "immediate_operand" "i") - (match_operand:HI 4 "vpr_register_operand" "Up")] + (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")] VQSHLQ_M_N)) ] "TARGET_HAVE_MVE" @@ -5667,7 +5667,7 @@ (define_insn "mve_vqshlq_m_<supf><mode>" (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") (match_operand:MVE_2 2 "s_register_operand" "w") (match_operand:MVE_2 3 "s_register_operand" "w") - (match_operand:HI 4 "vpr_register_operand" "Up")] + (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")] VQSHLQ_M)) ] "TARGET_HAVE_MVE" @@ -5684,7 +5684,7 @@ (define_insn "mve_vqsubq_m_n_<supf><mode>" (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") (match_operand:MVE_2 2 "s_register_operand" "w") (match_operand:<V_elem> 3 "s_register_operand" "r") - (match_operand:HI 4 "vpr_register_operand" "Up")] + (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")] VQSUBQ_M_N)) ] "TARGET_HAVE_MVE" @@ -5701,7 +5701,7 @@ (define_insn "mve_vqsubq_m_<supf><mode>" (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") (match_operand:MVE_2 2 "s_register_operand" "w") (match_operand:MVE_2 3 "s_register_operand" "w") - (match_operand:HI 4 "vpr_register_operand" "Up")] + (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")] VQSUBQ_M)) ] "TARGET_HAVE_MVE" @@ -5718,7 +5718,7 @@ (define_insn "mve_vrhaddq_m_<supf><mode>" (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") (match_operand:MVE_2 2 "s_register_operand" "w") (match_operand:MVE_2 3 "s_register_operand" "w") - (match_operand:HI 4 "vpr_register_operand" "Up")] + (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")] VRHADDQ_M)) ] "TARGET_HAVE_MVE" @@ -5735,7 +5735,7 @@ (define_insn "mve_vrmulhq_m_<supf><mode>" (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") (match_operand:MVE_2 2 "s_register_operand" "w") (match_operand:MVE_2 3 "s_register_operand" "w") - (match_operand:HI 4 "vpr_register_operand" "Up")] + (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")] VRMULHQ_M)) ] "TARGET_HAVE_MVE" @@ -5752,7 +5752,7 @@ (define_insn "mve_vrshlq_m_<supf><mode>" (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") (match_operand:MVE_2 2 "s_register_operand" "w") (match_operand:MVE_2 3 "s_register_operand" "w") - (match_operand:HI 4 "vpr_register_operand" "Up")] + (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")] VRSHLQ_M)) ] "TARGET_HAVE_MVE" @@ -5769,7 +5769,7 @@ (define_insn "mve_vrshrq_m_n_<supf><mode>" (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") (match_operand:MVE_2 2 "s_register_operand" "w") (match_operand:SI 3 "<MVE_pred2>" "<MVE_constraint2>") - (match_operand:HI 4 "vpr_register_operand" "Up")] + (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")] VRSHRQ_M_N)) ] "TARGET_HAVE_MVE" @@ -5786,7 +5786,7 @@ (define_insn "mve_vshlq_m_n_<supf><mode>" (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") (match_operand:MVE_2 2 "s_register_operand" "w") (match_operand:SI 3 "immediate_operand" "i") - (match_operand:HI 4 "vpr_register_operand" "Up")] + (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")] VSHLQ_M_N)) ] "TARGET_HAVE_MVE" @@ -5803,7 +5803,7 @@ (define_insn "mve_vshrq_m_n_<supf><mode>" (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") (match_operand:MVE_2 2 "s_register_operand" "w") (match_operand:SI 3 "<MVE_pred2>" "<MVE_constraint2>") - (match_operand:HI 4 "vpr_register_operand" "Up")] + (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")] VSHRQ_M_N)) ] "TARGET_HAVE_MVE" @@ -5820,7 +5820,7 @@ (define_insn "mve_vsliq_m_n_<supf><mode>" (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") (match_operand:MVE_2 2 "s_register_operand" "w") (match_operand:SI 3 "<MVE_pred>" "<MVE_constraint>") - (match_operand:HI 4 "vpr_register_operand" "Up")] + (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")] VSLIQ_M_N)) ] "TARGET_HAVE_MVE" @@ -5837,7 +5837,7 @@ (define_insn "mve_vsubq_m_n_<supf><mode>" (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") (match_operand:MVE_2 2 "s_register_operand" "w") (match_operand:<V_elem> 3 "s_register_operand" "r") - (match_operand:HI 4 "vpr_register_operand" "Up")] + (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")] VSUBQ_M_N)) ] "TARGET_HAVE_MVE" @@ -5854,7 +5854,7 @@ (define_insn "mve_vhcaddq_rot270_m_s<mode>" (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") (match_operand:MVE_2 2 "s_register_operand" "w") (match_operand:MVE_2 3 "s_register_operand" "w") - (match_operand:HI 4 "vpr_register_operand" "Up")] + (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")] VHCADDQ_ROT270_M_S)) ] "TARGET_HAVE_MVE" @@ -5871,7 +5871,7 @@ (define_insn "mve_vhcaddq_rot90_m_s<mode>" (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") (match_operand:MVE_2 2 "s_register_operand" "w") (match_operand:MVE_2 3 "s_register_operand" "w") - (match_operand:HI 4 "vpr_register_operand" "Up")] + (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")] VHCADDQ_ROT90_M_S)) ] "TARGET_HAVE_MVE" @@ -5888,7 +5888,7 @@ (define_insn "mve_vmladavaxq_p_s<mode>" (unspec:SI [(match_operand:SI 1 "s_register_operand" "0") (match_operand:MVE_2 2 "s_register_operand" "w") (match_operand:MVE_2 3 "s_register_operand" "w") - (match_operand:HI 4 "vpr_register_operand" "Up")] + (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")] VMLADAVAXQ_P_S)) ] "TARGET_HAVE_MVE" @@ -5905,7 +5905,7 @@ (define_insn "mve_vmlsdavaq_p_s<mode>" (unspec:SI [(match_operand:SI 1 "s_register_operand" "0") (match_operand:MVE_2 2 "s_register_operand" "w") (match_operand:MVE_2 3 "s_register_operand" "w") - (match_operand:HI 4 "vpr_register_operand" "Up")] + (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")] VMLSDAVAQ_P_S)) ] "TARGET_HAVE_MVE" @@ -5922,7 +5922,7 @@ (define_insn "mve_vmlsdavaxq_p_s<mode>" (unspec:SI [(match_operand:SI 1 "s_register_operand" "0") (match_operand:MVE_2 2 "s_register_operand" "w") (match_operand:MVE_2 3 "s_register_operand" "w") - (match_operand:HI 4 "vpr_register_operand" "Up")] + (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")] VMLSDAVAXQ_P_S)) ] "TARGET_HAVE_MVE" @@ -5939,7 +5939,7 @@ (define_insn "mve_vqdmladhq_m_s<mode>" (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") (match_operand:MVE_2 2 "s_register_operand" "w") (match_operand:MVE_2 3 "s_register_operand" "w") - (match_operand:HI 4 "vpr_register_operand" "Up")] + (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")] VQDMLADHQ_M_S)) ] "TARGET_HAVE_MVE" @@ -5956,7 +5956,7 @@ (define_insn "mve_vqdmladhxq_m_s<mode>" (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") (match_operand:MVE_2 2 "s_register_operand" "w") (match_operand:MVE_2 3 "s_register_operand" "w") - (match_operand:HI 4 "vpr_register_operand" "Up")] + (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")] VQDMLADHXQ_M_S)) ] "TARGET_HAVE_MVE" @@ -5973,7 +5973,7 @@ (define_insn "mve_vqdmlsdhq_m_s<mode>" (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") (match_operand:MVE_2 2 "s_register_operand" "w") (match_operand:MVE_2 3 "s_register_operand" "w") - (match_operand:HI 4 "vpr_register_operand" "Up")] + (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")] VQDMLSDHQ_M_S)) ] "TARGET_HAVE_MVE" @@ -5990,7 +5990,7 @@ (define_insn "mve_vqdmlsdhxq_m_s<mode>" (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") (match_operand:MVE_2 2 "s_register_operand" "w") (match_operand:MVE_2 3 "s_register_operand" "w") - (match_operand:HI 4 "vpr_register_operand" "Up")] + (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")] VQDMLSDHXQ_M_S)) ] "TARGET_HAVE_MVE" @@ -6007,7 +6007,7 @@ (define_insn "mve_vqdmulhq_m_n_s<mode>" (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") (match_operand:MVE_2 2 "s_register_operand" "w") (match_operand:<V_elem> 3 "s_register_operand" "r") - (match_operand:HI 4 "vpr_register_operand" "Up")] + (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")] VQDMULHQ_M_N_S)) ] "TARGET_HAVE_MVE" @@ -6024,7 +6024,7 @@ (define_insn "mve_vqdmulhq_m_s<mode>" (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") (match_operand:MVE_2 2 "s_register_operand" "w") (match_operand:MVE_2 3 "s_register_operand" "w") - (match_operand:HI 4 "vpr_register_operand" "Up")] + (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")] VQDMULHQ_M_S)) ] "TARGET_HAVE_MVE" @@ -6041,7 +6041,7 @@ (define_insn "mve_vqrdmladhq_m_s<mode>" (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") (match_operand:MVE_2 2 "s_register_operand" "w") (match_operand:MVE_2 3 "s_register_operand" "w") - (match_operand:HI 4 "vpr_register_operand" "Up")] + (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")] VQRDMLADHQ_M_S)) ] "TARGET_HAVE_MVE" @@ -6058,7 +6058,7 @@ (define_insn "mve_vqrdmladhxq_m_s<mode>" (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") (match_operand:MVE_2 2 "s_register_operand" "w") (match_operand:MVE_2 3 "s_register_operand" "w") - (match_operand:HI 4 "vpr_register_operand" "Up")] + (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")] VQRDMLADHXQ_M_S)) ] "TARGET_HAVE_MVE" @@ -6075,7 +6075,7 @@ (define_insn "mve_vqrdmlsdhq_m_s<mode>" (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") (match_operand:MVE_2 2 "s_register_operand" "w") (match_operand:MVE_2 3 "s_register_operand" "w") - (match_operand:HI 4 "vpr_register_operand" "Up")] + (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")] VQRDMLSDHQ_M_S)) ] "TARGET_HAVE_MVE" @@ -6092,7 +6092,7 @@ (define_insn "mve_vqrdmlsdhxq_m_s<mode>" (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") (match_operand:MVE_2 2 "s_register_operand" "w") (match_operand:MVE_2 3 "s_register_operand" "w") - (match_operand:HI 4 "vpr_register_operand" "Up")] + (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")] VQRDMLSDHXQ_M_S)) ] "TARGET_HAVE_MVE" @@ -6109,7 +6109,7 @@ (define_insn "mve_vqrdmulhq_m_n_s<mode>" (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") (match_operand:MVE_2 2 "s_register_operand" "w") (match_operand:<V_elem> 3 "s_register_operand" "r") - (match_operand:HI 4 "vpr_register_operand" "Up")] + (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")] VQRDMULHQ_M_N_S)) ] "TARGET_HAVE_MVE" @@ -6126,7 +6126,7 @@ (define_insn "mve_vqrdmulhq_m_s<mode>" (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") (match_operand:MVE_2 2 "s_register_operand" "w") (match_operand:MVE_2 3 "s_register_operand" "w") - (match_operand:HI 4 "vpr_register_operand" "Up")] + (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")] VQRDMULHQ_M_S)) ] "TARGET_HAVE_MVE" @@ -6143,7 +6143,7 @@ (define_insn "mve_vmlaldavaq_p_<supf><mode>" (unspec:DI [(match_operand:DI 1 "s_register_operand" "0") (match_operand:MVE_5 2 "s_register_operand" "w") (match_operand:MVE_5 3 "s_register_operand" "w") - (match_operand:HI 4 "vpr_register_operand" "Up")] + (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")] VMLALDAVAQ_P)) ] "TARGET_HAVE_MVE" @@ -6160,7 +6160,7 @@ (define_insn "mve_vmlaldavaxq_p_<supf><mode>" (unspec:DI [(match_operand:DI 1 "s_register_operand" "0") (match_operand:MVE_5 2 "s_register_operand" "w") (match_operand:MVE_5 3 "s_register_operand" "w") - (match_operand:HI 4 "vpr_register_operand" "Up")] + (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")] VMLALDAVAXQ_P)) ] "TARGET_HAVE_MVE" @@ -6177,7 +6177,7 @@ (define_insn "mve_vqrshrnbq_m_n_<supf><mode>" (unspec:<V_narrow_pack> [(match_operand:<V_narrow_pack> 1 "s_register_operand" "0") (match_operand:MVE_5 2 "s_register_operand" "w") (match_operand:SI 3 "mve_imm_8" "Rb") - (match_operand:HI 4 "vpr_register_operand" "Up")] + (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")] VQRSHRNBQ_M_N)) ] "TARGET_HAVE_MVE" @@ -6194,7 +6194,7 @@ (define_insn "mve_vqrshrntq_m_n_<supf><mode>" (unspec:<V_narrow_pack> [(match_operand:<V_narrow_pack> 1 "s_register_operand" "0") (match_operand:MVE_5 2 "s_register_operand" "w") (match_operand:SI 3 "mve_imm_8" "Rb") - (match_operand:HI 4 "vpr_register_operand" "Up")] + (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")] VQRSHRNTQ_M_N)) ] "TARGET_HAVE_MVE" @@ -6211,7 +6211,7 @@ (define_insn "mve_vqshrnbq_m_n_<supf><mode>" (unspec:<V_narrow_pack> [(match_operand:<V_narrow_pack> 1 "s_register_operand" "0") (match_operand:MVE_5 2 "s_register_operand" "w") (match_operand:SI 3 "<MVE_pred3>" "<MVE_constraint3>") - (match_operand:HI 4 "vpr_register_operand" "Up")] + (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")] VQSHRNBQ_M_N)) ] "TARGET_HAVE_MVE" @@ -6228,7 +6228,7 @@ (define_insn "mve_vqshrntq_m_n_<supf><mode>" (unspec:<V_narrow_pack> [(match_operand:<V_narrow_pack> 1 "s_register_operand" "0") (match_operand:MVE_5 2 "s_register_operand" "w") (match_operand:SI 3 "<MVE_pred3>" "<MVE_constraint3>") - (match_operand:HI 4 "vpr_register_operand" "Up")] + (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")] VQSHRNTQ_M_N)) ] "TARGET_HAVE_MVE" @@ -6262,7 +6262,7 @@ (define_insn "mve_vrshrnbq_m_n_<supf><mode>" (unspec:<V_narrow_pack> [(match_operand:<V_narrow_pack> 1 "s_register_operand" "0") (match_operand:MVE_5 2 "s_register_operand" "w") (match_operand:SI 3 "mve_imm_8" "Rb") - (match_operand:HI 4 "vpr_register_operand" "Up")] + (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")] VRSHRNBQ_M_N)) ] "TARGET_HAVE_MVE" @@ -6279,7 +6279,7 @@ (define_insn "mve_vrshrntq_m_n_<supf><mode>" (unspec:<V_narrow_pack> [(match_operand:<V_narrow_pack> 1 "s_register_operand" "0") (match_operand:MVE_5 2 "s_register_operand" "w") (match_operand:SI 3 "mve_imm_8" "Rb") - (match_operand:HI 4 "vpr_register_operand" "Up")] + (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")] VRSHRNTQ_M_N)) ] "TARGET_HAVE_MVE" @@ -6296,7 +6296,7 @@ (define_insn "mve_vshllbq_m_n_<supf><mode>" (unspec:<V_double_width> [(match_operand:<V_double_width> 1 "s_register_operand" "0") (match_operand:MVE_3 2 "s_register_operand" "w") (match_operand:SI 3 "immediate_operand" "i") - (match_operand:HI 4 "vpr_register_operand" "Up")] + (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")] VSHLLBQ_M_N)) ] "TARGET_HAVE_MVE" @@ -6313,7 +6313,7 @@ (define_insn "mve_vshlltq_m_n_<supf><mode>" (unspec:<V_double_width> [(match_operand:<V_double_width> 1 "s_register_operand" "0") (match_operand:MVE_3 2 "s_register_operand" "w") (match_operand:SI 3 "immediate_operand" "i") - (match_operand:HI 4 "vpr_register_operand" "Up")] + (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")] VSHLLTQ_M_N)) ] "TARGET_HAVE_MVE" @@ -6330,7 +6330,7 @@ (define_insn "mve_vshrnbq_m_n_<supf><mode>" (unspec:<V_narrow_pack> [(match_operand:<V_narrow_pack> 1 "s_register_operand" "0") (match_operand:MVE_5 2 "s_register_operand" "w") (match_operand:SI 3 "<MVE_pred3>" "<MVE_constraint3>") - (match_operand:HI 4 "vpr_register_operand" "Up")] + (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")] VSHRNBQ_M_N)) ] "TARGET_HAVE_MVE" @@ -6347,7 +6347,7 @@ (define_insn "mve_vshrntq_m_n_<supf><mode>" (unspec:<V_narrow_pack> [(match_operand:<V_narrow_pack> 1 "s_register_operand" "0") (match_operand:MVE_5 2 "s_register_operand" "w") (match_operand:SI 3 "<MVE_pred3>" "<MVE_constraint3>") - (match_operand:HI 4 "vpr_register_operand" "Up")] + (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")] VSHRNTQ_M_N)) ] "TARGET_HAVE_MVE" @@ -6364,7 +6364,7 @@ (define_insn "mve_vmlsldavaq_p_s<mode>" (unspec:DI [(match_operand:DI 1 "s_register_operand" "0") (match_operand:MVE_5 2 "s_register_operand" "w") (match_operand:MVE_5 3 "s_register_operand" "w") - (match_operand:HI 4 "vpr_register_operand" "Up")] + (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")] VMLSLDAVAQ_P_S)) ] "TARGET_HAVE_MVE" @@ -6381,7 +6381,7 @@ (define_insn "mve_vmlsldavaxq_p_s<mode>" (unspec:DI [(match_operand:DI 1 "s_register_operand" "0") (match_operand:MVE_5 2 "s_register_operand" "w") (match_operand:MVE_5 3 "s_register_operand" "w") - (match_operand:HI 4 "vpr_register_operand" "Up")] + (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")] VMLSLDAVAXQ_P_S)) ] "TARGET_HAVE_MVE" @@ -6398,7 +6398,7 @@ (define_insn "mve_vmullbq_poly_m_p<mode>" (unspec:<V_double_width> [(match_operand:<V_double_width> 1 "s_register_operand" "0") (match_operand:MVE_3 2 "s_register_operand" "w") (match_operand:MVE_3 3 "s_register_operand" "w") - (match_operand:HI 4 "vpr_register_operand" "Up")] + (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")] VMULLBQ_POLY_M_P)) ] "TARGET_HAVE_MVE" @@ -6415,7 +6415,7 @@ (define_insn "mve_vmulltq_poly_m_p<mode>" (unspec:<V_double_width> [(match_operand:<V_double_width> 1 "s_register_operand" "0") (match_operand:MVE_3 2 "s_register_operand" "w") (match_operand:MVE_3 3 "s_register_operand" "w") - (match_operand:HI 4 "vpr_register_operand" "Up")] + (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")] VMULLTQ_POLY_M_P)) ] "TARGET_HAVE_MVE" @@ -6432,7 +6432,7 @@ (define_insn "mve_vqdmullbq_m_n_s<mode>" (unspec:<V_double_width> [(match_operand:<V_double_width> 1 "s_register_operand" "0") (match_operand:MVE_5 2 "s_register_operand" "w") (match_operand:<V_elem> 3 "s_register_operand" "r") - (match_operand:HI 4 "vpr_register_operand" "Up")] + (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")] VQDMULLBQ_M_N_S)) ] "TARGET_HAVE_MVE" @@ -6449,7 +6449,7 @@ (define_insn "mve_vqdmullbq_m_s<mode>" (unspec:<V_double_width> [(match_operand:<V_double_width> 1 "s_register_operand" "0") (match_operand:MVE_5 2 "s_register_operand" "w") (match_operand:MVE_5 3 "s_register_operand" "w") - (match_operand:HI 4 "vpr_register_operand" "Up")] + (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")] VQDMULLBQ_M_S)) ] "TARGET_HAVE_MVE" @@ -6466,7 +6466,7 @@ (define_insn "mve_vqdmulltq_m_n_s<mode>" (unspec:<V_double_width> [(match_operand:<V_double_width> 1 "s_register_operand" "0") (match_operand:MVE_5 2 "s_register_operand" "w") (match_operand:<V_elem> 3 "s_register_operand" "r") - (match_operand:HI 4 "vpr_register_operand" "Up")] + (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")] VQDMULLTQ_M_N_S)) ] "TARGET_HAVE_MVE" @@ -6483,7 +6483,7 @@ (define_insn "mve_vqdmulltq_m_s<mode>" (unspec:<V_double_width> [(match_operand:<V_double_width> 1 "s_register_operand" "0") (match_operand:MVE_5 2 "s_register_operand" "w") (match_operand:MVE_5 3 "s_register_operand" "w") - (match_operand:HI 4 "vpr_register_operand" "Up")] + (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")] VQDMULLTQ_M_S)) ] "TARGET_HAVE_MVE" @@ -6500,7 +6500,7 @@ (define_insn "mve_vqrshrunbq_m_n_s<mode>" (unspec:<V_narrow_pack> [(match_operand:<V_narrow_pack> 1 "s_register_operand" "0") (match_operand:MVE_5 2 "s_register_operand" "w") (match_operand:SI 3 "mve_imm_8" "Rb") - (match_operand:HI 4 "vpr_register_operand" "Up")] + (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")] VQRSHRUNBQ_M_N_S)) ] "TARGET_HAVE_MVE" @@ -6517,7 +6517,7 @@ (define_insn "mve_vqrshruntq_m_n_s<mode>" (unspec:<V_narrow_pack> [(match_operand:<V_narrow_pack> 1 "s_register_operand" "0") (match_operand:MVE_5 2 "s_register_operand" "w") (match_operand:SI 3 "<MVE_pred3>" "<MVE_constraint3>") - (match_operand:HI 4 "vpr_register_operand" "Up")] + (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")] VQRSHRUNTQ_M_N_S)) ] "TARGET_HAVE_MVE" @@ -6534,7 +6534,7 @@ (define_insn "mve_vqshrunbq_m_n_s<mode>" (unspec:<V_narrow_pack> [(match_operand:<V_narrow_pack> 1 "s_register_operand" "0") (match_operand:MVE_5 2 "s_register_operand" "w") (match_operand:SI 3 "<MVE_pred3>" "<MVE_constraint3>") - (match_operand:HI 4 "vpr_register_operand" "Up")] + (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")] VQSHRUNBQ_M_N_S)) ] "TARGET_HAVE_MVE" @@ -6551,7 +6551,7 @@ (define_insn "mve_vqshruntq_m_n_s<mode>" (unspec:<V_narrow_pack> [(match_operand:<V_narrow_pack> 1 "s_register_operand" "0") (match_operand:MVE_5 2 "s_register_operand" "w") (match_operand:SI 3 "<MVE_pred3>" "<MVE_constraint3>") - (match_operand:HI 4 "vpr_register_operand" "Up")] + (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")] VQSHRUNTQ_M_N_S)) ] "TARGET_HAVE_MVE" @@ -6635,7 +6635,7 @@ (define_insn "mve_vabdq_m_f<mode>" (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0") (match_operand:MVE_0 2 "s_register_operand" "w") (match_operand:MVE_0 3 "s_register_operand" "w") - (match_operand:HI 4 "vpr_register_operand" "Up")] + (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")] VABDQ_M_F)) ] "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" @@ -6652,7 +6652,7 @@ (define_insn "mve_vaddq_m_f<mode>" (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0") (match_operand:MVE_0 2 "s_register_operand" "w") (match_operand:MVE_0 3 "s_register_operand" "w") - (match_operand:HI 4 "vpr_register_operand" "Up")] + (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")] VADDQ_M_F)) ] "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" @@ -6669,7 +6669,7 @@ (define_insn "mve_vaddq_m_n_f<mode>" (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0") (match_operand:MVE_0 2 "s_register_operand" "w") (match_operand:<V_elem> 3 "s_register_operand" "r") - (match_operand:HI 4 "vpr_register_operand" "Up")] + (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")] VADDQ_M_N_F)) ] "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" @@ -6686,7 +6686,7 @@ (define_insn "mve_vandq_m_f<mode>" (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0") (match_operand:MVE_0 2 "s_register_operand" "w") (match_operand:MVE_0 3 "s_register_operand" "w") - (match_operand:HI 4 "vpr_register_operand" "Up")] + (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")] VANDQ_M_F)) ] "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" @@ -6703,7 +6703,7 @@ (define_insn "mve_vbicq_m_f<mode>" (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0") (match_operand:MVE_0 2 "s_register_operand" "w") (match_operand:MVE_0 3 "s_register_operand" "w") - (match_operand:HI 4 "vpr_register_operand" "Up")] + (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")] VBICQ_M_F)) ] "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" @@ -6720,7 +6720,7 @@ (define_insn "mve_vbrsrq_m_n_f<mode>" (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0") (match_operand:MVE_0 2 "s_register_operand" "w") (match_operand:SI 3 "s_register_operand" "r") - (match_operand:HI 4 "vpr_register_operand" "Up")] + (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")] VBRSRQ_M_N_F)) ] "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" @@ -6737,7 +6737,7 @@ (define_insn "mve_vcaddq_rot270_m_f<mode>" (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0") (match_operand:MVE_0 2 "s_register_operand" "w") (match_operand:MVE_0 3 "s_register_operand" "w") - (match_operand:HI 4 "vpr_register_operand" "Up")] + (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")] VCADDQ_ROT270_M_F)) ] "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" @@ -6754,7 +6754,7 @@ (define_insn "mve_vcaddq_rot90_m_f<mode>" (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0") (match_operand:MVE_0 2 "s_register_operand" "w") (match_operand:MVE_0 3 "s_register_operand" "w") - (match_operand:HI 4 "vpr_register_operand" "Up")] + (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")] VCADDQ_ROT90_M_F)) ] "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" @@ -6771,7 +6771,7 @@ (define_insn "mve_vcmlaq_m_f<mode>" (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0") (match_operand:MVE_0 2 "s_register_operand" "w") (match_operand:MVE_0 3 "s_register_operand" "w") - (match_operand:HI 4 "vpr_register_operand" "Up")] + (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")] VCMLAQ_M_F)) ] "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" @@ -6788,7 +6788,7 @@ (define_insn "mve_vcmlaq_rot180_m_f<mode>" (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0") (match_operand:MVE_0 2 "s_register_operand" "w") (match_operand:MVE_0 3 "s_register_operand" "w") - (match_operand:HI 4 "vpr_register_operand" "Up")] + (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")] VCMLAQ_ROT180_M_F)) ] "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" @@ -6805,7 +6805,7 @@ (define_insn "mve_vcmlaq_rot270_m_f<mode>" (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0") (match_operand:MVE_0 2 "s_register_operand" "w") (match_operand:MVE_0 3 "s_register_operand" "w") - (match_operand:HI 4 "vpr_register_operand" "Up")] + (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")] VCMLAQ_ROT270_M_F)) ] "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" @@ -6822,7 +6822,7 @@ (define_insn "mve_vcmlaq_rot90_m_f<mode>" (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0") (match_operand:MVE_0 2 "s_register_operand" "w") (match_operand:MVE_0 3 "s_register_operand" "w") - (match_operand:HI 4 "vpr_register_operand" "Up")] + (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")] VCMLAQ_ROT90_M_F)) ] "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" @@ -6839,7 +6839,7 @@ (define_insn "mve_vcmulq_m_f<mode>" (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0") (match_operand:MVE_0 2 "s_register_operand" "w") (match_operand:MVE_0 3 "s_register_operand" "w") - (match_operand:HI 4 "vpr_register_operand" "Up")] + (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")] VCMULQ_M_F)) ] "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" @@ -6856,7 +6856,7 @@ (define_insn "mve_vcmulq_rot180_m_f<mode>" (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0") (match_operand:MVE_0 2 "s_register_operand" "w") (match_operand:MVE_0 3 "s_register_operand" "w") - (match_operand:HI 4 "vpr_register_operand" "Up")] + (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")] VCMULQ_ROT180_M_F)) ] "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" @@ -6873,7 +6873,7 @@ (define_insn "mve_vcmulq_rot270_m_f<mode>" (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0") (match_operand:MVE_0 2 "s_register_operand" "w") (match_operand:MVE_0 3 "s_register_operand" "w") - (match_operand:HI 4 "vpr_register_operand" "Up")] + (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")] VCMULQ_ROT270_M_F)) ] "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" @@ -6890,7 +6890,7 @@ (define_insn "mve_vcmulq_rot90_m_f<mode>" (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0") (match_operand:MVE_0 2 "s_register_operand" "w") (match_operand:MVE_0 3 "s_register_operand" "w") - (match_operand:HI 4 "vpr_register_operand" "Up")] + (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")] VCMULQ_ROT90_M_F)) ] "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" @@ -6907,7 +6907,7 @@ (define_insn "mve_veorq_m_f<mode>" (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0") (match_operand:MVE_0 2 "s_register_operand" "w") (match_operand:MVE_0 3 "s_register_operand" "w") - (match_operand:HI 4 "vpr_register_operand" "Up")] + (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")] VEORQ_M_F)) ] "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" @@ -6924,7 +6924,7 @@ (define_insn "mve_vfmaq_m_f<mode>" (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0") (match_operand:MVE_0 2 "s_register_operand" "w") (match_operand:MVE_0 3 "s_register_operand" "w") - (match_operand:HI 4 "vpr_register_operand" "Up")] + (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")] VFMAQ_M_F)) ] "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" @@ -6941,7 +6941,7 @@ (define_insn "mve_vfmaq_m_n_f<mode>" (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0") (match_operand:MVE_0 2 "s_register_operand" "w") (match_operand:<V_elem> 3 "s_register_operand" "r") - (match_operand:HI 4 "vpr_register_operand" "Up")] + (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")] VFMAQ_M_N_F)) ] "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" @@ -6958,7 +6958,7 @@ (define_insn "mve_vfmasq_m_n_f<mode>" (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0") (match_operand:MVE_0 2 "s_register_operand" "w") (match_operand:<V_elem> 3 "s_register_operand" "r") - (match_operand:HI 4 "vpr_register_operand" "Up")] + (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")] VFMASQ_M_N_F)) ] "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" @@ -6975,7 +6975,7 @@ (define_insn "mve_vfmsq_m_f<mode>" (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0") (match_operand:MVE_0 2 "s_register_operand" "w") (match_operand:MVE_0 3 "s_register_operand" "w") - (match_operand:HI 4 "vpr_register_operand" "Up")] + (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")] VFMSQ_M_F)) ] "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" @@ -6992,7 +6992,7 @@ (define_insn "mve_vmaxnmq_m_f<mode>" (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0") (match_operand:MVE_0 2 "s_register_operand" "w") (match_operand:MVE_0 3 "s_register_operand" "w") - (match_operand:HI 4 "vpr_register_operand" "Up")] + (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")] VMAXNMQ_M_F)) ] "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" @@ -7009,7 +7009,7 @@ (define_insn "mve_vminnmq_m_f<mode>" (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0") (match_operand:MVE_0 2 "s_register_operand" "w") (match_operand:MVE_0 3 "s_register_operand" "w") - (match_operand:HI 4 "vpr_register_operand" "Up")] + (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")] VMINNMQ_M_F)) ] "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" @@ -7026,7 +7026,7 @@ (define_insn "mve_vmulq_m_f<mode>" (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0") (match_operand:MVE_0 2 "s_register_operand" "w") (match_operand:MVE_0 3 "s_register_operand" "w") - (match_operand:HI 4 "vpr_register_operand" "Up")] + (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")] VMULQ_M_F)) ] "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" @@ -7043,7 +7043,7 @@ (define_insn "mve_vmulq_m_n_f<mode>" (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0") (match_operand:MVE_0 2 "s_register_operand" "w") (match_operand:<V_elem> 3 "s_register_operand" "r") - (match_operand:HI 4 "vpr_register_operand" "Up")] + (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")] VMULQ_M_N_F)) ] "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" @@ -7060,7 +7060,7 @@ (define_insn "mve_vornq_m_f<mode>" (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0") (match_operand:MVE_0 2 "s_register_operand" "w") (match_operand:MVE_0 3 "s_register_operand" "w") - (match_operand:HI 4 "vpr_register_operand" "Up")] + (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")] VORNQ_M_F)) ] "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" @@ -7077,7 +7077,7 @@ (define_insn "mve_vorrq_m_f<mode>" (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0") (match_operand:MVE_0 2 "s_register_operand" "w") (match_operand:MVE_0 3 "s_register_operand" "w") - (match_operand:HI 4 "vpr_register_operand" "Up")] + (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")] VORRQ_M_F)) ] "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" @@ -7094,7 +7094,7 @@ (define_insn "mve_vsubq_m_f<mode>" (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0") (match_operand:MVE_0 2 "s_register_operand" "w") (match_operand:MVE_0 3 "s_register_operand" "w") - (match_operand:HI 4 "vpr_register_operand" "Up")] + (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")] VSUBQ_M_F)) ] "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" @@ -7111,7 +7111,7 @@ (define_insn "mve_vsubq_m_n_f<mode>" (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0") (match_operand:MVE_0 2 "s_register_operand" "w") (match_operand:<V_elem> 3 "s_register_operand" "r") - (match_operand:HI 4 "vpr_register_operand" "Up")] + (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")] VSUBQ_M_N_F)) ] "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" @@ -7260,7 +7260,7 @@ (define_expand "mve_vstrbq_scatter_offset_p_<supf><mode>" [(match_operand:<MVE_B_ELEM> 0 "mve_scatter_memory") (match_operand:MVE_2 1 "s_register_operand") (match_operand:MVE_2 2 "s_register_operand") - (match_operand:HI 3 "vpr_register_operand" "Up") + (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up") (unspec:V4SI [(const_int 0)] VSTRBSOQ)] "TARGET_HAVE_MVE" { @@ -7279,7 +7279,7 @@ (define_insn "mve_vstrbq_scatter_offset_p_<supf><mode>_insn" [(match_operand:SI 0 "register_operand" "r") (match_operand:MVE_2 1 "s_register_operand" "w") (match_operand:MVE_2 2 "s_register_operand" "w") - (match_operand:HI 3 "vpr_register_operand" "Up")] + (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")] VSTRBSOQ))] "TARGET_HAVE_MVE" "vpst\;vstrbt.<V_sz_elem>\t%q2, [%0, %q1]" @@ -7314,7 +7314,7 @@ (define_insn "mve_vstrwq_scatter_base_p_<supf>v4si" (define_insn "mve_vstrbq_p_<supf><mode>" [(set (match_operand:<MVE_B_ELEM> 0 "mve_memory_operand" "=Ux") (unspec:<MVE_B_ELEM> [(match_operand:MVE_2 1 "s_register_operand" "w") - (match_operand:HI 2 "vpr_register_operand" "Up")] + (match_operand:<MVE_VPRED> 2 "vpr_register_operand" "Up")] VSTRBQ)) ] "TARGET_HAVE_MVE" @@ -7335,7 +7335,7 @@ (define_insn "mve_vldrbq_gather_offset_z_<supf><mode>" [(set (match_operand:MVE_2 0 "s_register_operand" "=&w") (unspec:MVE_2 [(match_operand:<MVE_B_ELEM> 1 "memory_operand" "Us") (match_operand:MVE_2 2 "s_register_operand" "w") - (match_operand:HI 3 "vpr_register_operand" "Up")] + (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")] VLDRBGOQ)) ] "TARGET_HAVE_MVE" @@ -7359,7 +7359,7 @@ (define_insn "mve_vldrbq_gather_offset_z_<supf><mode>" (define_insn "mve_vldrbq_z_<supf><mode>" [(set (match_operand:MVE_2 0 "s_register_operand" "=w") (unspec:MVE_2 [(match_operand:<MVE_B_ELEM> 1 "mve_memory_operand" "Ux") - (match_operand:HI 2 "vpr_register_operand" "Up")] + (match_operand:<MVE_VPRED> 2 "vpr_register_operand" "Up")] VLDRBQ)) ] "TARGET_HAVE_MVE" @@ -7446,7 +7446,7 @@ (define_insn "mve_vldrhq_gather_offset_z_<supf><mode>" [(set (match_operand:MVE_6 0 "s_register_operand" "=&w") (unspec:MVE_6 [(match_operand:<MVE_H_ELEM> 1 "memory_operand" "Us") (match_operand:MVE_6 2 "s_register_operand" "w") - (match_operand:HI 3 "vpr_register_operand" "Up") + (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up") ]VLDRHGOQ)) ] "TARGET_HAVE_MVE" @@ -7494,7 +7494,7 @@ (define_insn "mve_vldrhq_gather_shifted_offset_z_<supf><mode>" [(set (match_operand:MVE_6 0 "s_register_operand" "=&w") (unspec:MVE_6 [(match_operand:<MVE_H_ELEM> 1 "memory_operand" "Us") (match_operand:MVE_6 2 "s_register_operand" "w") - (match_operand:HI 3 "vpr_register_operand" "Up") + (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up") ]VLDRHGSOQ)) ] "TARGET_HAVE_MVE" @@ -7560,7 +7560,7 @@ (define_insn "mve_vldrhq_z_fv8hf" (define_insn "mve_vldrhq_z_<supf><mode>" [(set (match_operand:MVE_6 0 "s_register_operand" "=w") (unspec:MVE_6 [(match_operand:<MVE_H_ELEM> 1 "mve_memory_operand" "Ux") - (match_operand:HI 2 "vpr_register_operand" "Up")] + (match_operand:<MVE_VPRED> 2 "vpr_register_operand" "Up")] VLDRHQ)) ] "TARGET_HAVE_MVE" @@ -8136,7 +8136,7 @@ (define_insn "mve_vstrhq_p_fv8hf" (define_insn "mve_vstrhq_p_<supf><mode>" [(set (match_operand:<MVE_H_ELEM> 0 "mve_memory_operand" "=Ux") (unspec:<MVE_H_ELEM> [(match_operand:MVE_6 1 "s_register_operand" "w") - (match_operand:HI 2 "vpr_register_operand" "Up")] + (match_operand:<MVE_VPRED> 2 "vpr_register_operand" "Up")] VSTRHQ)) ] "TARGET_HAVE_MVE" @@ -8157,7 +8157,7 @@ (define_expand "mve_vstrhq_scatter_offset_p_<supf><mode>" [(match_operand:<MVE_H_ELEM> 0 "mve_scatter_memory") (match_operand:MVE_6 1 "s_register_operand") (match_operand:MVE_6 2 "s_register_operand") - (match_operand:HI 3 "vpr_register_operand") + (match_operand:<MVE_VPRED> 3 "vpr_register_operand") (unspec:V4SI [(const_int 0)] VSTRHSOQ)] "TARGET_HAVE_MVE" { @@ -8176,7 +8176,7 @@ (define_insn "mve_vstrhq_scatter_offset_p_<supf><mode>_insn" [(match_operand:SI 0 "register_operand" "r") (match_operand:MVE_6 1 "s_register_operand" "w") (match_operand:MVE_6 2 "s_register_operand" "w") - (match_operand:HI 3 "vpr_register_operand" "Up")] + (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")] VSTRHSOQ))] "TARGET_HAVE_MVE" "vpst\;vstrht.<V_sz_elem>\t%q2, [%0, %q1]" @@ -8217,7 +8217,7 @@ (define_expand "mve_vstrhq_scatter_shifted_offset_p_<supf><mode>" [(match_operand:<MVE_H_ELEM> 0 "mve_scatter_memory") (match_operand:MVE_6 1 "s_register_operand") (match_operand:MVE_6 2 "s_register_operand") - (match_operand:HI 3 "vpr_register_operand") + (match_operand:<MVE_VPRED> 3 "vpr_register_operand") (unspec:V4SI [(const_int 0)] VSTRHSSOQ)] "TARGET_HAVE_MVE" { @@ -8236,7 +8236,7 @@ (define_insn "mve_vstrhq_scatter_shifted_offset_p_<supf><mode>_insn" [(match_operand:SI 0 "register_operand" "r") (match_operand:MVE_6 1 "s_register_operand" "w") (match_operand:MVE_6 2 "s_register_operand" "w") - (match_operand:HI 3 "vpr_register_operand" "Up")] + (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")] VSTRHSSOQ))] "TARGET_HAVE_MVE" "vpst\;vstrht.<V_sz_elem>\t%q2, [%0, %q1, uxtw #1]" @@ -9023,7 +9023,7 @@ (define_expand "mve_vidupq_m_n_u<mode>" (match_operand:MVE_2 1 "s_register_operand") (match_operand:SI 2 "s_register_operand") (match_operand:SI 3 "mve_imm_selective_upto_8") - (match_operand:HI 4 "vpr_register_operand")] + (match_operand:<MVE_VPRED> 4 "vpr_register_operand")] "TARGET_HAVE_MVE" { rtx temp = gen_reg_rtx (SImode); @@ -9043,7 +9043,7 @@ (define_insn "mve_vidupq_m_wb_u<mode>_insn" (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") (match_operand:SI 3 "s_register_operand" "2") (match_operand:SI 4 "mve_imm_selective_upto_8" "Rg") - (match_operand:HI 5 "vpr_register_operand" "Up")] + (match_operand:<MVE_VPRED> 5 "vpr_register_operand" "Up")] VIDUPQ_M)) (set (match_operand:SI 2 "s_register_operand" "=Te") (plus:SI (match_dup 3) @@ -9091,7 +9091,7 @@ (define_expand "mve_vddupq_m_n_u<mode>" (match_operand:MVE_2 1 "s_register_operand") (match_operand:SI 2 "s_register_operand") (match_operand:SI 3 "mve_imm_selective_upto_8") - (match_operand:HI 4 "vpr_register_operand")] + (match_operand:<MVE_VPRED> 4 "vpr_register_operand")] "TARGET_HAVE_MVE" { rtx temp = gen_reg_rtx (SImode); @@ -9111,7 +9111,7 @@ (define_insn "mve_vddupq_m_wb_u<mode>_insn" (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") (match_operand:SI 3 "s_register_operand" "2") (match_operand:SI 4 "mve_imm_selective_upto_8" "Rg") - (match_operand:HI 5 "vpr_register_operand" "Up")] + (match_operand:<MVE_VPRED> 5 "vpr_register_operand" "Up")] VDDUPQ_M)) (set (match_operand:SI 2 "s_register_operand" "=Te") (minus:SI (match_dup 3) @@ -9182,7 +9182,7 @@ (define_expand "mve_vdwdupq_m_n_u<mode>" (match_operand:SI 2 "s_register_operand") (match_operand:DI 3 "s_register_operand") (match_operand:SI 4 "mve_imm_selective_upto_8") - (match_operand:HI 5 "vpr_register_operand")] + (match_operand:<MVE_VPRED> 5 "vpr_register_operand")] "TARGET_HAVE_MVE" { rtx ignore_wb = gen_reg_rtx (SImode); @@ -9202,7 +9202,7 @@ (define_expand "mve_vdwdupq_m_wb_u<mode>" (match_operand:SI 2 "s_register_operand") (match_operand:DI 3 "s_register_operand") (match_operand:SI 4 "mve_imm_selective_upto_8") - (match_operand:HI 5 "vpr_register_operand")] + (match_operand:<MVE_VPRED> 5 "vpr_register_operand")] "TARGET_HAVE_MVE" { rtx ignore_vec = gen_reg_rtx (<MODE>mode); @@ -9222,7 +9222,7 @@ (define_insn "mve_vdwdupq_m_wb_u<mode>_insn" (match_operand:SI 3 "s_register_operand" "1") (subreg:SI (match_operand:DI 4 "s_register_operand" "r") 4) (match_operand:SI 5 "mve_imm_selective_upto_8" "Rg") - (match_operand:HI 6 "vpr_register_operand" "Up")] + (match_operand:<MVE_VPRED> 6 "vpr_register_operand" "Up")] VDWDUPQ_M)) (set (match_operand:SI 1 "s_register_operand" "=Te") (unspec:SI [(match_dup 2) @@ -9299,7 +9299,7 @@ (define_expand "mve_viwdupq_m_n_u<mode>" (match_operand:SI 2 "s_register_operand") (match_operand:DI 3 "s_register_operand") (match_operand:SI 4 "mve_imm_selective_upto_8") - (match_operand:HI 5 "vpr_register_operand")] + (match_operand:<MVE_VPRED> 5 "vpr_register_operand")] "TARGET_HAVE_MVE" { rtx ignore_wb = gen_reg_rtx (SImode); @@ -9319,7 +9319,7 @@ (define_expand "mve_viwdupq_m_wb_u<mode>" (match_operand:SI 2 "s_register_operand") (match_operand:DI 3 "s_register_operand") (match_operand:SI 4 "mve_imm_selective_upto_8") - (match_operand:HI 5 "vpr_register_operand")] + (match_operand:<MVE_VPRED> 5 "vpr_register_operand")] "TARGET_HAVE_MVE" { rtx ignore_vec = gen_reg_rtx (<MODE>mode); @@ -9339,7 +9339,7 @@ (define_insn "mve_viwdupq_m_wb_u<mode>_insn" (match_operand:SI 3 "s_register_operand" "1") (subreg:SI (match_operand:DI 4 "s_register_operand" "r") 4) (match_operand:SI 5 "mve_imm_selective_upto_8" "Rg") - (match_operand:HI 6 "vpr_register_operand" "Up")] + (match_operand:<MVE_VPRED> 6 "vpr_register_operand" "Up")] VIWDUPQ_M)) (set (match_operand:SI 1 "s_register_operand" "=Te") (unspec:SI [(match_dup 2) @@ -10347,7 +10347,7 @@ (define_expand "mve_vshlcq_m_vec_<supf><mode>" (match_operand:MVE_2 1 "s_register_operand") (match_operand:SI 2 "s_register_operand") (match_operand:SI 3 "mve_imm_32") - (match_operand:HI 4 "vpr_register_operand") + (match_operand:<MVE_VPRED> 4 "vpr_register_operand") (unspec:MVE_2 [(const_int 0)] VSHLCQ_M)] "TARGET_HAVE_MVE" { @@ -10363,7 +10363,7 @@ (define_expand "mve_vshlcq_m_carry_<supf><mode>" (match_operand:MVE_2 1 "s_register_operand") (match_operand:SI 2 "s_register_operand") (match_operand:SI 3 "mve_imm_32") - (match_operand:HI 4 "vpr_register_operand") + (match_operand:<MVE_VPRED> 4 "vpr_register_operand") (unspec:MVE_2 [(const_int 0)] VSHLCQ_M)] "TARGET_HAVE_MVE" { @@ -10379,7 +10379,7 @@ (define_insn "mve_vshlcq_m_<supf><mode>" (unspec:MVE_2 [(match_operand:MVE_2 2 "s_register_operand" "0") (match_operand:SI 3 "s_register_operand" "1") (match_operand:SI 4 "mve_imm_32" "Rf") - (match_operand:HI 5 "vpr_register_operand" "Up")] + (match_operand:<MVE_VPRED> 5 "vpr_register_operand" "Up")] VSHLCQ_M)) (set (match_operand:SI 1 "s_register_operand" "=r") (unspec:SI [(match_dup 2) -- 2.25.1 ^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH 11/13] arm: Convert more MVE builtins to predicate qualifiers 2021-09-07 9:20 ` [PATCH 11/13] arm: Convert more MVE " Christophe Lyon @ 2021-10-11 14:17 ` Richard Sandiford 0 siblings, 0 replies; 9+ messages in thread From: Richard Sandiford @ 2021-10-11 14:17 UTC (permalink / raw) To: Christophe Lyon via Gcc-patches Christophe Lyon via Gcc-patches <gcc-patches@gcc.gnu.org> writes: > This patch covers all builtins that have an HI operand and use the > <mode> iterator, thus we can replace HI whe <MVE_vpred>. > > 2021-09-02 Christophe Lyon <christophe.lyon@foss.st.com> > > gcc/ > PR target/100757 > PR target/101325 > * config/arm/arm-builtins.c (TERNOP_UNONE_UNONE_NONE_UNONE_QUALIFIERS): Change to ... > (TERNOP_UNONE_UNONE_NONE_PRED_QUALIFIERS): ... this. > (TERNOP_UNONE_UNONE_IMM_UNONE_QUALIFIERS): Change to ... > (TERNOP_UNONE_UNONE_IMM_PRED_QUALIFIERS): ... this. > (TERNOP_NONE_NONE_IMM_UNONE_QUALIFIERS): Change to ... > (TERNOP_NONE_NONE_IMM_PRED_QUALIFIERS): ... this. > (TERNOP_NONE_NONE_UNONE_UNONE_QUALIFIERS): Change to ... > (TERNOP_NONE_NONE_UNONE_PRED_QUALIFIERS): ... this. > (QUADOP_UNONE_UNONE_NONE_NONE_UNONE_QUALIFIERS): Change to ... > (QUADOP_UNONE_UNONE_NONE_NONE_PRED_QUALIFIERS): ... this. > (QUADOP_NONE_NONE_NONE_NONE_PRED_QUALIFIERS): New. > (QUADOP_NONE_NONE_NONE_IMM_UNONE_QUALIFIERS): Change to ... > (QUADOP_NONE_NONE_NONE_IMM_PRED_QUALIFIERS): ... this. > (QUADOP_UNONE_UNONE_UNONE_UNONE_PRED_QUALIFIERS): New. > (QUADOP_UNONE_UNONE_NONE_IMM_UNONE_QUALIFIERS): Change to ... > (QUADOP_UNONE_UNONE_NONE_IMM_PRED_QUALIFIERS): ... this. > (QUADOP_NONE_NONE_UNONE_IMM_UNONE_QUALIFIERS): Change to ... > (QUADOP_NONE_NONE_UNONE_IMM_PRED_QUALIFIERS): ... this. > (QUADOP_UNONE_UNONE_UNONE_IMM_UNONE_QUALIFIERS): Change to ... > (QUADOP_UNONE_UNONE_UNONE_IMM_PRED_QUALIFIERS): ... this. > (QUADOP_UNONE_UNONE_UNONE_NONE_UNONE_QUALIFIERS): Change to ... > (QUADOP_UNONE_UNONE_UNONE_NONE_PRED_QUALIFIERS): ... this. > (STRS_P_QUALIFIERS): Use predicate qualifier. > (STRU_P_QUALIFIERS): Likewise. > (STRSU_P_QUALIFIERS): Likewise. > (STRSS_P_QUALIFIERS): Likewise. > (LDRGS_Z_QUALIFIERS): Likewise. > (LDRGU_Z_QUALIFIERS): Likewise. > (LDRS_Z_QUALIFIERS): Likewise. > (LDRU_Z_QUALIFIERS): Likewise. > (QUINOP_UNONE_UNONE_UNONE_UNONE_IMM_UNONE_QUALIFIERS): Change to ... > (QUINOP_UNONE_UNONE_UNONE_UNONE_IMM_PRED_QUALIFIERS): ... this. > (BINOP_NONE_NONE_PRED_QUALIFIERS): New. > (BINOP_UNONE_UNONE_PRED_QUALIFIERS): New. > * config/arm/arm_mve_builtins.def: Use new predicated qualifiers. > * config/arm/mve.md: Use MVE_VPRED instead of HI. OK, thanks. Richard > diff --git a/gcc/config/arm/arm-builtins.c b/gcc/config/arm/arm-builtins.c > index b3455d87d4f..06ff9d2278a 100644 > --- a/gcc/config/arm/arm-builtins.c > +++ b/gcc/config/arm/arm-builtins.c > @@ -533,18 +533,18 @@ arm_ternop_unone_unone_none_imm_qualifiers[SIMD_MAX_BUILTIN_ARGS] > (arm_ternop_unone_unone_none_imm_qualifiers) > > static enum arm_type_qualifiers > -arm_ternop_unone_unone_none_unone_qualifiers[SIMD_MAX_BUILTIN_ARGS] > +arm_ternop_unone_unone_none_pred_qualifiers[SIMD_MAX_BUILTIN_ARGS] > = { qualifier_unsigned, qualifier_unsigned, qualifier_none, > - qualifier_unsigned }; > -#define TERNOP_UNONE_UNONE_NONE_UNONE_QUALIFIERS \ > - (arm_ternop_unone_unone_none_unone_qualifiers) > + qualifier_predicate }; > +#define TERNOP_UNONE_UNONE_NONE_PRED_QUALIFIERS \ > + (arm_ternop_unone_unone_none_pred_qualifiers) > > static enum arm_type_qualifiers > -arm_ternop_unone_unone_imm_unone_qualifiers[SIMD_MAX_BUILTIN_ARGS] > +arm_ternop_unone_unone_imm_pred_qualifiers[SIMD_MAX_BUILTIN_ARGS] > = { qualifier_unsigned, qualifier_unsigned, qualifier_immediate, > - qualifier_unsigned }; > -#define TERNOP_UNONE_UNONE_IMM_UNONE_QUALIFIERS \ > - (arm_ternop_unone_unone_imm_unone_qualifiers) > + qualifier_predicate }; > +#define TERNOP_UNONE_UNONE_IMM_PRED_QUALIFIERS \ > + (arm_ternop_unone_unone_imm_pred_qualifiers) > > static enum arm_type_qualifiers > arm_ternop_pred_none_none_pred_qualifiers[SIMD_MAX_BUILTIN_ARGS] > @@ -571,16 +571,16 @@ arm_ternop_none_none_none_pred_qualifiers[SIMD_MAX_BUILTIN_ARGS] > (arm_ternop_none_none_none_pred_qualifiers) > > static enum arm_type_qualifiers > -arm_ternop_none_none_imm_unone_qualifiers[SIMD_MAX_BUILTIN_ARGS] > - = { qualifier_none, qualifier_none, qualifier_immediate, qualifier_unsigned }; > -#define TERNOP_NONE_NONE_IMM_UNONE_QUALIFIERS \ > - (arm_ternop_none_none_imm_unone_qualifiers) > +arm_ternop_none_none_imm_pred_qualifiers[SIMD_MAX_BUILTIN_ARGS] > + = { qualifier_none, qualifier_none, qualifier_immediate, qualifier_predicate }; > +#define TERNOP_NONE_NONE_IMM_PRED_QUALIFIERS \ > + (arm_ternop_none_none_imm_pred_qualifiers) > > static enum arm_type_qualifiers > -arm_ternop_none_none_unone_unone_qualifiers[SIMD_MAX_BUILTIN_ARGS] > - = { qualifier_none, qualifier_none, qualifier_unsigned, qualifier_unsigned }; > -#define TERNOP_NONE_NONE_UNONE_UNONE_QUALIFIERS \ > - (arm_ternop_none_none_unone_unone_qualifiers) > +arm_ternop_none_none_unone_pred_qualifiers[SIMD_MAX_BUILTIN_ARGS] > + = { qualifier_none, qualifier_none, qualifier_unsigned, qualifier_predicate }; > +#define TERNOP_NONE_NONE_UNONE_PRED_QUALIFIERS \ > + (arm_ternop_none_none_unone_pred_qualifiers) > > static enum arm_type_qualifiers > arm_ternop_unone_unone_unone_unone_qualifiers[SIMD_MAX_BUILTIN_ARGS] > @@ -610,11 +610,11 @@ arm_ternop_none_none_none_none_qualifiers[SIMD_MAX_BUILTIN_ARGS] > (arm_ternop_none_none_none_none_qualifiers) > > static enum arm_type_qualifiers > -arm_quadop_unone_unone_none_none_unone_qualifiers[SIMD_MAX_BUILTIN_ARGS] > +arm_quadop_unone_unone_none_none_pred_qualifiers[SIMD_MAX_BUILTIN_ARGS] > = { qualifier_unsigned, qualifier_unsigned, qualifier_none, qualifier_none, > - qualifier_unsigned }; > -#define QUADOP_UNONE_UNONE_NONE_NONE_UNONE_QUALIFIERS \ > - (arm_quadop_unone_unone_none_none_unone_qualifiers) > + qualifier_predicate }; > +#define QUADOP_UNONE_UNONE_NONE_NONE_PRED_QUALIFIERS \ > + (arm_quadop_unone_unone_none_none_pred_qualifiers) > > static enum arm_type_qualifiers > arm_quadop_none_none_none_none_unone_qualifiers[SIMD_MAX_BUILTIN_ARGS] > @@ -624,11 +624,18 @@ arm_quadop_none_none_none_none_unone_qualifiers[SIMD_MAX_BUILTIN_ARGS] > (arm_quadop_none_none_none_none_unone_qualifiers) > > static enum arm_type_qualifiers > -arm_quadop_none_none_none_imm_unone_qualifiers[SIMD_MAX_BUILTIN_ARGS] > +arm_quadop_none_none_none_none_pred_qualifiers[SIMD_MAX_BUILTIN_ARGS] > + = { qualifier_none, qualifier_none, qualifier_none, qualifier_none, > + qualifier_predicate }; > +#define QUADOP_NONE_NONE_NONE_NONE_PRED_QUALIFIERS \ > + (arm_quadop_none_none_none_none_pred_qualifiers) > + > +static enum arm_type_qualifiers > +arm_quadop_none_none_none_imm_pred_qualifiers[SIMD_MAX_BUILTIN_ARGS] > = { qualifier_none, qualifier_none, qualifier_none, qualifier_immediate, > - qualifier_unsigned }; > -#define QUADOP_NONE_NONE_NONE_IMM_UNONE_QUALIFIERS \ > - (arm_quadop_none_none_none_imm_unone_qualifiers) > + qualifier_predicate }; > +#define QUADOP_NONE_NONE_NONE_IMM_PRED_QUALIFIERS \ > + (arm_quadop_none_none_none_imm_pred_qualifiers) > > static enum arm_type_qualifiers > arm_quadop_unone_unone_unone_unone_unone_qualifiers[SIMD_MAX_BUILTIN_ARGS] > @@ -638,32 +645,39 @@ arm_quadop_unone_unone_unone_unone_unone_qualifiers[SIMD_MAX_BUILTIN_ARGS] > (arm_quadop_unone_unone_unone_unone_unone_qualifiers) > > static enum arm_type_qualifiers > -arm_quadop_unone_unone_none_imm_unone_qualifiers[SIMD_MAX_BUILTIN_ARGS] > +arm_quadop_unone_unone_unone_unone_pred_qualifiers[SIMD_MAX_BUILTIN_ARGS] > + = { qualifier_unsigned, qualifier_unsigned, qualifier_unsigned, > + qualifier_unsigned, qualifier_predicate }; > +#define QUADOP_UNONE_UNONE_UNONE_UNONE_PRED_QUALIFIERS \ > + (arm_quadop_unone_unone_unone_unone_pred_qualifiers) > + > +static enum arm_type_qualifiers > +arm_quadop_unone_unone_none_imm_pred_qualifiers[SIMD_MAX_BUILTIN_ARGS] > = { qualifier_unsigned, qualifier_unsigned, qualifier_none, > - qualifier_immediate, qualifier_unsigned }; > -#define QUADOP_UNONE_UNONE_NONE_IMM_UNONE_QUALIFIERS \ > - (arm_quadop_unone_unone_none_imm_unone_qualifiers) > + qualifier_immediate, qualifier_predicate }; > +#define QUADOP_UNONE_UNONE_NONE_IMM_PRED_QUALIFIERS \ > + (arm_quadop_unone_unone_none_imm_pred_qualifiers) > > static enum arm_type_qualifiers > -arm_quadop_none_none_unone_imm_unone_qualifiers[SIMD_MAX_BUILTIN_ARGS] > +arm_quadop_none_none_unone_imm_pred_qualifiers[SIMD_MAX_BUILTIN_ARGS] > = { qualifier_none, qualifier_none, qualifier_unsigned, qualifier_immediate, > - qualifier_unsigned }; > -#define QUADOP_NONE_NONE_UNONE_IMM_UNONE_QUALIFIERS \ > - (arm_quadop_none_none_unone_imm_unone_qualifiers) > + qualifier_predicate }; > +#define QUADOP_NONE_NONE_UNONE_IMM_PRED_QUALIFIERS \ > + (arm_quadop_none_none_unone_imm_pred_qualifiers) > > static enum arm_type_qualifiers > -arm_quadop_unone_unone_unone_imm_unone_qualifiers[SIMD_MAX_BUILTIN_ARGS] > +arm_quadop_unone_unone_unone_imm_pred_qualifiers[SIMD_MAX_BUILTIN_ARGS] > = { qualifier_unsigned, qualifier_unsigned, qualifier_unsigned, > - qualifier_immediate, qualifier_unsigned }; > -#define QUADOP_UNONE_UNONE_UNONE_IMM_UNONE_QUALIFIERS \ > - (arm_quadop_unone_unone_unone_imm_unone_qualifiers) > + qualifier_immediate, qualifier_predicate }; > +#define QUADOP_UNONE_UNONE_UNONE_IMM_PRED_QUALIFIERS \ > + (arm_quadop_unone_unone_unone_imm_pred_qualifiers) > > static enum arm_type_qualifiers > -arm_quadop_unone_unone_unone_none_unone_qualifiers[SIMD_MAX_BUILTIN_ARGS] > +arm_quadop_unone_unone_unone_none_pred_qualifiers[SIMD_MAX_BUILTIN_ARGS] > = { qualifier_unsigned, qualifier_unsigned, qualifier_unsigned, > - qualifier_none, qualifier_unsigned }; > -#define QUADOP_UNONE_UNONE_UNONE_NONE_UNONE_QUALIFIERS \ > - (arm_quadop_unone_unone_unone_none_unone_qualifiers) > + qualifier_none, qualifier_predicate }; > +#define QUADOP_UNONE_UNONE_UNONE_NONE_PRED_QUALIFIERS \ > + (arm_quadop_unone_unone_unone_none_pred_qualifiers) > > static enum arm_type_qualifiers > arm_strs_qualifiers[SIMD_MAX_BUILTIN_ARGS] > @@ -700,25 +714,25 @@ arm_strsbu_qualifiers[SIMD_MAX_BUILTIN_ARGS] > > static enum arm_type_qualifiers > arm_strs_p_qualifiers[SIMD_MAX_BUILTIN_ARGS] > - = { qualifier_void, qualifier_pointer, qualifier_none, qualifier_unsigned}; > + = { qualifier_void, qualifier_pointer, qualifier_none, qualifier_predicate}; > #define STRS_P_QUALIFIERS (arm_strs_p_qualifiers) > > static enum arm_type_qualifiers > arm_stru_p_qualifiers[SIMD_MAX_BUILTIN_ARGS] > = { qualifier_void, qualifier_pointer, qualifier_unsigned, > - qualifier_unsigned}; > + qualifier_predicate}; > #define STRU_P_QUALIFIERS (arm_stru_p_qualifiers) > > static enum arm_type_qualifiers > arm_strsu_p_qualifiers[SIMD_MAX_BUILTIN_ARGS] > = { qualifier_void, qualifier_pointer, qualifier_unsigned, > - qualifier_unsigned, qualifier_unsigned}; > + qualifier_unsigned, qualifier_predicate}; > #define STRSU_P_QUALIFIERS (arm_strsu_p_qualifiers) > > static enum arm_type_qualifiers > arm_strss_p_qualifiers[SIMD_MAX_BUILTIN_ARGS] > = { qualifier_void, qualifier_pointer, qualifier_unsigned, > - qualifier_none, qualifier_unsigned}; > + qualifier_none, qualifier_predicate}; > #define STRSS_P_QUALIFIERS (arm_strss_p_qualifiers) > > static enum arm_type_qualifiers > @@ -778,31 +792,31 @@ arm_ldrgbu_z_qualifiers[SIMD_MAX_BUILTIN_ARGS] > static enum arm_type_qualifiers > arm_ldrgs_z_qualifiers[SIMD_MAX_BUILTIN_ARGS] > = { qualifier_none, qualifier_pointer, qualifier_unsigned, > - qualifier_unsigned}; > + qualifier_predicate}; > #define LDRGS_Z_QUALIFIERS (arm_ldrgs_z_qualifiers) > > static enum arm_type_qualifiers > arm_ldrgu_z_qualifiers[SIMD_MAX_BUILTIN_ARGS] > = { qualifier_unsigned, qualifier_pointer, qualifier_unsigned, > - qualifier_unsigned}; > + qualifier_predicate}; > #define LDRGU_Z_QUALIFIERS (arm_ldrgu_z_qualifiers) > > static enum arm_type_qualifiers > arm_ldrs_z_qualifiers[SIMD_MAX_BUILTIN_ARGS] > - = { qualifier_none, qualifier_pointer, qualifier_unsigned}; > + = { qualifier_none, qualifier_pointer, qualifier_predicate}; > #define LDRS_Z_QUALIFIERS (arm_ldrs_z_qualifiers) > > static enum arm_type_qualifiers > arm_ldru_z_qualifiers[SIMD_MAX_BUILTIN_ARGS] > - = { qualifier_unsigned, qualifier_pointer, qualifier_unsigned}; > + = { qualifier_unsigned, qualifier_pointer, qualifier_predicate}; > #define LDRU_Z_QUALIFIERS (arm_ldru_z_qualifiers) > > static enum arm_type_qualifiers > -arm_quinop_unone_unone_unone_unone_imm_unone_qualifiers[SIMD_MAX_BUILTIN_ARGS] > +arm_quinop_unone_unone_unone_unone_imm_pred_qualifiers[SIMD_MAX_BUILTIN_ARGS] > = { qualifier_unsigned, qualifier_unsigned, qualifier_unsigned, > - qualifier_unsigned, qualifier_immediate, qualifier_unsigned }; > -#define QUINOP_UNONE_UNONE_UNONE_UNONE_IMM_UNONE_QUALIFIERS \ > - (arm_quinop_unone_unone_unone_unone_imm_unone_qualifiers) > + qualifier_unsigned, qualifier_immediate, qualifier_predicate }; > +#define QUINOP_UNONE_UNONE_UNONE_UNONE_IMM_PRED_QUALIFIERS \ > + (arm_quinop_unone_unone_unone_unone_imm_pred_qualifiers) > > static enum arm_type_qualifiers > arm_ldrgbwbxu_qualifiers[SIMD_MAX_BUILTIN_ARGS] > @@ -879,6 +893,18 @@ arm_sqshl_qualifiers[SIMD_MAX_BUILTIN_ARGS] > = { qualifier_unsigned, qualifier_unsigned, qualifier_const}; > #define SQSHL_QUALIFIERS (arm_sqshl_qualifiers) > > +static enum arm_type_qualifiers > +arm_binop_none_none_pred_qualifiers[SIMD_MAX_BUILTIN_ARGS] > + = { qualifier_none, qualifier_none, qualifier_predicate }; > +#define BINOP_NONE_NONE_PRED_QUALIFIERS \ > + (arm_binop_none_none_pred_qualifiers) > + > +static enum arm_type_qualifiers > +arm_binop_unone_unone_pred_qualifiers[SIMD_MAX_BUILTIN_ARGS] > + = { qualifier_unsigned, qualifier_unsigned, qualifier_predicate }; > +#define BINOP_UNONE_UNONE_PRED_QUALIFIERS \ > + (arm_binop_unone_unone_pred_qualifiers) > + > /* End of Qualifier for MVE builtins. */ > > /* void ([T element type] *, T, immediate). */ > diff --git a/gcc/config/arm/arm_mve_builtins.def b/gcc/config/arm/arm_mve_builtins.def > index 91ed2073918..bb79edf83ca 100644 > --- a/gcc/config/arm/arm_mve_builtins.def > +++ b/gcc/config/arm/arm_mve_builtins.def > @@ -123,7 +123,7 @@ VAR3 (BINOP_PRED_UNONE_UNONE, vcmpcsq_, v16qi, v8hi, v4si) > VAR3 (BINOP_PRED_UNONE_UNONE, vcmpcsq_n_, v16qi, v8hi, v4si) > VAR3 (BINOP_UNONE_UNONE_UNONE, vbicq_u, v16qi, v8hi, v4si) > VAR3 (BINOP_UNONE_UNONE_UNONE, vandq_u, v16qi, v8hi, v4si) > -VAR3 (BINOP_UNONE_UNONE_UNONE, vaddvq_p_u, v16qi, v8hi, v4si) > +VAR3 (BINOP_UNONE_UNONE_PRED, vaddvq_p_u, v16qi, v8hi, v4si) > VAR3 (BINOP_UNONE_UNONE_UNONE, vaddvaq_u, v16qi, v8hi, v4si) > VAR3 (BINOP_UNONE_UNONE_UNONE, vaddq_n_u, v16qi, v8hi, v4si) > VAR3 (BINOP_UNONE_UNONE_UNONE, vabdq_u, v16qi, v8hi, v4si) > @@ -154,7 +154,7 @@ VAR3 (BINOP_PRED_NONE_NONE, vcmpgeq_n_, v16qi, v8hi, v4si) > VAR3 (BINOP_PRED_NONE_NONE, vcmpeqq_, v16qi, v8hi, v4si) > VAR3 (BINOP_PRED_NONE_NONE, vcmpeqq_n_, v16qi, v8hi, v4si) > VAR3 (BINOP_UNONE_NONE_IMM, vqshluq_n_s, v16qi, v8hi, v4si) > -VAR3 (BINOP_NONE_NONE_UNONE, vaddvq_p_s, v16qi, v8hi, v4si) > +VAR3 (BINOP_NONE_NONE_PRED, vaddvq_p_s, v16qi, v8hi, v4si) > VAR3 (BINOP_NONE_NONE_NONE, vsubq_s, v16qi, v8hi, v4si) > VAR3 (BINOP_NONE_NONE_NONE, vsubq_n_s, v16qi, v8hi, v4si) > VAR3 (BINOP_NONE_NONE_NONE, vshlq_r_s, v16qi, v8hi, v4si) > @@ -277,35 +277,35 @@ VAR1 (BINOP_NONE_NONE_NONE, vrmlaldavhq_s, v4si) > VAR1 (BINOP_NONE_NONE_NONE, vcvttq_f16_f32, v8hf) > VAR1 (BINOP_NONE_NONE_NONE, vcvtbq_f16_f32, v8hf) > VAR1 (BINOP_NONE_NONE_NONE, vaddlvaq_s, v4si) > -VAR2 (TERNOP_NONE_NONE_IMM_UNONE, vbicq_m_n_s, v8hi, v4si) > -VAR2 (TERNOP_UNONE_UNONE_IMM_UNONE, vbicq_m_n_u, v8hi, v4si) > +VAR2 (TERNOP_NONE_NONE_IMM_PRED, vbicq_m_n_s, v8hi, v4si) > +VAR2 (TERNOP_UNONE_UNONE_IMM_PRED, vbicq_m_n_u, v8hi, v4si) > VAR2 (TERNOP_NONE_NONE_NONE_IMM, vqrshrnbq_n_s, v8hi, v4si) > VAR2 (TERNOP_UNONE_UNONE_UNONE_IMM, vqrshrnbq_n_u, v8hi, v4si) > VAR1 (TERNOP_NONE_NONE_NONE_NONE, vrmlaldavhaq_s, v4si) > VAR1 (TERNOP_UNONE_UNONE_UNONE_UNONE, vrmlaldavhaq_u, v4si) > -VAR2 (TERNOP_NONE_NONE_UNONE_UNONE, vcvtq_m_to_f_u, v8hf, v4sf) > -VAR2 (TERNOP_NONE_NONE_NONE_UNONE, vcvtq_m_to_f_s, v8hf, v4sf) > +VAR2 (TERNOP_NONE_NONE_UNONE_PRED, vcvtq_m_to_f_u, v8hf, v4sf) > +VAR2 (TERNOP_NONE_NONE_NONE_PRED, vcvtq_m_to_f_s, v8hf, v4sf) > VAR2 (TERNOP_PRED_NONE_NONE_PRED, vcmpeqq_m_f, v8hf, v4sf) > VAR3 (TERNOP_UNONE_NONE_UNONE_IMM, vshlcq_carry_s, v16qi, v8hi, v4si) > VAR3 (TERNOP_UNONE_UNONE_UNONE_IMM, vshlcq_carry_u, v16qi, v8hi, v4si) > VAR2 (TERNOP_UNONE_UNONE_NONE_IMM, vqrshrunbq_n_s, v8hi, v4si) > VAR3 (TERNOP_UNONE_UNONE_NONE_NONE, vabavq_s, v16qi, v8hi, v4si) > VAR3 (TERNOP_UNONE_UNONE_UNONE_UNONE, vabavq_u, v16qi, v8hi, v4si) > -VAR2 (TERNOP_UNONE_UNONE_NONE_UNONE, vcvtaq_m_u, v8hi, v4si) > -VAR2 (TERNOP_NONE_NONE_NONE_UNONE, vcvtaq_m_s, v8hi, v4si) > +VAR2 (TERNOP_UNONE_UNONE_NONE_PRED, vcvtaq_m_u, v8hi, v4si) > +VAR2 (TERNOP_NONE_NONE_NONE_PRED, vcvtaq_m_s, v8hi, v4si) > VAR3 (TERNOP_UNONE_UNONE_UNONE_IMM, vshlcq_vec_u, v16qi, v8hi, v4si) > VAR3 (TERNOP_NONE_NONE_UNONE_IMM, vshlcq_vec_s, v16qi, v8hi, v4si) > VAR4 (TERNOP_UNONE_UNONE_UNONE_PRED, vpselq_u, v16qi, v8hi, v4si, v2di) > VAR4 (TERNOP_NONE_NONE_NONE_PRED, vpselq_s, v16qi, v8hi, v4si, v2di) > -VAR3 (TERNOP_UNONE_UNONE_UNONE_UNONE, vrev64q_m_u, v16qi, v8hi, v4si) > -VAR3 (TERNOP_UNONE_UNONE_UNONE_UNONE, vmvnq_m_u, v16qi, v8hi, v4si) > +VAR3 (TERNOP_UNONE_UNONE_UNONE_PRED, vrev64q_m_u, v16qi, v8hi, v4si) > +VAR3 (TERNOP_UNONE_UNONE_UNONE_PRED, vmvnq_m_u, v16qi, v8hi, v4si) > VAR3 (TERNOP_UNONE_UNONE_UNONE_UNONE, vmlasq_n_u, v16qi, v8hi, v4si) > VAR3 (TERNOP_UNONE_UNONE_UNONE_UNONE, vmlaq_n_u, v16qi, v8hi, v4si) > -VAR3 (TERNOP_UNONE_UNONE_UNONE_UNONE, vmladavq_p_u, v16qi, v8hi, v4si) > +VAR3 (TERNOP_UNONE_UNONE_UNONE_PRED, vmladavq_p_u, v16qi, v8hi, v4si) > VAR3 (TERNOP_UNONE_UNONE_UNONE_UNONE, vmladavaq_u, v16qi, v8hi, v4si) > -VAR3 (TERNOP_UNONE_UNONE_UNONE_UNONE, vminvq_p_u, v16qi, v8hi, v4si) > -VAR3 (TERNOP_UNONE_UNONE_UNONE_UNONE, vmaxvq_p_u, v16qi, v8hi, v4si) > -VAR3 (TERNOP_UNONE_UNONE_UNONE_UNONE, vdupq_m_n_u, v16qi, v8hi, v4si) > +VAR3 (TERNOP_UNONE_UNONE_UNONE_PRED, vminvq_p_u, v16qi, v8hi, v4si) > +VAR3 (TERNOP_UNONE_UNONE_UNONE_PRED, vmaxvq_p_u, v16qi, v8hi, v4si) > +VAR3 (TERNOP_UNONE_UNONE_UNONE_PRED, vdupq_m_n_u, v16qi, v8hi, v4si) > VAR3 (TERNOP_PRED_UNONE_UNONE_PRED, vcmpneq_m_u, v16qi, v8hi, v4si) > VAR3 (TERNOP_PRED_UNONE_UNONE_PRED, vcmpneq_m_n_u, v16qi, v8hi, v4si) > VAR3 (TERNOP_PRED_UNONE_UNONE_PRED, vcmphiq_m_u, v16qi, v8hi, v4si) > @@ -314,18 +314,18 @@ VAR3 (TERNOP_PRED_UNONE_UNONE_PRED, vcmpeqq_m_u, v16qi, v8hi, v4si) > VAR3 (TERNOP_PRED_UNONE_UNONE_PRED, vcmpeqq_m_n_u, v16qi, v8hi, v4si) > VAR3 (TERNOP_PRED_UNONE_UNONE_PRED, vcmpcsq_m_u, v16qi, v8hi, v4si) > VAR3 (TERNOP_PRED_UNONE_UNONE_PRED, vcmpcsq_m_n_u, v16qi, v8hi, v4si) > -VAR3 (TERNOP_UNONE_UNONE_UNONE_UNONE, vclzq_m_u, v16qi, v8hi, v4si) > -VAR3 (TERNOP_UNONE_UNONE_UNONE_UNONE, vaddvaq_p_u, v16qi, v8hi, v4si) > +VAR3 (TERNOP_UNONE_UNONE_UNONE_PRED, vclzq_m_u, v16qi, v8hi, v4si) > +VAR3 (TERNOP_UNONE_UNONE_UNONE_PRED, vaddvaq_p_u, v16qi, v8hi, v4si) > VAR3 (TERNOP_UNONE_UNONE_UNONE_IMM, vsriq_n_u, v16qi, v8hi, v4si) > VAR3 (TERNOP_UNONE_UNONE_UNONE_IMM, vsliq_n_u, v16qi, v8hi, v4si) > -VAR3 (TERNOP_UNONE_UNONE_NONE_UNONE, vshlq_m_r_u, v16qi, v8hi, v4si) > -VAR3 (TERNOP_UNONE_UNONE_NONE_UNONE, vrshlq_m_n_u, v16qi, v8hi, v4si) > -VAR3 (TERNOP_UNONE_UNONE_NONE_UNONE, vqshlq_m_r_u, v16qi, v8hi, v4si) > -VAR3 (TERNOP_UNONE_UNONE_NONE_UNONE, vqrshlq_m_n_u, v16qi, v8hi, v4si) > -VAR3 (TERNOP_UNONE_UNONE_NONE_UNONE, vminavq_p_s, v16qi, v8hi, v4si) > -VAR3 (TERNOP_UNONE_UNONE_NONE_UNONE, vminaq_m_s, v16qi, v8hi, v4si) > -VAR3 (TERNOP_UNONE_UNONE_NONE_UNONE, vmaxavq_p_s, v16qi, v8hi, v4si) > -VAR3 (TERNOP_UNONE_UNONE_NONE_UNONE, vmaxaq_m_s, v16qi, v8hi, v4si) > +VAR3 (TERNOP_UNONE_UNONE_NONE_PRED, vshlq_m_r_u, v16qi, v8hi, v4si) > +VAR3 (TERNOP_UNONE_UNONE_NONE_PRED, vrshlq_m_n_u, v16qi, v8hi, v4si) > +VAR3 (TERNOP_UNONE_UNONE_NONE_PRED, vqshlq_m_r_u, v16qi, v8hi, v4si) > +VAR3 (TERNOP_UNONE_UNONE_NONE_PRED, vqrshlq_m_n_u, v16qi, v8hi, v4si) > +VAR3 (TERNOP_UNONE_UNONE_NONE_PRED, vminavq_p_s, v16qi, v8hi, v4si) > +VAR3 (TERNOP_UNONE_UNONE_NONE_PRED, vminaq_m_s, v16qi, v8hi, v4si) > +VAR3 (TERNOP_UNONE_UNONE_NONE_PRED, vmaxavq_p_s, v16qi, v8hi, v4si) > +VAR3 (TERNOP_UNONE_UNONE_NONE_PRED, vmaxaq_m_s, v16qi, v8hi, v4si) > VAR3 (TERNOP_PRED_NONE_NONE_PRED, vcmpneq_m_s, v16qi, v8hi, v4si) > VAR3 (TERNOP_PRED_NONE_NONE_PRED, vcmpneq_m_n_s, v16qi, v8hi, v4si) > VAR3 (TERNOP_PRED_NONE_NONE_PRED, vcmpltq_m_s, v16qi, v8hi, v4si) > @@ -338,26 +338,26 @@ VAR3 (TERNOP_PRED_NONE_NONE_PRED, vcmpgeq_m_s, v16qi, v8hi, v4si) > VAR3 (TERNOP_PRED_NONE_NONE_PRED, vcmpgeq_m_n_s, v16qi, v8hi, v4si) > VAR3 (TERNOP_PRED_NONE_NONE_PRED, vcmpeqq_m_s, v16qi, v8hi, v4si) > VAR3 (TERNOP_PRED_NONE_NONE_PRED, vcmpeqq_m_n_s, v16qi, v8hi, v4si) > -VAR3 (TERNOP_NONE_NONE_NONE_UNONE, vshlq_m_r_s, v16qi, v8hi, v4si) > -VAR3 (TERNOP_NONE_NONE_NONE_UNONE, vrshlq_m_n_s, v16qi, v8hi, v4si) > -VAR3 (TERNOP_NONE_NONE_NONE_UNONE, vrev64q_m_s, v16qi, v8hi, v4si) > -VAR3 (TERNOP_NONE_NONE_NONE_UNONE, vqshlq_m_r_s, v16qi, v8hi, v4si) > -VAR3 (TERNOP_NONE_NONE_NONE_UNONE, vqrshlq_m_n_s, v16qi, v8hi, v4si) > -VAR3 (TERNOP_NONE_NONE_NONE_UNONE, vqnegq_m_s, v16qi, v8hi, v4si) > -VAR3 (TERNOP_NONE_NONE_NONE_UNONE, vqabsq_m_s, v16qi, v8hi, v4si) > -VAR3 (TERNOP_NONE_NONE_NONE_UNONE, vnegq_m_s, v16qi, v8hi, v4si) > -VAR3 (TERNOP_NONE_NONE_NONE_UNONE, vmvnq_m_s, v16qi, v8hi, v4si) > -VAR3 (TERNOP_NONE_NONE_NONE_UNONE, vmlsdavxq_p_s, v16qi, v8hi, v4si) > -VAR3 (TERNOP_NONE_NONE_NONE_UNONE, vmlsdavq_p_s, v16qi, v8hi, v4si) > -VAR3 (TERNOP_NONE_NONE_NONE_UNONE, vmladavxq_p_s, v16qi, v8hi, v4si) > -VAR3 (TERNOP_NONE_NONE_NONE_UNONE, vmladavq_p_s, v16qi, v8hi, v4si) > -VAR3 (TERNOP_NONE_NONE_NONE_UNONE, vminvq_p_s, v16qi, v8hi, v4si) > -VAR3 (TERNOP_NONE_NONE_NONE_UNONE, vmaxvq_p_s, v16qi, v8hi, v4si) > -VAR3 (TERNOP_NONE_NONE_NONE_UNONE, vdupq_m_n_s, v16qi, v8hi, v4si) > -VAR3 (TERNOP_NONE_NONE_NONE_UNONE, vclzq_m_s, v16qi, v8hi, v4si) > -VAR3 (TERNOP_NONE_NONE_NONE_UNONE, vclsq_m_s, v16qi, v8hi, v4si) > -VAR3 (TERNOP_NONE_NONE_NONE_UNONE, vaddvaq_p_s, v16qi, v8hi, v4si) > -VAR3 (TERNOP_NONE_NONE_NONE_UNONE, vabsq_m_s, v16qi, v8hi, v4si) > +VAR3 (TERNOP_NONE_NONE_NONE_PRED, vshlq_m_r_s, v16qi, v8hi, v4si) > +VAR3 (TERNOP_NONE_NONE_NONE_PRED, vrshlq_m_n_s, v16qi, v8hi, v4si) > +VAR3 (TERNOP_NONE_NONE_NONE_PRED, vrev64q_m_s, v16qi, v8hi, v4si) > +VAR3 (TERNOP_NONE_NONE_NONE_PRED, vqshlq_m_r_s, v16qi, v8hi, v4si) > +VAR3 (TERNOP_NONE_NONE_NONE_PRED, vqrshlq_m_n_s, v16qi, v8hi, v4si) > +VAR3 (TERNOP_NONE_NONE_NONE_PRED, vqnegq_m_s, v16qi, v8hi, v4si) > +VAR3 (TERNOP_NONE_NONE_NONE_PRED, vqabsq_m_s, v16qi, v8hi, v4si) > +VAR3 (TERNOP_NONE_NONE_NONE_PRED, vnegq_m_s, v16qi, v8hi, v4si) > +VAR3 (TERNOP_NONE_NONE_NONE_PRED, vmvnq_m_s, v16qi, v8hi, v4si) > +VAR3 (TERNOP_NONE_NONE_NONE_PRED, vmlsdavxq_p_s, v16qi, v8hi, v4si) > +VAR3 (TERNOP_NONE_NONE_NONE_PRED, vmlsdavq_p_s, v16qi, v8hi, v4si) > +VAR3 (TERNOP_NONE_NONE_NONE_PRED, vmladavxq_p_s, v16qi, v8hi, v4si) > +VAR3 (TERNOP_NONE_NONE_NONE_PRED, vmladavq_p_s, v16qi, v8hi, v4si) > +VAR3 (TERNOP_NONE_NONE_NONE_PRED, vminvq_p_s, v16qi, v8hi, v4si) > +VAR3 (TERNOP_NONE_NONE_NONE_PRED, vmaxvq_p_s, v16qi, v8hi, v4si) > +VAR3 (TERNOP_NONE_NONE_NONE_PRED, vdupq_m_n_s, v16qi, v8hi, v4si) > +VAR3 (TERNOP_NONE_NONE_NONE_PRED, vclzq_m_s, v16qi, v8hi, v4si) > +VAR3 (TERNOP_NONE_NONE_NONE_PRED, vclsq_m_s, v16qi, v8hi, v4si) > +VAR3 (TERNOP_NONE_NONE_NONE_PRED, vaddvaq_p_s, v16qi, v8hi, v4si) > +VAR3 (TERNOP_NONE_NONE_NONE_PRED, vabsq_m_s, v16qi, v8hi, v4si) > VAR3 (TERNOP_NONE_NONE_NONE_NONE, vqrdmlsdhxq_s, v16qi, v8hi, v4si) > VAR3 (TERNOP_NONE_NONE_NONE_NONE, vqrdmlsdhq_s, v16qi, v8hi, v4si) > VAR3 (TERNOP_NONE_NONE_NONE_NONE, vqrdmlashq_n_s, v16qi, v8hi, v4si) > @@ -378,14 +378,14 @@ VAR3 (TERNOP_NONE_NONE_NONE_NONE, vmladavaxq_s, v16qi, v8hi, v4si) > VAR3 (TERNOP_NONE_NONE_NONE_NONE, vmladavaq_s, v16qi, v8hi, v4si) > VAR3 (TERNOP_NONE_NONE_NONE_IMM, vsriq_n_s, v16qi, v8hi, v4si) > VAR3 (TERNOP_NONE_NONE_NONE_IMM, vsliq_n_s, v16qi, v8hi, v4si) > -VAR2 (TERNOP_UNONE_UNONE_UNONE_UNONE, vrev32q_m_u, v16qi, v8hi) > -VAR2 (TERNOP_UNONE_UNONE_UNONE_UNONE, vqmovntq_m_u, v8hi, v4si) > -VAR2 (TERNOP_UNONE_UNONE_UNONE_UNONE, vqmovnbq_m_u, v8hi, v4si) > -VAR2 (TERNOP_UNONE_UNONE_UNONE_UNONE, vmovntq_m_u, v8hi, v4si) > -VAR2 (TERNOP_UNONE_UNONE_UNONE_UNONE, vmovnbq_m_u, v8hi, v4si) > -VAR2 (TERNOP_UNONE_UNONE_UNONE_UNONE, vmovltq_m_u, v16qi, v8hi) > -VAR2 (TERNOP_UNONE_UNONE_UNONE_UNONE, vmovlbq_m_u, v16qi, v8hi) > -VAR2 (TERNOP_UNONE_UNONE_UNONE_UNONE, vmlaldavq_p_u, v8hi, v4si) > +VAR2 (TERNOP_UNONE_UNONE_UNONE_PRED, vrev32q_m_u, v16qi, v8hi) > +VAR2 (TERNOP_UNONE_UNONE_UNONE_PRED, vqmovntq_m_u, v8hi, v4si) > +VAR2 (TERNOP_UNONE_UNONE_UNONE_PRED, vqmovnbq_m_u, v8hi, v4si) > +VAR2 (TERNOP_UNONE_UNONE_UNONE_PRED, vmovntq_m_u, v8hi, v4si) > +VAR2 (TERNOP_UNONE_UNONE_UNONE_PRED, vmovnbq_m_u, v8hi, v4si) > +VAR2 (TERNOP_UNONE_UNONE_UNONE_PRED, vmovltq_m_u, v16qi, v8hi) > +VAR2 (TERNOP_UNONE_UNONE_UNONE_PRED, vmovlbq_m_u, v16qi, v8hi) > +VAR2 (TERNOP_UNONE_UNONE_UNONE_PRED, vmlaldavq_p_u, v8hi, v4si) > VAR2 (TERNOP_UNONE_UNONE_UNONE_UNONE, vmlaldavaq_u, v8hi, v4si) > VAR2 (TERNOP_UNONE_UNONE_UNONE_IMM, vshrntq_n_u, v8hi, v4si) > VAR2 (TERNOP_UNONE_UNONE_UNONE_IMM, vshrnbq_n_u, v8hi, v4si) > @@ -394,17 +394,17 @@ VAR2 (TERNOP_UNONE_UNONE_UNONE_IMM, vrshrnbq_n_u, v8hi, v4si) > VAR2 (TERNOP_UNONE_UNONE_UNONE_IMM, vqshrntq_n_u, v8hi, v4si) > VAR2 (TERNOP_UNONE_UNONE_UNONE_IMM, vqshrnbq_n_u, v8hi, v4si) > VAR2 (TERNOP_UNONE_UNONE_UNONE_IMM, vqrshrntq_n_u, v8hi, v4si) > -VAR2 (TERNOP_UNONE_UNONE_NONE_UNONE, vqmovuntq_m_s, v8hi, v4si) > -VAR2 (TERNOP_UNONE_UNONE_NONE_UNONE, vqmovunbq_m_s, v8hi, v4si) > -VAR2 (TERNOP_UNONE_UNONE_NONE_UNONE, vcvtq_m_from_f_u, v8hi, v4si) > -VAR2 (TERNOP_UNONE_UNONE_NONE_UNONE, vcvtpq_m_u, v8hi, v4si) > -VAR2 (TERNOP_UNONE_UNONE_NONE_UNONE, vcvtnq_m_u, v8hi, v4si) > -VAR2 (TERNOP_UNONE_UNONE_NONE_UNONE, vcvtmq_m_u, v8hi, v4si) > +VAR2 (TERNOP_UNONE_UNONE_NONE_PRED, vqmovuntq_m_s, v8hi, v4si) > +VAR2 (TERNOP_UNONE_UNONE_NONE_PRED, vqmovunbq_m_s, v8hi, v4si) > +VAR2 (TERNOP_UNONE_UNONE_NONE_PRED, vcvtq_m_from_f_u, v8hi, v4si) > +VAR2 (TERNOP_UNONE_UNONE_NONE_PRED, vcvtpq_m_u, v8hi, v4si) > +VAR2 (TERNOP_UNONE_UNONE_NONE_PRED, vcvtnq_m_u, v8hi, v4si) > +VAR2 (TERNOP_UNONE_UNONE_NONE_PRED, vcvtmq_m_u, v8hi, v4si) > VAR2 (TERNOP_UNONE_UNONE_NONE_IMM, vqshruntq_n_s, v8hi, v4si) > VAR2 (TERNOP_UNONE_UNONE_NONE_IMM, vqshrunbq_n_s, v8hi, v4si) > VAR2 (TERNOP_UNONE_UNONE_NONE_IMM, vqrshruntq_n_s, v8hi, v4si) > -VAR2 (TERNOP_UNONE_UNONE_IMM_UNONE, vorrq_m_n_u, v8hi, v4si) > -VAR2 (TERNOP_UNONE_UNONE_IMM_UNONE, vmvnq_m_n_u, v8hi, v4si) > +VAR2 (TERNOP_UNONE_UNONE_IMM_PRED, vorrq_m_n_u, v8hi, v4si) > +VAR2 (TERNOP_UNONE_UNONE_IMM_PRED, vmvnq_m_n_u, v8hi, v4si) > VAR2 (TERNOP_PRED_NONE_NONE_PRED, vcmpneq_m_n_f, v8hf, v4sf) > VAR2 (TERNOP_PRED_NONE_NONE_PRED, vcmpneq_m_f, v8hf, v4sf) > VAR2 (TERNOP_PRED_NONE_NONE_PRED, vcmpltq_m_n_f, v8hf, v4sf) > @@ -416,38 +416,38 @@ VAR2 (TERNOP_PRED_NONE_NONE_PRED, vcmpgtq_m_f, v8hf, v4sf) > VAR2 (TERNOP_PRED_NONE_NONE_PRED, vcmpgeq_m_n_f, v8hf, v4sf) > VAR2 (TERNOP_PRED_NONE_NONE_PRED, vcmpgeq_m_f, v8hf, v4sf) > VAR2 (TERNOP_PRED_NONE_NONE_PRED, vcmpeqq_m_n_f, v8hf, v4sf) > -VAR2 (TERNOP_NONE_NONE_NONE_UNONE, vrndxq_m_f, v8hf, v4sf) > -VAR2 (TERNOP_NONE_NONE_NONE_UNONE, vrndq_m_f, v8hf, v4sf) > -VAR2 (TERNOP_NONE_NONE_NONE_UNONE, vrndpq_m_f, v8hf, v4sf) > -VAR2 (TERNOP_NONE_NONE_NONE_UNONE, vrndnq_m_f, v8hf, v4sf) > -VAR2 (TERNOP_NONE_NONE_NONE_UNONE, vrndmq_m_f, v8hf, v4sf) > -VAR2 (TERNOP_NONE_NONE_NONE_UNONE, vrndaq_m_f, v8hf, v4sf) > -VAR2 (TERNOP_NONE_NONE_NONE_UNONE, vrev64q_m_f, v8hf, v4sf) > -VAR2 (TERNOP_NONE_NONE_NONE_UNONE, vrev32q_m_s, v16qi, v8hi) > -VAR2 (TERNOP_NONE_NONE_NONE_UNONE, vqmovntq_m_s, v8hi, v4si) > -VAR2 (TERNOP_NONE_NONE_NONE_UNONE, vqmovnbq_m_s, v8hi, v4si) > +VAR2 (TERNOP_NONE_NONE_NONE_PRED, vrndxq_m_f, v8hf, v4sf) > +VAR2 (TERNOP_NONE_NONE_NONE_PRED, vrndq_m_f, v8hf, v4sf) > +VAR2 (TERNOP_NONE_NONE_NONE_PRED, vrndpq_m_f, v8hf, v4sf) > +VAR2 (TERNOP_NONE_NONE_NONE_PRED, vrndnq_m_f, v8hf, v4sf) > +VAR2 (TERNOP_NONE_NONE_NONE_PRED, vrndmq_m_f, v8hf, v4sf) > +VAR2 (TERNOP_NONE_NONE_NONE_PRED, vrndaq_m_f, v8hf, v4sf) > +VAR2 (TERNOP_NONE_NONE_NONE_PRED, vrev64q_m_f, v8hf, v4sf) > +VAR2 (TERNOP_NONE_NONE_NONE_PRED, vrev32q_m_s, v16qi, v8hi) > +VAR2 (TERNOP_NONE_NONE_NONE_PRED, vqmovntq_m_s, v8hi, v4si) > +VAR2 (TERNOP_NONE_NONE_NONE_PRED, vqmovnbq_m_s, v8hi, v4si) > VAR2 (TERNOP_NONE_NONE_NONE_PRED, vpselq_f, v8hf, v4sf) > -VAR2 (TERNOP_NONE_NONE_NONE_UNONE, vnegq_m_f, v8hf, v4sf) > -VAR2 (TERNOP_NONE_NONE_NONE_UNONE, vmovntq_m_s, v8hi, v4si) > -VAR2 (TERNOP_NONE_NONE_NONE_UNONE, vmovnbq_m_s, v8hi, v4si) > -VAR2 (TERNOP_NONE_NONE_NONE_UNONE, vmovltq_m_s, v16qi, v8hi) > -VAR2 (TERNOP_NONE_NONE_NONE_UNONE, vmovlbq_m_s, v16qi, v8hi) > -VAR2 (TERNOP_NONE_NONE_NONE_UNONE, vmlsldavxq_p_s, v8hi, v4si) > -VAR2 (TERNOP_NONE_NONE_NONE_UNONE, vmlsldavq_p_s, v8hi, v4si) > -VAR2 (TERNOP_NONE_NONE_NONE_UNONE, vmlaldavxq_p_s, v8hi, v4si) > -VAR2 (TERNOP_NONE_NONE_NONE_UNONE, vmlaldavq_p_s, v8hi, v4si) > -VAR2 (TERNOP_NONE_NONE_NONE_UNONE, vminnmvq_p_f, v8hf, v4sf) > -VAR2 (TERNOP_NONE_NONE_NONE_UNONE, vminnmavq_p_f, v8hf, v4sf) > -VAR2 (TERNOP_NONE_NONE_NONE_UNONE, vminnmaq_m_f, v8hf, v4sf) > -VAR2 (TERNOP_NONE_NONE_NONE_UNONE, vmaxnmvq_p_f, v8hf, v4sf) > -VAR2 (TERNOP_NONE_NONE_NONE_UNONE, vmaxnmavq_p_f, v8hf, v4sf) > -VAR2 (TERNOP_NONE_NONE_NONE_UNONE, vmaxnmaq_m_f, v8hf, v4sf) > -VAR2 (TERNOP_NONE_NONE_NONE_UNONE, vdupq_m_n_f, v8hf, v4sf) > -VAR2 (TERNOP_NONE_NONE_NONE_UNONE, vcvtq_m_from_f_s, v8hi, v4si) > -VAR2 (TERNOP_NONE_NONE_NONE_UNONE, vcvtpq_m_s, v8hi, v4si) > -VAR2 (TERNOP_NONE_NONE_NONE_UNONE, vcvtnq_m_s, v8hi, v4si) > -VAR2 (TERNOP_NONE_NONE_NONE_UNONE, vcvtmq_m_s, v8hi, v4si) > -VAR2 (TERNOP_NONE_NONE_NONE_UNONE, vabsq_m_f, v8hf, v4sf) > +VAR2 (TERNOP_NONE_NONE_NONE_PRED, vnegq_m_f, v8hf, v4sf) > +VAR2 (TERNOP_NONE_NONE_NONE_PRED, vmovntq_m_s, v8hi, v4si) > +VAR2 (TERNOP_NONE_NONE_NONE_PRED, vmovnbq_m_s, v8hi, v4si) > +VAR2 (TERNOP_NONE_NONE_NONE_PRED, vmovltq_m_s, v16qi, v8hi) > +VAR2 (TERNOP_NONE_NONE_NONE_PRED, vmovlbq_m_s, v16qi, v8hi) > +VAR2 (TERNOP_NONE_NONE_NONE_PRED, vmlsldavxq_p_s, v8hi, v4si) > +VAR2 (TERNOP_NONE_NONE_NONE_PRED, vmlsldavq_p_s, v8hi, v4si) > +VAR2 (TERNOP_NONE_NONE_NONE_PRED, vmlaldavxq_p_s, v8hi, v4si) > +VAR2 (TERNOP_NONE_NONE_NONE_PRED, vmlaldavq_p_s, v8hi, v4si) > +VAR2 (TERNOP_NONE_NONE_NONE_PRED, vminnmvq_p_f, v8hf, v4sf) > +VAR2 (TERNOP_NONE_NONE_NONE_PRED, vminnmavq_p_f, v8hf, v4sf) > +VAR2 (TERNOP_NONE_NONE_NONE_PRED, vminnmaq_m_f, v8hf, v4sf) > +VAR2 (TERNOP_NONE_NONE_NONE_PRED, vmaxnmvq_p_f, v8hf, v4sf) > +VAR2 (TERNOP_NONE_NONE_NONE_PRED, vmaxnmavq_p_f, v8hf, v4sf) > +VAR2 (TERNOP_NONE_NONE_NONE_PRED, vmaxnmaq_m_f, v8hf, v4sf) > +VAR2 (TERNOP_NONE_NONE_NONE_PRED, vdupq_m_n_f, v8hf, v4sf) > +VAR2 (TERNOP_NONE_NONE_NONE_PRED, vcvtq_m_from_f_s, v8hi, v4si) > +VAR2 (TERNOP_NONE_NONE_NONE_PRED, vcvtpq_m_s, v8hi, v4si) > +VAR2 (TERNOP_NONE_NONE_NONE_PRED, vcvtnq_m_s, v8hi, v4si) > +VAR2 (TERNOP_NONE_NONE_NONE_PRED, vcvtmq_m_s, v8hi, v4si) > +VAR2 (TERNOP_NONE_NONE_NONE_PRED, vabsq_m_f, v8hf, v4sf) > VAR2 (TERNOP_NONE_NONE_NONE_NONE, vmlsldavaxq_s, v8hi, v4si) > VAR2 (TERNOP_NONE_NONE_NONE_NONE, vmlsldavaq_s, v8hi, v4si) > VAR2 (TERNOP_NONE_NONE_NONE_NONE, vmlaldavaxq_s, v8hi, v4si) > @@ -463,8 +463,8 @@ VAR2 (TERNOP_NONE_NONE_NONE_IMM, vrshrnbq_n_s, v8hi, v4si) > VAR2 (TERNOP_NONE_NONE_NONE_IMM, vqshrntq_n_s, v8hi, v4si) > VAR2 (TERNOP_NONE_NONE_NONE_IMM, vqshrnbq_n_s, v8hi, v4si) > VAR2 (TERNOP_NONE_NONE_NONE_IMM, vqrshrntq_n_s, v8hi, v4si) > -VAR2 (TERNOP_NONE_NONE_IMM_UNONE, vorrq_m_n_s, v8hi, v4si) > -VAR2 (TERNOP_NONE_NONE_IMM_UNONE, vmvnq_m_n_s, v8hi, v4si) > +VAR2 (TERNOP_NONE_NONE_IMM_PRED, vorrq_m_n_s, v8hi, v4si) > +VAR2 (TERNOP_NONE_NONE_IMM_PRED, vmvnq_m_n_s, v8hi, v4si) > VAR1 (TERNOP_UNONE_UNONE_UNONE_UNONE, vrmlaldavhq_p_u, v4si) > VAR1 (TERNOP_UNONE_UNONE_UNONE_UNONE, vrev16q_m_u, v16qi) > VAR1 (TERNOP_UNONE_UNONE_UNONE_UNONE, vaddlvaq_p_u, v4si) > @@ -482,189 +482,189 @@ VAR1 (TERNOP_NONE_NONE_NONE_UNONE, vaddlvaq_p_s, v4si) > VAR1 (TERNOP_NONE_NONE_NONE_NONE, vrmlsldavhaxq_s, v4si) > VAR1 (TERNOP_NONE_NONE_NONE_NONE, vrmlsldavhaq_s, v4si) > VAR1 (TERNOP_NONE_NONE_NONE_NONE, vrmlaldavhaxq_s, v4si) > -VAR3 (QUADOP_NONE_NONE_NONE_IMM_UNONE, vsriq_m_n_s, v16qi, v8hi, v4si) > -VAR3 (QUADOP_UNONE_UNONE_UNONE_IMM_UNONE, vsriq_m_n_u, v16qi, v8hi, v4si) > -VAR3 (QUADOP_NONE_NONE_NONE_NONE_UNONE, vsubq_m_s, v16qi, v8hi, v4si) > -VAR3 (QUADOP_UNONE_UNONE_UNONE_UNONE_UNONE, vsubq_m_u, v16qi, v8hi, v4si) > -VAR2 (QUADOP_NONE_NONE_UNONE_IMM_UNONE, vcvtq_m_n_to_f_u, v8hf, v4sf) > -VAR2 (QUADOP_NONE_NONE_NONE_IMM_UNONE, vcvtq_m_n_to_f_s, v8hf, v4sf) > -VAR3 (QUADOP_UNONE_UNONE_NONE_IMM_UNONE, vqshluq_m_n_s, v16qi, v8hi, v4si) > -VAR3 (QUADOP_UNONE_UNONE_NONE_NONE_UNONE, vabavq_p_s, v16qi, v8hi, v4si) > -VAR3 (QUADOP_UNONE_UNONE_UNONE_UNONE_UNONE, vabavq_p_u, v16qi, v8hi, v4si) > -VAR3 (QUADOP_UNONE_UNONE_UNONE_NONE_UNONE, vshlq_m_u, v16qi, v8hi, v4si) > -VAR3 (QUADOP_NONE_NONE_NONE_NONE_UNONE, vshlq_m_s, v16qi, v8hi, v4si) > -VAR3 (QUADOP_UNONE_UNONE_UNONE_UNONE_UNONE, vsubq_m_n_u, v16qi, v8hi, v4si) > -VAR3 (QUADOP_UNONE_UNONE_UNONE_UNONE_UNONE, vrmulhq_m_u, v16qi, v8hi, v4si) > -VAR3 (QUADOP_UNONE_UNONE_UNONE_UNONE_UNONE, vrhaddq_m_u, v16qi, v8hi, v4si) > -VAR3 (QUADOP_UNONE_UNONE_UNONE_UNONE_UNONE, vqsubq_m_u, v16qi, v8hi, v4si) > -VAR3 (QUADOP_UNONE_UNONE_UNONE_UNONE_UNONE, vqsubq_m_n_u, v16qi, v8hi, v4si) > -VAR3 (QUADOP_UNONE_UNONE_UNONE_UNONE_UNONE, vqaddq_m_u, v16qi, v8hi, v4si) > -VAR3 (QUADOP_UNONE_UNONE_UNONE_UNONE_UNONE, vqaddq_m_n_u, v16qi, v8hi, v4si) > -VAR3 (QUADOP_UNONE_UNONE_UNONE_UNONE_UNONE, vorrq_m_u, v16qi, v8hi, v4si) > -VAR3 (QUADOP_UNONE_UNONE_UNONE_UNONE_UNONE, vornq_m_u, v16qi, v8hi, v4si) > -VAR3 (QUADOP_UNONE_UNONE_UNONE_UNONE_UNONE, vmulq_m_u, v16qi, v8hi, v4si) > -VAR3 (QUADOP_UNONE_UNONE_UNONE_UNONE_UNONE, vmulq_m_n_u, v16qi, v8hi, v4si) > -VAR3 (QUADOP_UNONE_UNONE_UNONE_UNONE_UNONE, vmulltq_int_m_u, v16qi, v8hi, v4si) > -VAR3 (QUADOP_UNONE_UNONE_UNONE_UNONE_UNONE, vmullbq_int_m_u, v16qi, v8hi, v4si) > -VAR3 (QUADOP_UNONE_UNONE_UNONE_UNONE_UNONE, vmulhq_m_u, v16qi, v8hi, v4si) > -VAR3 (QUADOP_UNONE_UNONE_UNONE_UNONE_UNONE, vmlasq_m_n_u, v16qi, v8hi, v4si) > -VAR3 (QUADOP_UNONE_UNONE_UNONE_UNONE_UNONE, vmlaq_m_n_u, v16qi, v8hi, v4si) > -VAR3 (QUADOP_UNONE_UNONE_UNONE_UNONE_UNONE, vmladavaq_p_u, v16qi, v8hi, v4si) > -VAR3 (QUADOP_UNONE_UNONE_UNONE_UNONE_UNONE, vminq_m_u, v16qi, v8hi, v4si) > -VAR3 (QUADOP_UNONE_UNONE_UNONE_UNONE_UNONE, vmaxq_m_u, v16qi, v8hi, v4si) > -VAR3 (QUADOP_UNONE_UNONE_UNONE_UNONE_UNONE, vhsubq_m_u, v16qi, v8hi, v4si) > -VAR3 (QUADOP_UNONE_UNONE_UNONE_UNONE_UNONE, vhsubq_m_n_u, v16qi, v8hi, v4si) > -VAR3 (QUADOP_UNONE_UNONE_UNONE_UNONE_UNONE, vhaddq_m_u, v16qi, v8hi, v4si) > -VAR3 (QUADOP_UNONE_UNONE_UNONE_UNONE_UNONE, vhaddq_m_n_u, v16qi, v8hi, v4si) > -VAR3 (QUADOP_UNONE_UNONE_UNONE_UNONE_UNONE, veorq_m_u, v16qi, v8hi, v4si) > -VAR3 (QUADOP_UNONE_UNONE_UNONE_UNONE_UNONE, vcaddq_rot90_m_u, v16qi, v8hi, v4si) > -VAR3 (QUADOP_UNONE_UNONE_UNONE_UNONE_UNONE, vcaddq_rot270_m_u, v16qi, v8hi, v4si) > -VAR3 (QUADOP_UNONE_UNONE_UNONE_UNONE_UNONE, vbicq_m_u, v16qi, v8hi, v4si) > -VAR3 (QUADOP_UNONE_UNONE_UNONE_UNONE_UNONE, vandq_m_u, v16qi, v8hi, v4si) > -VAR3 (QUADOP_UNONE_UNONE_UNONE_UNONE_UNONE, vaddq_m_u, v16qi, v8hi, v4si) > -VAR3 (QUADOP_UNONE_UNONE_UNONE_UNONE_UNONE, vaddq_m_n_u, v16qi, v8hi, v4si) > -VAR3 (QUADOP_UNONE_UNONE_UNONE_UNONE_UNONE, vabdq_m_u, v16qi, v8hi, v4si) > -VAR3 (QUADOP_UNONE_UNONE_UNONE_NONE_UNONE, vrshlq_m_u, v16qi, v8hi, v4si) > -VAR3 (QUADOP_UNONE_UNONE_UNONE_NONE_UNONE, vqshlq_m_u, v16qi, v8hi, v4si) > -VAR3 (QUADOP_UNONE_UNONE_UNONE_NONE_UNONE, vqrshlq_m_u, v16qi, v8hi, v4si) > -VAR3 (QUADOP_UNONE_UNONE_UNONE_NONE_UNONE, vbrsrq_m_n_u, v16qi, v8hi, v4si) > -VAR3 (QUADOP_UNONE_UNONE_UNONE_IMM_UNONE, vsliq_m_n_u, v16qi, v8hi, v4si) > -VAR3 (QUADOP_UNONE_UNONE_UNONE_IMM_UNONE, vshrq_m_n_u, v16qi, v8hi, v4si) > -VAR3 (QUADOP_UNONE_UNONE_UNONE_IMM_UNONE, vshlq_m_n_u, v16qi, v8hi, v4si) > -VAR3 (QUADOP_UNONE_UNONE_UNONE_IMM_UNONE, vrshrq_m_n_u, v16qi, v8hi, v4si) > -VAR3 (QUADOP_UNONE_UNONE_UNONE_IMM_UNONE, vqshlq_m_n_u, v16qi, v8hi, v4si) > -VAR3 (QUADOP_NONE_NONE_NONE_NONE_UNONE, vsubq_m_n_s, v16qi, v8hi, v4si) > -VAR3 (QUADOP_NONE_NONE_NONE_NONE_UNONE, vrshlq_m_s, v16qi, v8hi, v4si) > -VAR3 (QUADOP_NONE_NONE_NONE_NONE_UNONE, vrmulhq_m_s, v16qi, v8hi, v4si) > -VAR3 (QUADOP_NONE_NONE_NONE_NONE_UNONE, vrhaddq_m_s, v16qi, v8hi, v4si) > -VAR3 (QUADOP_NONE_NONE_NONE_NONE_UNONE, vqsubq_m_s, v16qi, v8hi, v4si) > -VAR3 (QUADOP_NONE_NONE_NONE_NONE_UNONE, vqsubq_m_n_s, v16qi, v8hi, v4si) > -VAR3 (QUADOP_NONE_NONE_NONE_NONE_UNONE, vqshlq_m_s, v16qi, v8hi, v4si) > -VAR3 (QUADOP_NONE_NONE_NONE_NONE_UNONE, vqrshlq_m_s, v16qi, v8hi, v4si) > -VAR3 (QUADOP_NONE_NONE_NONE_NONE_UNONE, vqrdmulhq_m_s, v16qi, v8hi, v4si) > -VAR3 (QUADOP_NONE_NONE_NONE_NONE_UNONE, vqrdmulhq_m_n_s, v16qi, v8hi, v4si) > -VAR3 (QUADOP_NONE_NONE_NONE_NONE_UNONE, vqrdmlsdhxq_m_s, v16qi, v8hi, v4si) > -VAR3 (QUADOP_NONE_NONE_NONE_NONE_UNONE, vqrdmlsdhq_m_s, v16qi, v8hi, v4si) > -VAR3 (QUADOP_NONE_NONE_NONE_NONE_UNONE, vqrdmlashq_m_n_s, v16qi, v8hi, v4si) > -VAR3 (QUADOP_NONE_NONE_NONE_NONE_UNONE, vqrdmlahq_m_n_s, v16qi, v8hi, v4si) > -VAR3 (QUADOP_NONE_NONE_NONE_NONE_UNONE, vqrdmladhxq_m_s, v16qi, v8hi, v4si) > -VAR3 (QUADOP_NONE_NONE_NONE_NONE_UNONE, vqrdmladhq_m_s, v16qi, v8hi, v4si) > -VAR3 (QUADOP_NONE_NONE_NONE_NONE_UNONE, vqdmulhq_m_s, v16qi, v8hi, v4si) > -VAR3 (QUADOP_NONE_NONE_NONE_NONE_UNONE, vqdmulhq_m_n_s, v16qi, v8hi, v4si) > -VAR3 (QUADOP_NONE_NONE_NONE_NONE_UNONE, vqdmlsdhxq_m_s, v16qi, v8hi, v4si) > -VAR3 (QUADOP_NONE_NONE_NONE_NONE_UNONE, vqdmlsdhq_m_s, v16qi, v8hi, v4si) > -VAR3 (QUADOP_NONE_NONE_NONE_NONE_UNONE, vqdmlahq_m_n_s, v16qi, v8hi, v4si) > -VAR3 (QUADOP_NONE_NONE_NONE_NONE_UNONE, vqdmlashq_m_n_s, v16qi, v8hi, v4si) > -VAR3 (QUADOP_NONE_NONE_NONE_NONE_UNONE, vqdmladhxq_m_s, v16qi, v8hi, v4si) > -VAR3 (QUADOP_NONE_NONE_NONE_NONE_UNONE, vqdmladhq_m_s, v16qi, v8hi, v4si) > -VAR3 (QUADOP_NONE_NONE_NONE_NONE_UNONE, vqaddq_m_s, v16qi, v8hi, v4si) > -VAR3 (QUADOP_NONE_NONE_NONE_NONE_UNONE, vqaddq_m_n_s, v16qi, v8hi, v4si) > -VAR3 (QUADOP_NONE_NONE_NONE_NONE_UNONE, vorrq_m_s, v16qi, v8hi, v4si) > -VAR3 (QUADOP_NONE_NONE_NONE_NONE_UNONE, vornq_m_s, v16qi, v8hi, v4si) > -VAR3 (QUADOP_NONE_NONE_NONE_NONE_UNONE, vmulq_m_s, v16qi, v8hi, v4si) > -VAR3 (QUADOP_NONE_NONE_NONE_NONE_UNONE, vmulq_m_n_s, v16qi, v8hi, v4si) > -VAR3 (QUADOP_NONE_NONE_NONE_NONE_UNONE, vmulltq_int_m_s, v16qi, v8hi, v4si) > -VAR3 (QUADOP_NONE_NONE_NONE_NONE_UNONE, vmullbq_int_m_s, v16qi, v8hi, v4si) > -VAR3 (QUADOP_NONE_NONE_NONE_NONE_UNONE, vmulhq_m_s, v16qi, v8hi, v4si) > -VAR3 (QUADOP_NONE_NONE_NONE_NONE_UNONE, vmlsdavaxq_p_s, v16qi, v8hi, v4si) > -VAR3 (QUADOP_NONE_NONE_NONE_NONE_UNONE, vmlsdavaq_p_s, v16qi, v8hi, v4si) > -VAR3 (QUADOP_NONE_NONE_NONE_NONE_UNONE, vmlasq_m_n_s, v16qi, v8hi, v4si) > -VAR3 (QUADOP_NONE_NONE_NONE_NONE_UNONE, vmlaq_m_n_s, v16qi, v8hi, v4si) > -VAR3 (QUADOP_NONE_NONE_NONE_NONE_UNONE, vmladavaxq_p_s, v16qi, v8hi, v4si) > -VAR3 (QUADOP_NONE_NONE_NONE_NONE_UNONE, vmladavaq_p_s, v16qi, v8hi, v4si) > -VAR3 (QUADOP_NONE_NONE_NONE_NONE_UNONE, vminq_m_s, v16qi, v8hi, v4si) > -VAR3 (QUADOP_NONE_NONE_NONE_NONE_UNONE, vmaxq_m_s, v16qi, v8hi, v4si) > -VAR3 (QUADOP_NONE_NONE_NONE_NONE_UNONE, vhsubq_m_s, v16qi, v8hi, v4si) > -VAR3 (QUADOP_NONE_NONE_NONE_NONE_UNONE, vhsubq_m_n_s, v16qi, v8hi, v4si) > -VAR3 (QUADOP_NONE_NONE_NONE_NONE_UNONE, vhcaddq_rot90_m_s, v16qi, v8hi, v4si) > -VAR3 (QUADOP_NONE_NONE_NONE_NONE_UNONE, vhcaddq_rot270_m_s, v16qi, v8hi, v4si) > -VAR3 (QUADOP_NONE_NONE_NONE_NONE_UNONE, vhaddq_m_s, v16qi, v8hi, v4si) > -VAR3 (QUADOP_NONE_NONE_NONE_NONE_UNONE, vhaddq_m_n_s, v16qi, v8hi, v4si) > -VAR3 (QUADOP_NONE_NONE_NONE_NONE_UNONE, veorq_m_s, v16qi, v8hi, v4si) > -VAR3 (QUADOP_NONE_NONE_NONE_NONE_UNONE, vcaddq_rot90_m_s, v16qi, v8hi, v4si) > -VAR3 (QUADOP_NONE_NONE_NONE_NONE_UNONE, vcaddq_rot270_m_s, v16qi, v8hi, v4si) > -VAR3 (QUADOP_NONE_NONE_NONE_NONE_UNONE, vbrsrq_m_n_s, v16qi, v8hi, v4si) > -VAR3 (QUADOP_NONE_NONE_NONE_NONE_UNONE, vbicq_m_s, v16qi, v8hi, v4si) > -VAR3 (QUADOP_NONE_NONE_NONE_NONE_UNONE, vandq_m_s, v16qi, v8hi, v4si) > -VAR3 (QUADOP_NONE_NONE_NONE_NONE_UNONE, vaddq_m_s, v16qi, v8hi, v4si) > -VAR3 (QUADOP_NONE_NONE_NONE_NONE_UNONE, vaddq_m_n_s, v16qi, v8hi, v4si) > -VAR3 (QUADOP_NONE_NONE_NONE_NONE_UNONE, vabdq_m_s, v16qi, v8hi, v4si) > -VAR3 (QUADOP_NONE_NONE_NONE_IMM_UNONE, vsliq_m_n_s, v16qi, v8hi, v4si) > -VAR3 (QUADOP_NONE_NONE_NONE_IMM_UNONE, vshrq_m_n_s, v16qi, v8hi, v4si) > -VAR3 (QUADOP_NONE_NONE_NONE_IMM_UNONE, vshlq_m_n_s, v16qi, v8hi, v4si) > -VAR3 (QUADOP_NONE_NONE_NONE_IMM_UNONE, vrshrq_m_n_s, v16qi, v8hi, v4si) > -VAR3 (QUADOP_NONE_NONE_NONE_IMM_UNONE, vqshlq_m_n_s, v16qi, v8hi, v4si) > -VAR2 (QUADOP_UNONE_UNONE_UNONE_UNONE_UNONE, vmulltq_poly_m_p, v16qi, v8hi) > -VAR2 (QUADOP_UNONE_UNONE_UNONE_UNONE_UNONE, vmullbq_poly_m_p, v16qi, v8hi) > -VAR2 (QUADOP_UNONE_UNONE_UNONE_UNONE_UNONE, vmlaldavaq_p_u, v8hi, v4si) > -VAR2 (QUADOP_UNONE_UNONE_UNONE_IMM_UNONE, vshrntq_m_n_u, v8hi, v4si) > -VAR2 (QUADOP_UNONE_UNONE_UNONE_IMM_UNONE, vshrnbq_m_n_u, v8hi, v4si) > -VAR2 (QUADOP_UNONE_UNONE_UNONE_IMM_UNONE, vshlltq_m_n_u, v16qi, v8hi) > -VAR2 (QUADOP_UNONE_UNONE_UNONE_IMM_UNONE, vshllbq_m_n_u, v16qi, v8hi) > -VAR2 (QUADOP_UNONE_UNONE_UNONE_IMM_UNONE, vrshrntq_m_n_u, v8hi, v4si) > -VAR2 (QUADOP_UNONE_UNONE_UNONE_IMM_UNONE, vrshrnbq_m_n_u, v8hi, v4si) > -VAR2 (QUADOP_UNONE_UNONE_UNONE_IMM_UNONE, vqshrntq_m_n_u, v8hi, v4si) > -VAR2 (QUADOP_UNONE_UNONE_UNONE_IMM_UNONE, vqshrnbq_m_n_u, v8hi, v4si) > -VAR2 (QUADOP_UNONE_UNONE_UNONE_IMM_UNONE, vqrshrntq_m_n_u, v8hi, v4si) > -VAR2 (QUADOP_UNONE_UNONE_UNONE_IMM_UNONE, vqrshrnbq_m_n_u, v8hi, v4si) > -VAR2 (QUADOP_UNONE_UNONE_NONE_IMM_UNONE, vqshruntq_m_n_s, v8hi, v4si) > -VAR2 (QUADOP_UNONE_UNONE_NONE_IMM_UNONE, vqshrunbq_m_n_s, v8hi, v4si) > -VAR2 (QUADOP_UNONE_UNONE_NONE_IMM_UNONE, vqrshruntq_m_n_s, v8hi, v4si) > -VAR2 (QUADOP_UNONE_UNONE_NONE_IMM_UNONE, vqrshrunbq_m_n_s, v8hi, v4si) > -VAR2 (QUADOP_NONE_NONE_NONE_NONE_UNONE, vqdmulltq_m_s, v8hi, v4si) > -VAR2 (QUADOP_NONE_NONE_NONE_NONE_UNONE, vqdmulltq_m_n_s, v8hi, v4si) > -VAR2 (QUADOP_NONE_NONE_NONE_NONE_UNONE, vqdmullbq_m_s, v8hi, v4si) > -VAR2 (QUADOP_NONE_NONE_NONE_NONE_UNONE, vqdmullbq_m_n_s, v8hi, v4si) > -VAR2 (QUADOP_NONE_NONE_NONE_NONE_UNONE, vmlsldavaxq_p_s, v8hi, v4si) > -VAR2 (QUADOP_NONE_NONE_NONE_NONE_UNONE, vmlsldavaq_p_s, v8hi, v4si) > -VAR2 (QUADOP_NONE_NONE_NONE_NONE_UNONE, vmlaldavaxq_p_s, v8hi, v4si) > -VAR2 (QUADOP_NONE_NONE_NONE_NONE_UNONE, vmlaldavaq_p_s, v8hi, v4si) > -VAR2 (QUADOP_NONE_NONE_NONE_IMM_UNONE, vshrntq_m_n_s, v8hi, v4si) > -VAR2 (QUADOP_NONE_NONE_NONE_IMM_UNONE, vshrnbq_m_n_s, v8hi, v4si) > -VAR2 (QUADOP_NONE_NONE_NONE_IMM_UNONE, vshlltq_m_n_s, v16qi, v8hi) > -VAR2 (QUADOP_NONE_NONE_NONE_IMM_UNONE, vshllbq_m_n_s, v16qi, v8hi) > -VAR2 (QUADOP_NONE_NONE_NONE_IMM_UNONE, vrshrntq_m_n_s, v8hi, v4si) > -VAR2 (QUADOP_NONE_NONE_NONE_IMM_UNONE, vrshrnbq_m_n_s, v8hi, v4si) > -VAR2 (QUADOP_NONE_NONE_NONE_IMM_UNONE, vqshrntq_m_n_s, v8hi, v4si) > -VAR2 (QUADOP_NONE_NONE_NONE_IMM_UNONE, vqshrnbq_m_n_s, v8hi, v4si) > -VAR2 (QUADOP_NONE_NONE_NONE_IMM_UNONE, vqrshrntq_m_n_s, v8hi, v4si) > -VAR2 (QUADOP_NONE_NONE_NONE_IMM_UNONE, vqrshrnbq_m_n_s, v8hi, v4si) > +VAR3 (QUADOP_NONE_NONE_NONE_IMM_PRED, vsriq_m_n_s, v16qi, v8hi, v4si) > +VAR3 (QUADOP_UNONE_UNONE_UNONE_IMM_PRED, vsriq_m_n_u, v16qi, v8hi, v4si) > +VAR3 (QUADOP_NONE_NONE_NONE_NONE_PRED, vsubq_m_s, v16qi, v8hi, v4si) > +VAR3 (QUADOP_UNONE_UNONE_UNONE_UNONE_PRED, vsubq_m_u, v16qi, v8hi, v4si) > +VAR2 (QUADOP_NONE_NONE_UNONE_IMM_PRED, vcvtq_m_n_to_f_u, v8hf, v4sf) > +VAR2 (QUADOP_NONE_NONE_NONE_IMM_PRED, vcvtq_m_n_to_f_s, v8hf, v4sf) > +VAR3 (QUADOP_UNONE_UNONE_NONE_IMM_PRED, vqshluq_m_n_s, v16qi, v8hi, v4si) > +VAR3 (QUADOP_UNONE_UNONE_NONE_NONE_PRED, vabavq_p_s, v16qi, v8hi, v4si) > +VAR3 (QUADOP_UNONE_UNONE_UNONE_UNONE_PRED, vabavq_p_u, v16qi, v8hi, v4si) > +VAR3 (QUADOP_UNONE_UNONE_UNONE_NONE_PRED, vshlq_m_u, v16qi, v8hi, v4si) > +VAR3 (QUADOP_NONE_NONE_NONE_NONE_PRED, vshlq_m_s, v16qi, v8hi, v4si) > +VAR3 (QUADOP_UNONE_UNONE_UNONE_UNONE_PRED, vsubq_m_n_u, v16qi, v8hi, v4si) > +VAR3 (QUADOP_UNONE_UNONE_UNONE_UNONE_PRED, vrmulhq_m_u, v16qi, v8hi, v4si) > +VAR3 (QUADOP_UNONE_UNONE_UNONE_UNONE_PRED, vrhaddq_m_u, v16qi, v8hi, v4si) > +VAR3 (QUADOP_UNONE_UNONE_UNONE_UNONE_PRED, vqsubq_m_u, v16qi, v8hi, v4si) > +VAR3 (QUADOP_UNONE_UNONE_UNONE_UNONE_PRED, vqsubq_m_n_u, v16qi, v8hi, v4si) > +VAR3 (QUADOP_UNONE_UNONE_UNONE_UNONE_PRED, vqaddq_m_u, v16qi, v8hi, v4si) > +VAR3 (QUADOP_UNONE_UNONE_UNONE_UNONE_PRED, vqaddq_m_n_u, v16qi, v8hi, v4si) > +VAR3 (QUADOP_UNONE_UNONE_UNONE_UNONE_PRED, vorrq_m_u, v16qi, v8hi, v4si) > +VAR3 (QUADOP_UNONE_UNONE_UNONE_UNONE_PRED, vornq_m_u, v16qi, v8hi, v4si) > +VAR3 (QUADOP_UNONE_UNONE_UNONE_UNONE_PRED, vmulq_m_u, v16qi, v8hi, v4si) > +VAR3 (QUADOP_UNONE_UNONE_UNONE_UNONE_PRED, vmulq_m_n_u, v16qi, v8hi, v4si) > +VAR3 (QUADOP_UNONE_UNONE_UNONE_UNONE_PRED, vmulltq_int_m_u, v16qi, v8hi, v4si) > +VAR3 (QUADOP_UNONE_UNONE_UNONE_UNONE_PRED, vmullbq_int_m_u, v16qi, v8hi, v4si) > +VAR3 (QUADOP_UNONE_UNONE_UNONE_UNONE_PRED, vmulhq_m_u, v16qi, v8hi, v4si) > +VAR3 (QUADOP_UNONE_UNONE_UNONE_UNONE_PRED, vmlasq_m_n_u, v16qi, v8hi, v4si) > +VAR3 (QUADOP_UNONE_UNONE_UNONE_UNONE_PRED, vmlaq_m_n_u, v16qi, v8hi, v4si) > +VAR3 (QUADOP_UNONE_UNONE_UNONE_UNONE_PRED, vmladavaq_p_u, v16qi, v8hi, v4si) > +VAR3 (QUADOP_UNONE_UNONE_UNONE_UNONE_PRED, vminq_m_u, v16qi, v8hi, v4si) > +VAR3 (QUADOP_UNONE_UNONE_UNONE_UNONE_PRED, vmaxq_m_u, v16qi, v8hi, v4si) > +VAR3 (QUADOP_UNONE_UNONE_UNONE_UNONE_PRED, vhsubq_m_u, v16qi, v8hi, v4si) > +VAR3 (QUADOP_UNONE_UNONE_UNONE_UNONE_PRED, vhsubq_m_n_u, v16qi, v8hi, v4si) > +VAR3 (QUADOP_UNONE_UNONE_UNONE_UNONE_PRED, vhaddq_m_u, v16qi, v8hi, v4si) > +VAR3 (QUADOP_UNONE_UNONE_UNONE_UNONE_PRED, vhaddq_m_n_u, v16qi, v8hi, v4si) > +VAR3 (QUADOP_UNONE_UNONE_UNONE_UNONE_PRED, veorq_m_u, v16qi, v8hi, v4si) > +VAR3 (QUADOP_UNONE_UNONE_UNONE_UNONE_PRED, vcaddq_rot90_m_u, v16qi, v8hi, v4si) > +VAR3 (QUADOP_UNONE_UNONE_UNONE_UNONE_PRED, vcaddq_rot270_m_u, v16qi, v8hi, v4si) > +VAR3 (QUADOP_UNONE_UNONE_UNONE_UNONE_PRED, vbicq_m_u, v16qi, v8hi, v4si) > +VAR3 (QUADOP_UNONE_UNONE_UNONE_UNONE_PRED, vandq_m_u, v16qi, v8hi, v4si) > +VAR3 (QUADOP_UNONE_UNONE_UNONE_UNONE_PRED, vaddq_m_u, v16qi, v8hi, v4si) > +VAR3 (QUADOP_UNONE_UNONE_UNONE_UNONE_PRED, vaddq_m_n_u, v16qi, v8hi, v4si) > +VAR3 (QUADOP_UNONE_UNONE_UNONE_UNONE_PRED, vabdq_m_u, v16qi, v8hi, v4si) > +VAR3 (QUADOP_UNONE_UNONE_UNONE_NONE_PRED, vrshlq_m_u, v16qi, v8hi, v4si) > +VAR3 (QUADOP_UNONE_UNONE_UNONE_NONE_PRED, vqshlq_m_u, v16qi, v8hi, v4si) > +VAR3 (QUADOP_UNONE_UNONE_UNONE_NONE_PRED, vqrshlq_m_u, v16qi, v8hi, v4si) > +VAR3 (QUADOP_UNONE_UNONE_UNONE_NONE_PRED, vbrsrq_m_n_u, v16qi, v8hi, v4si) > +VAR3 (QUADOP_UNONE_UNONE_UNONE_IMM_PRED, vsliq_m_n_u, v16qi, v8hi, v4si) > +VAR3 (QUADOP_UNONE_UNONE_UNONE_IMM_PRED, vshrq_m_n_u, v16qi, v8hi, v4si) > +VAR3 (QUADOP_UNONE_UNONE_UNONE_IMM_PRED, vshlq_m_n_u, v16qi, v8hi, v4si) > +VAR3 (QUADOP_UNONE_UNONE_UNONE_IMM_PRED, vrshrq_m_n_u, v16qi, v8hi, v4si) > +VAR3 (QUADOP_UNONE_UNONE_UNONE_IMM_PRED, vqshlq_m_n_u, v16qi, v8hi, v4si) > +VAR3 (QUADOP_NONE_NONE_NONE_NONE_PRED, vsubq_m_n_s, v16qi, v8hi, v4si) > +VAR3 (QUADOP_NONE_NONE_NONE_NONE_PRED, vrshlq_m_s, v16qi, v8hi, v4si) > +VAR3 (QUADOP_NONE_NONE_NONE_NONE_PRED, vrmulhq_m_s, v16qi, v8hi, v4si) > +VAR3 (QUADOP_NONE_NONE_NONE_NONE_PRED, vrhaddq_m_s, v16qi, v8hi, v4si) > +VAR3 (QUADOP_NONE_NONE_NONE_NONE_PRED, vqsubq_m_s, v16qi, v8hi, v4si) > +VAR3 (QUADOP_NONE_NONE_NONE_NONE_PRED, vqsubq_m_n_s, v16qi, v8hi, v4si) > +VAR3 (QUADOP_NONE_NONE_NONE_NONE_PRED, vqshlq_m_s, v16qi, v8hi, v4si) > +VAR3 (QUADOP_NONE_NONE_NONE_NONE_PRED, vqrshlq_m_s, v16qi, v8hi, v4si) > +VAR3 (QUADOP_NONE_NONE_NONE_NONE_PRED, vqrdmulhq_m_s, v16qi, v8hi, v4si) > +VAR3 (QUADOP_NONE_NONE_NONE_NONE_PRED, vqrdmulhq_m_n_s, v16qi, v8hi, v4si) > +VAR3 (QUADOP_NONE_NONE_NONE_NONE_PRED, vqrdmlsdhxq_m_s, v16qi, v8hi, v4si) > +VAR3 (QUADOP_NONE_NONE_NONE_NONE_PRED, vqrdmlsdhq_m_s, v16qi, v8hi, v4si) > +VAR3 (QUADOP_NONE_NONE_NONE_NONE_PRED, vqrdmlashq_m_n_s, v16qi, v8hi, v4si) > +VAR3 (QUADOP_NONE_NONE_NONE_NONE_PRED, vqrdmlahq_m_n_s, v16qi, v8hi, v4si) > +VAR3 (QUADOP_NONE_NONE_NONE_NONE_PRED, vqrdmladhxq_m_s, v16qi, v8hi, v4si) > +VAR3 (QUADOP_NONE_NONE_NONE_NONE_PRED, vqrdmladhq_m_s, v16qi, v8hi, v4si) > +VAR3 (QUADOP_NONE_NONE_NONE_NONE_PRED, vqdmulhq_m_s, v16qi, v8hi, v4si) > +VAR3 (QUADOP_NONE_NONE_NONE_NONE_PRED, vqdmulhq_m_n_s, v16qi, v8hi, v4si) > +VAR3 (QUADOP_NONE_NONE_NONE_NONE_PRED, vqdmlsdhxq_m_s, v16qi, v8hi, v4si) > +VAR3 (QUADOP_NONE_NONE_NONE_NONE_PRED, vqdmlsdhq_m_s, v16qi, v8hi, v4si) > +VAR3 (QUADOP_NONE_NONE_NONE_NONE_PRED, vqdmlahq_m_n_s, v16qi, v8hi, v4si) > +VAR3 (QUADOP_NONE_NONE_NONE_NONE_PRED, vqdmlashq_m_n_s, v16qi, v8hi, v4si) > +VAR3 (QUADOP_NONE_NONE_NONE_NONE_PRED, vqdmladhxq_m_s, v16qi, v8hi, v4si) > +VAR3 (QUADOP_NONE_NONE_NONE_NONE_PRED, vqdmladhq_m_s, v16qi, v8hi, v4si) > +VAR3 (QUADOP_NONE_NONE_NONE_NONE_PRED, vqaddq_m_s, v16qi, v8hi, v4si) > +VAR3 (QUADOP_NONE_NONE_NONE_NONE_PRED, vqaddq_m_n_s, v16qi, v8hi, v4si) > +VAR3 (QUADOP_NONE_NONE_NONE_NONE_PRED, vorrq_m_s, v16qi, v8hi, v4si) > +VAR3 (QUADOP_NONE_NONE_NONE_NONE_PRED, vornq_m_s, v16qi, v8hi, v4si) > +VAR3 (QUADOP_NONE_NONE_NONE_NONE_PRED, vmulq_m_s, v16qi, v8hi, v4si) > +VAR3 (QUADOP_NONE_NONE_NONE_NONE_PRED, vmulq_m_n_s, v16qi, v8hi, v4si) > +VAR3 (QUADOP_NONE_NONE_NONE_NONE_PRED, vmulltq_int_m_s, v16qi, v8hi, v4si) > +VAR3 (QUADOP_NONE_NONE_NONE_NONE_PRED, vmullbq_int_m_s, v16qi, v8hi, v4si) > +VAR3 (QUADOP_NONE_NONE_NONE_NONE_PRED, vmulhq_m_s, v16qi, v8hi, v4si) > +VAR3 (QUADOP_NONE_NONE_NONE_NONE_PRED, vmlsdavaxq_p_s, v16qi, v8hi, v4si) > +VAR3 (QUADOP_NONE_NONE_NONE_NONE_PRED, vmlsdavaq_p_s, v16qi, v8hi, v4si) > +VAR3 (QUADOP_NONE_NONE_NONE_NONE_PRED, vmlasq_m_n_s, v16qi, v8hi, v4si) > +VAR3 (QUADOP_NONE_NONE_NONE_NONE_PRED, vmlaq_m_n_s, v16qi, v8hi, v4si) > +VAR3 (QUADOP_NONE_NONE_NONE_NONE_PRED, vmladavaxq_p_s, v16qi, v8hi, v4si) > +VAR3 (QUADOP_NONE_NONE_NONE_NONE_PRED, vmladavaq_p_s, v16qi, v8hi, v4si) > +VAR3 (QUADOP_NONE_NONE_NONE_NONE_PRED, vminq_m_s, v16qi, v8hi, v4si) > +VAR3 (QUADOP_NONE_NONE_NONE_NONE_PRED, vmaxq_m_s, v16qi, v8hi, v4si) > +VAR3 (QUADOP_NONE_NONE_NONE_NONE_PRED, vhsubq_m_s, v16qi, v8hi, v4si) > +VAR3 (QUADOP_NONE_NONE_NONE_NONE_PRED, vhsubq_m_n_s, v16qi, v8hi, v4si) > +VAR3 (QUADOP_NONE_NONE_NONE_NONE_PRED, vhcaddq_rot90_m_s, v16qi, v8hi, v4si) > +VAR3 (QUADOP_NONE_NONE_NONE_NONE_PRED, vhcaddq_rot270_m_s, v16qi, v8hi, v4si) > +VAR3 (QUADOP_NONE_NONE_NONE_NONE_PRED, vhaddq_m_s, v16qi, v8hi, v4si) > +VAR3 (QUADOP_NONE_NONE_NONE_NONE_PRED, vhaddq_m_n_s, v16qi, v8hi, v4si) > +VAR3 (QUADOP_NONE_NONE_NONE_NONE_PRED, veorq_m_s, v16qi, v8hi, v4si) > +VAR3 (QUADOP_NONE_NONE_NONE_NONE_PRED, vcaddq_rot90_m_s, v16qi, v8hi, v4si) > +VAR3 (QUADOP_NONE_NONE_NONE_NONE_PRED, vcaddq_rot270_m_s, v16qi, v8hi, v4si) > +VAR3 (QUADOP_NONE_NONE_NONE_NONE_PRED, vbrsrq_m_n_s, v16qi, v8hi, v4si) > +VAR3 (QUADOP_NONE_NONE_NONE_NONE_PRED, vbicq_m_s, v16qi, v8hi, v4si) > +VAR3 (QUADOP_NONE_NONE_NONE_NONE_PRED, vandq_m_s, v16qi, v8hi, v4si) > +VAR3 (QUADOP_NONE_NONE_NONE_NONE_PRED, vaddq_m_s, v16qi, v8hi, v4si) > +VAR3 (QUADOP_NONE_NONE_NONE_NONE_PRED, vaddq_m_n_s, v16qi, v8hi, v4si) > +VAR3 (QUADOP_NONE_NONE_NONE_NONE_PRED, vabdq_m_s, v16qi, v8hi, v4si) > +VAR3 (QUADOP_NONE_NONE_NONE_IMM_PRED, vsliq_m_n_s, v16qi, v8hi, v4si) > +VAR3 (QUADOP_NONE_NONE_NONE_IMM_PRED, vshrq_m_n_s, v16qi, v8hi, v4si) > +VAR3 (QUADOP_NONE_NONE_NONE_IMM_PRED, vshlq_m_n_s, v16qi, v8hi, v4si) > +VAR3 (QUADOP_NONE_NONE_NONE_IMM_PRED, vrshrq_m_n_s, v16qi, v8hi, v4si) > +VAR3 (QUADOP_NONE_NONE_NONE_IMM_PRED, vqshlq_m_n_s, v16qi, v8hi, v4si) > +VAR2 (QUADOP_UNONE_UNONE_UNONE_UNONE_PRED, vmulltq_poly_m_p, v16qi, v8hi) > +VAR2 (QUADOP_UNONE_UNONE_UNONE_UNONE_PRED, vmullbq_poly_m_p, v16qi, v8hi) > +VAR2 (QUADOP_UNONE_UNONE_UNONE_UNONE_PRED, vmlaldavaq_p_u, v8hi, v4si) > +VAR2 (QUADOP_UNONE_UNONE_UNONE_IMM_PRED, vshrntq_m_n_u, v8hi, v4si) > +VAR2 (QUADOP_UNONE_UNONE_UNONE_IMM_PRED, vshrnbq_m_n_u, v8hi, v4si) > +VAR2 (QUADOP_UNONE_UNONE_UNONE_IMM_PRED, vshlltq_m_n_u, v16qi, v8hi) > +VAR2 (QUADOP_UNONE_UNONE_UNONE_IMM_PRED, vshllbq_m_n_u, v16qi, v8hi) > +VAR2 (QUADOP_UNONE_UNONE_UNONE_IMM_PRED, vrshrntq_m_n_u, v8hi, v4si) > +VAR2 (QUADOP_UNONE_UNONE_UNONE_IMM_PRED, vrshrnbq_m_n_u, v8hi, v4si) > +VAR2 (QUADOP_UNONE_UNONE_UNONE_IMM_PRED, vqshrntq_m_n_u, v8hi, v4si) > +VAR2 (QUADOP_UNONE_UNONE_UNONE_IMM_PRED, vqshrnbq_m_n_u, v8hi, v4si) > +VAR2 (QUADOP_UNONE_UNONE_UNONE_IMM_PRED, vqrshrntq_m_n_u, v8hi, v4si) > +VAR2 (QUADOP_UNONE_UNONE_UNONE_IMM_PRED, vqrshrnbq_m_n_u, v8hi, v4si) > +VAR2 (QUADOP_UNONE_UNONE_NONE_IMM_PRED, vqshruntq_m_n_s, v8hi, v4si) > +VAR2 (QUADOP_UNONE_UNONE_NONE_IMM_PRED, vqshrunbq_m_n_s, v8hi, v4si) > +VAR2 (QUADOP_UNONE_UNONE_NONE_IMM_PRED, vqrshruntq_m_n_s, v8hi, v4si) > +VAR2 (QUADOP_UNONE_UNONE_NONE_IMM_PRED, vqrshrunbq_m_n_s, v8hi, v4si) > +VAR2 (QUADOP_NONE_NONE_NONE_NONE_PRED, vqdmulltq_m_s, v8hi, v4si) > +VAR2 (QUADOP_NONE_NONE_NONE_NONE_PRED, vqdmulltq_m_n_s, v8hi, v4si) > +VAR2 (QUADOP_NONE_NONE_NONE_NONE_PRED, vqdmullbq_m_s, v8hi, v4si) > +VAR2 (QUADOP_NONE_NONE_NONE_NONE_PRED, vqdmullbq_m_n_s, v8hi, v4si) > +VAR2 (QUADOP_NONE_NONE_NONE_NONE_PRED, vmlsldavaxq_p_s, v8hi, v4si) > +VAR2 (QUADOP_NONE_NONE_NONE_NONE_PRED, vmlsldavaq_p_s, v8hi, v4si) > +VAR2 (QUADOP_NONE_NONE_NONE_NONE_PRED, vmlaldavaxq_p_s, v8hi, v4si) > +VAR2 (QUADOP_NONE_NONE_NONE_NONE_PRED, vmlaldavaq_p_s, v8hi, v4si) > +VAR2 (QUADOP_NONE_NONE_NONE_IMM_PRED, vshrntq_m_n_s, v8hi, v4si) > +VAR2 (QUADOP_NONE_NONE_NONE_IMM_PRED, vshrnbq_m_n_s, v8hi, v4si) > +VAR2 (QUADOP_NONE_NONE_NONE_IMM_PRED, vshlltq_m_n_s, v16qi, v8hi) > +VAR2 (QUADOP_NONE_NONE_NONE_IMM_PRED, vshllbq_m_n_s, v16qi, v8hi) > +VAR2 (QUADOP_NONE_NONE_NONE_IMM_PRED, vrshrntq_m_n_s, v8hi, v4si) > +VAR2 (QUADOP_NONE_NONE_NONE_IMM_PRED, vrshrnbq_m_n_s, v8hi, v4si) > +VAR2 (QUADOP_NONE_NONE_NONE_IMM_PRED, vqshrntq_m_n_s, v8hi, v4si) > +VAR2 (QUADOP_NONE_NONE_NONE_IMM_PRED, vqshrnbq_m_n_s, v8hi, v4si) > +VAR2 (QUADOP_NONE_NONE_NONE_IMM_PRED, vqrshrntq_m_n_s, v8hi, v4si) > +VAR2 (QUADOP_NONE_NONE_NONE_IMM_PRED, vqrshrnbq_m_n_s, v8hi, v4si) > VAR1 (QUADOP_UNONE_UNONE_UNONE_UNONE_UNONE, vrmlaldavhaq_p_u, v4si) > VAR1 (QUADOP_NONE_NONE_NONE_NONE_UNONE, vrmlsldavhaxq_p_s, v4si) > VAR1 (QUADOP_NONE_NONE_NONE_NONE_UNONE, vrmlsldavhaq_p_s, v4si) > VAR1 (QUADOP_NONE_NONE_NONE_NONE_UNONE, vrmlaldavhaxq_p_s, v4si) > VAR1 (QUADOP_NONE_NONE_NONE_NONE_UNONE, vrmlaldavhaq_p_s, v4si) > -VAR2 (QUADOP_UNONE_UNONE_NONE_IMM_UNONE, vcvtq_m_n_from_f_u, v8hi, v4si) > -VAR2 (QUADOP_NONE_NONE_NONE_IMM_UNONE, vcvtq_m_n_from_f_s, v8hi, v4si) > -VAR2 (QUADOP_NONE_NONE_NONE_NONE_UNONE, vbrsrq_m_n_f, v8hf, v4sf) > -VAR2 (QUADOP_NONE_NONE_NONE_NONE_UNONE, vsubq_m_n_f, v8hf, v4sf) > -VAR2 (QUADOP_NONE_NONE_NONE_NONE_UNONE, vsubq_m_f, v8hf, v4sf) > -VAR2 (QUADOP_NONE_NONE_NONE_NONE_UNONE, vorrq_m_f, v8hf, v4sf) > -VAR2 (QUADOP_NONE_NONE_NONE_NONE_UNONE, vornq_m_f, v8hf, v4sf) > -VAR2 (QUADOP_NONE_NONE_NONE_NONE_UNONE, vmulq_m_n_f, v8hf, v4sf) > -VAR2 (QUADOP_NONE_NONE_NONE_NONE_UNONE, vmulq_m_f, v8hf, v4sf) > -VAR2 (QUADOP_NONE_NONE_NONE_NONE_UNONE, vminnmq_m_f, v8hf, v4sf) > -VAR2 (QUADOP_NONE_NONE_NONE_NONE_UNONE, vmaxnmq_m_f, v8hf, v4sf) > -VAR2 (QUADOP_NONE_NONE_NONE_NONE_UNONE, vfmsq_m_f, v8hf, v4sf) > -VAR2 (QUADOP_NONE_NONE_NONE_NONE_UNONE, vfmasq_m_n_f, v8hf, v4sf) > -VAR2 (QUADOP_NONE_NONE_NONE_NONE_UNONE, vfmaq_m_n_f, v8hf, v4sf) > -VAR2 (QUADOP_NONE_NONE_NONE_NONE_UNONE, vfmaq_m_f, v8hf, v4sf) > -VAR2 (QUADOP_NONE_NONE_NONE_NONE_UNONE, veorq_m_f, v8hf, v4sf) > -VAR2 (QUADOP_NONE_NONE_NONE_NONE_UNONE, vcmulq_rot90_m_f, v8hf, v4sf) > -VAR2 (QUADOP_NONE_NONE_NONE_NONE_UNONE, vcmulq_rot270_m_f, v8hf, v4sf) > -VAR2 (QUADOP_NONE_NONE_NONE_NONE_UNONE, vcmulq_rot180_m_f, v8hf, v4sf) > -VAR2 (QUADOP_NONE_NONE_NONE_NONE_UNONE, vcmulq_m_f, v8hf, v4sf) > -VAR2 (QUADOP_NONE_NONE_NONE_NONE_UNONE, vcmlaq_rot90_m_f, v8hf, v4sf) > -VAR2 (QUADOP_NONE_NONE_NONE_NONE_UNONE, vcmlaq_rot270_m_f, v8hf, v4sf) > -VAR2 (QUADOP_NONE_NONE_NONE_NONE_UNONE, vcmlaq_rot180_m_f, v8hf, v4sf) > -VAR2 (QUADOP_NONE_NONE_NONE_NONE_UNONE, vcmlaq_m_f, v8hf, v4sf) > -VAR2 (QUADOP_NONE_NONE_NONE_NONE_UNONE, vcaddq_rot90_m_f, v8hf, v4sf) > -VAR2 (QUADOP_NONE_NONE_NONE_NONE_UNONE, vcaddq_rot270_m_f, v8hf, v4sf) > -VAR2 (QUADOP_NONE_NONE_NONE_NONE_UNONE, vbicq_m_f, v8hf, v4sf) > -VAR2 (QUADOP_NONE_NONE_NONE_NONE_UNONE, vandq_m_f, v8hf, v4sf) > -VAR2 (QUADOP_NONE_NONE_NONE_NONE_UNONE, vaddq_m_n_f, v8hf, v4sf) > -VAR2 (QUADOP_NONE_NONE_NONE_NONE_UNONE, vaddq_m_f, v8hf, v4sf) > -VAR2 (QUADOP_NONE_NONE_NONE_NONE_UNONE, vabdq_m_f, v8hf, v4sf) > +VAR2 (QUADOP_UNONE_UNONE_NONE_IMM_PRED, vcvtq_m_n_from_f_u, v8hi, v4si) > +VAR2 (QUADOP_NONE_NONE_NONE_IMM_PRED, vcvtq_m_n_from_f_s, v8hi, v4si) > +VAR2 (QUADOP_NONE_NONE_NONE_NONE_PRED, vbrsrq_m_n_f, v8hf, v4sf) > +VAR2 (QUADOP_NONE_NONE_NONE_NONE_PRED, vsubq_m_n_f, v8hf, v4sf) > +VAR2 (QUADOP_NONE_NONE_NONE_NONE_PRED, vsubq_m_f, v8hf, v4sf) > +VAR2 (QUADOP_NONE_NONE_NONE_NONE_PRED, vorrq_m_f, v8hf, v4sf) > +VAR2 (QUADOP_NONE_NONE_NONE_NONE_PRED, vornq_m_f, v8hf, v4sf) > +VAR2 (QUADOP_NONE_NONE_NONE_NONE_PRED, vmulq_m_n_f, v8hf, v4sf) > +VAR2 (QUADOP_NONE_NONE_NONE_NONE_PRED, vmulq_m_f, v8hf, v4sf) > +VAR2 (QUADOP_NONE_NONE_NONE_NONE_PRED, vminnmq_m_f, v8hf, v4sf) > +VAR2 (QUADOP_NONE_NONE_NONE_NONE_PRED, vmaxnmq_m_f, v8hf, v4sf) > +VAR2 (QUADOP_NONE_NONE_NONE_NONE_PRED, vfmsq_m_f, v8hf, v4sf) > +VAR2 (QUADOP_NONE_NONE_NONE_NONE_PRED, vfmasq_m_n_f, v8hf, v4sf) > +VAR2 (QUADOP_NONE_NONE_NONE_NONE_PRED, vfmaq_m_n_f, v8hf, v4sf) > +VAR2 (QUADOP_NONE_NONE_NONE_NONE_PRED, vfmaq_m_f, v8hf, v4sf) > +VAR2 (QUADOP_NONE_NONE_NONE_NONE_PRED, veorq_m_f, v8hf, v4sf) > +VAR2 (QUADOP_NONE_NONE_NONE_NONE_PRED, vcmulq_rot90_m_f, v8hf, v4sf) > +VAR2 (QUADOP_NONE_NONE_NONE_NONE_PRED, vcmulq_rot270_m_f, v8hf, v4sf) > +VAR2 (QUADOP_NONE_NONE_NONE_NONE_PRED, vcmulq_rot180_m_f, v8hf, v4sf) > +VAR2 (QUADOP_NONE_NONE_NONE_NONE_PRED, vcmulq_m_f, v8hf, v4sf) > +VAR2 (QUADOP_NONE_NONE_NONE_NONE_PRED, vcmlaq_rot90_m_f, v8hf, v4sf) > +VAR2 (QUADOP_NONE_NONE_NONE_NONE_PRED, vcmlaq_rot270_m_f, v8hf, v4sf) > +VAR2 (QUADOP_NONE_NONE_NONE_NONE_PRED, vcmlaq_rot180_m_f, v8hf, v4sf) > +VAR2 (QUADOP_NONE_NONE_NONE_NONE_PRED, vcmlaq_m_f, v8hf, v4sf) > +VAR2 (QUADOP_NONE_NONE_NONE_NONE_PRED, vcaddq_rot90_m_f, v8hf, v4sf) > +VAR2 (QUADOP_NONE_NONE_NONE_NONE_PRED, vcaddq_rot270_m_f, v8hf, v4sf) > +VAR2 (QUADOP_NONE_NONE_NONE_NONE_PRED, vbicq_m_f, v8hf, v4sf) > +VAR2 (QUADOP_NONE_NONE_NONE_NONE_PRED, vandq_m_f, v8hf, v4sf) > +VAR2 (QUADOP_NONE_NONE_NONE_NONE_PRED, vaddq_m_n_f, v8hf, v4sf) > +VAR2 (QUADOP_NONE_NONE_NONE_NONE_PRED, vaddq_m_f, v8hf, v4sf) > +VAR2 (QUADOP_NONE_NONE_NONE_NONE_PRED, vabdq_m_f, v8hf, v4sf) > VAR3 (STRS, vstrbq_s, v16qi, v8hi, v4si) > VAR3 (STRU, vstrbq_u, v16qi, v8hi, v4si) > VAR3 (STRSS, vstrbq_scatter_offset_s, v16qi, v8hi, v4si) > @@ -797,14 +797,14 @@ VAR1 (STRSU_P, vstrwq_scatter_offset_p_u, v4si) > VAR1 (STRSU_P, vstrwq_scatter_shifted_offset_p_u, v4si) > VAR3 (TERNOP_UNONE_UNONE_UNONE_IMM, viwdupq_wb_u, v16qi, v4si, v8hi) > VAR3 (TERNOP_UNONE_UNONE_UNONE_IMM, vdwdupq_wb_u, v16qi, v4si, v8hi) > -VAR3 (QUINOP_UNONE_UNONE_UNONE_UNONE_IMM_UNONE, viwdupq_m_wb_u, v16qi, v8hi, v4si) > -VAR3 (QUINOP_UNONE_UNONE_UNONE_UNONE_IMM_UNONE, vdwdupq_m_wb_u, v16qi, v8hi, v4si) > -VAR3 (QUINOP_UNONE_UNONE_UNONE_UNONE_IMM_UNONE, viwdupq_m_n_u, v16qi, v8hi, v4si) > -VAR3 (QUINOP_UNONE_UNONE_UNONE_UNONE_IMM_UNONE, vdwdupq_m_n_u, v16qi, v8hi, v4si) > +VAR3 (QUINOP_UNONE_UNONE_UNONE_UNONE_IMM_PRED, viwdupq_m_wb_u, v16qi, v8hi, v4si) > +VAR3 (QUINOP_UNONE_UNONE_UNONE_UNONE_IMM_PRED, vdwdupq_m_wb_u, v16qi, v8hi, v4si) > +VAR3 (QUINOP_UNONE_UNONE_UNONE_UNONE_IMM_PRED, viwdupq_m_n_u, v16qi, v8hi, v4si) > +VAR3 (QUINOP_UNONE_UNONE_UNONE_UNONE_IMM_PRED, vdwdupq_m_n_u, v16qi, v8hi, v4si) > VAR3 (BINOP_UNONE_UNONE_IMM, vddupq_n_u, v16qi, v8hi, v4si) > VAR3 (BINOP_UNONE_UNONE_IMM, vidupq_n_u, v16qi, v8hi, v4si) > -VAR3 (QUADOP_UNONE_UNONE_UNONE_IMM_UNONE, vddupq_m_n_u, v16qi, v8hi, v4si) > -VAR3 (QUADOP_UNONE_UNONE_UNONE_IMM_UNONE, vidupq_m_n_u, v16qi, v8hi, v4si) > +VAR3 (QUADOP_UNONE_UNONE_UNONE_IMM_PRED, vddupq_m_n_u, v16qi, v8hi, v4si) > +VAR3 (QUADOP_UNONE_UNONE_UNONE_IMM_PRED, vidupq_m_n_u, v16qi, v8hi, v4si) > VAR3 (TERNOP_UNONE_UNONE_UNONE_IMM, vdwdupq_n_u, v16qi, v4si, v8hi) > VAR3 (TERNOP_UNONE_UNONE_UNONE_IMM, viwdupq_n_u, v16qi, v4si, v8hi) > VAR1 (STRSBWBU, vstrwq_scatter_base_wb_u, v4si) > @@ -870,10 +870,10 @@ VAR1 (UQSHL, urshr_, si) > VAR1 (UQSHL, urshrl_, di) > VAR1 (UQSHL, uqshl_, si) > VAR1 (UQSHL, uqshll_, di) > -VAR3 (QUADOP_NONE_NONE_UNONE_IMM_UNONE, vshlcq_m_vec_s, v16qi, v8hi, v4si) > -VAR3 (QUADOP_NONE_NONE_UNONE_IMM_UNONE, vshlcq_m_carry_s, v16qi, v8hi, v4si) > -VAR3 (QUADOP_UNONE_UNONE_UNONE_IMM_UNONE, vshlcq_m_vec_u, v16qi, v8hi, v4si) > -VAR3 (QUADOP_UNONE_UNONE_UNONE_IMM_UNONE, vshlcq_m_carry_u, v16qi, v8hi, v4si) > +VAR3 (QUADOP_NONE_NONE_UNONE_IMM_PRED, vshlcq_m_vec_s, v16qi, v8hi, v4si) > +VAR3 (QUADOP_NONE_NONE_UNONE_IMM_PRED, vshlcq_m_carry_s, v16qi, v8hi, v4si) > +VAR3 (QUADOP_UNONE_UNONE_UNONE_IMM_PRED, vshlcq_m_vec_u, v16qi, v8hi, v4si) > +VAR3 (QUADOP_UNONE_UNONE_UNONE_IMM_PRED, vshlcq_m_carry_u, v16qi, v8hi, v4si) > > /* optabs without any suffixes. */ > VAR5 (BINOP_NONE_NONE_NONE, vcaddq_rot90, v16qi, v8hi, v4si, v8hf, v4sf) > diff --git a/gcc/config/arm/mve.md b/gcc/config/arm/mve.md > index 4867aa79687..2f36d47c800 100644 > --- a/gcc/config/arm/mve.md > +++ b/gcc/config/arm/mve.md > @@ -130,7 +130,7 @@ (define_insn "mve_vrndq_m_f<mode>" > (set (match_operand:MVE_0 0 "s_register_operand" "=w") > (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0") > (match_operand:MVE_0 2 "s_register_operand" "w") > - (match_operand:HI 3 "vpr_register_operand" "Up")] > + (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")] > VRNDQ_M_F)) > ] > "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" > @@ -918,7 +918,7 @@ (define_insn "mve_vaddvq_p_<supf><mode>" > [ > (set (match_operand:SI 0 "s_register_operand" "=Te") > (unspec:SI [(match_operand:MVE_2 1 "s_register_operand" "w") > - (match_operand:HI 2 "vpr_register_operand" "Up")] > + (match_operand:<MVE_VPRED> 2 "vpr_register_operand" "Up")] > VADDVQ_P)) > ] > "TARGET_HAVE_MVE" > @@ -2581,7 +2581,7 @@ (define_insn "mve_vbicq_m_n_<supf><mode>" > (set (match_operand:MVE_5 0 "s_register_operand" "=w") > (unspec:MVE_5 [(match_operand:MVE_5 1 "s_register_operand" "0") > (match_operand:SI 2 "immediate_operand" "i") > - (match_operand:HI 3 "vpr_register_operand" "Up")] > + (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")] > VBICQ_M_N)) > ] > "TARGET_HAVE_MVE" > @@ -2611,7 +2611,7 @@ (define_insn "mve_vcvtaq_m_<supf><mode>" > (set (match_operand:MVE_5 0 "s_register_operand" "=w") > (unspec:MVE_5 [(match_operand:MVE_5 1 "s_register_operand" "0") > (match_operand:<MVE_CNVT> 2 "s_register_operand" "w") > - (match_operand:HI 3 "vpr_register_operand" "Up")] > + (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")] > VCVTAQ_M)) > ] > "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" > @@ -2626,7 +2626,7 @@ (define_insn "mve_vcvtq_m_to_f_<supf><mode>" > (set (match_operand:MVE_0 0 "s_register_operand" "=w") > (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0") > (match_operand:<MVE_CNVT> 2 "s_register_operand" "w") > - (match_operand:HI 3 "vpr_register_operand" "Up")] > + (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")] > VCVTQ_M_TO_F)) > ] > "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" > @@ -2748,7 +2748,7 @@ (define_insn "mve_vabsq_m_s<mode>" > (set (match_operand:MVE_2 0 "s_register_operand" "=w") > (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") > (match_operand:MVE_2 2 "s_register_operand" "w") > - (match_operand:HI 3 "vpr_register_operand" "Up")] > + (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")] > VABSQ_M_S)) > ] > "TARGET_HAVE_MVE" > @@ -2764,7 +2764,7 @@ (define_insn "mve_vaddvaq_p_<supf><mode>" > (set (match_operand:SI 0 "s_register_operand" "=Te") > (unspec:SI [(match_operand:SI 1 "s_register_operand" "0") > (match_operand:MVE_2 2 "s_register_operand" "w") > - (match_operand:HI 3 "vpr_register_operand" "Up")] > + (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")] > VADDVAQ_P)) > ] > "TARGET_HAVE_MVE" > @@ -2780,7 +2780,7 @@ (define_insn "mve_vclsq_m_s<mode>" > (set (match_operand:MVE_2 0 "s_register_operand" "=w") > (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") > (match_operand:MVE_2 2 "s_register_operand" "w") > - (match_operand:HI 3 "vpr_register_operand" "Up")] > + (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")] > VCLSQ_M_S)) > ] > "TARGET_HAVE_MVE" > @@ -2796,7 +2796,7 @@ (define_insn "mve_vclzq_m_<supf><mode>" > (set (match_operand:MVE_2 0 "s_register_operand" "=w") > (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") > (match_operand:MVE_2 2 "s_register_operand" "w") > - (match_operand:HI 3 "vpr_register_operand" "Up")] > + (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")] > VCLZQ_M)) > ] > "TARGET_HAVE_MVE" > @@ -3068,7 +3068,7 @@ (define_insn "mve_vdupq_m_n_<supf><mode>" > (set (match_operand:MVE_2 0 "s_register_operand" "=w") > (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") > (match_operand:<V_elem> 2 "s_register_operand" "r") > - (match_operand:HI 3 "vpr_register_operand" "Up")] > + (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")] > VDUPQ_M_N)) > ] > "TARGET_HAVE_MVE" > @@ -3084,7 +3084,7 @@ (define_insn "mve_vmaxaq_m_s<mode>" > (set (match_operand:MVE_2 0 "s_register_operand" "=w") > (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") > (match_operand:MVE_2 2 "s_register_operand" "w") > - (match_operand:HI 3 "vpr_register_operand" "Up")] > + (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")] > VMAXAQ_M_S)) > ] > "TARGET_HAVE_MVE" > @@ -3100,7 +3100,7 @@ (define_insn "mve_vmaxavq_p_s<mode>" > (set (match_operand:<V_elem> 0 "s_register_operand" "=r") > (unspec:<V_elem> [(match_operand:<V_elem> 1 "s_register_operand" "0") > (match_operand:MVE_2 2 "s_register_operand" "w") > - (match_operand:HI 3 "vpr_register_operand" "Up")] > + (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")] > VMAXAVQ_P_S)) > ] > "TARGET_HAVE_MVE" > @@ -3116,7 +3116,7 @@ (define_insn "mve_vmaxvq_p_<supf><mode>" > (set (match_operand:<V_elem> 0 "s_register_operand" "=r") > (unspec:<V_elem> [(match_operand:<V_elem> 1 "s_register_operand" "0") > (match_operand:MVE_2 2 "s_register_operand" "w") > - (match_operand:HI 3 "vpr_register_operand" "Up")] > + (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")] > VMAXVQ_P)) > ] > "TARGET_HAVE_MVE" > @@ -3132,7 +3132,7 @@ (define_insn "mve_vminaq_m_s<mode>" > (set (match_operand:MVE_2 0 "s_register_operand" "=w") > (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") > (match_operand:MVE_2 2 "s_register_operand" "w") > - (match_operand:HI 3 "vpr_register_operand" "Up")] > + (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")] > VMINAQ_M_S)) > ] > "TARGET_HAVE_MVE" > @@ -3148,7 +3148,7 @@ (define_insn "mve_vminavq_p_s<mode>" > (set (match_operand:<V_elem> 0 "s_register_operand" "=r") > (unspec:<V_elem> [(match_operand:<V_elem> 1 "s_register_operand" "0") > (match_operand:MVE_2 2 "s_register_operand" "w") > - (match_operand:HI 3 "vpr_register_operand" "Up")] > + (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")] > VMINAVQ_P_S)) > ] > "TARGET_HAVE_MVE" > @@ -3164,7 +3164,7 @@ (define_insn "mve_vminvq_p_<supf><mode>" > (set (match_operand:<V_elem> 0 "s_register_operand" "=r") > (unspec:<V_elem> [(match_operand:<V_elem> 1 "s_register_operand" "0") > (match_operand:MVE_2 2 "s_register_operand" "w") > - (match_operand:HI 3 "vpr_register_operand" "Up")] > + (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")] > VMINVQ_P)) > ] > "TARGET_HAVE_MVE" > @@ -3196,7 +3196,7 @@ (define_insn "mve_vmladavq_p_<supf><mode>" > (set (match_operand:SI 0 "s_register_operand" "=Te") > (unspec:SI [(match_operand:MVE_2 1 "s_register_operand" "w") > (match_operand:MVE_2 2 "s_register_operand" "w") > - (match_operand:HI 3 "vpr_register_operand" "Up")] > + (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")] > VMLADAVQ_P)) > ] > "TARGET_HAVE_MVE" > @@ -3212,7 +3212,7 @@ (define_insn "mve_vmladavxq_p_s<mode>" > (set (match_operand:SI 0 "s_register_operand" "=Te") > (unspec:SI [(match_operand:MVE_2 1 "s_register_operand" "w") > (match_operand:MVE_2 2 "s_register_operand" "w") > - (match_operand:HI 3 "vpr_register_operand" "Up")] > + (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")] > VMLADAVXQ_P_S)) > ] > "TARGET_HAVE_MVE" > @@ -3260,7 +3260,7 @@ (define_insn "mve_vmlsdavq_p_s<mode>" > (set (match_operand:SI 0 "s_register_operand" "=Te") > (unspec:SI [(match_operand:MVE_2 1 "s_register_operand" "w") > (match_operand:MVE_2 2 "s_register_operand" "w") > - (match_operand:HI 3 "vpr_register_operand" "Up")] > + (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")] > VMLSDAVQ_P_S)) > ] > "TARGET_HAVE_MVE" > @@ -3276,7 +3276,7 @@ (define_insn "mve_vmlsdavxq_p_s<mode>" > (set (match_operand:SI 0 "s_register_operand" "=Te") > (unspec:SI [(match_operand:MVE_2 1 "s_register_operand" "w") > (match_operand:MVE_2 2 "s_register_operand" "w") > - (match_operand:HI 3 "vpr_register_operand" "Up")] > + (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")] > VMLSDAVXQ_P_S)) > ] > "TARGET_HAVE_MVE" > @@ -3292,7 +3292,7 @@ (define_insn "mve_vmvnq_m_<supf><mode>" > (set (match_operand:MVE_2 0 "s_register_operand" "=w") > (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") > (match_operand:MVE_2 2 "s_register_operand" "w") > - (match_operand:HI 3 "vpr_register_operand" "Up")] > + (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")] > VMVNQ_M)) > ] > "TARGET_HAVE_MVE" > @@ -3308,7 +3308,7 @@ (define_insn "mve_vnegq_m_s<mode>" > (set (match_operand:MVE_2 0 "s_register_operand" "=w") > (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") > (match_operand:MVE_2 2 "s_register_operand" "w") > - (match_operand:HI 3 "vpr_register_operand" "Up")] > + (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")] > VNEGQ_M_S)) > ] > "TARGET_HAVE_MVE" > @@ -3352,7 +3352,7 @@ (define_insn "mve_vqabsq_m_s<mode>" > (set (match_operand:MVE_2 0 "s_register_operand" "=w") > (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") > (match_operand:MVE_2 2 "s_register_operand" "w") > - (match_operand:HI 3 "vpr_register_operand" "Up")] > + (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")] > VQABSQ_M_S)) > ] > "TARGET_HAVE_MVE" > @@ -3400,7 +3400,7 @@ (define_insn "mve_vqnegq_m_s<mode>" > (set (match_operand:MVE_2 0 "s_register_operand" "=w") > (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") > (match_operand:MVE_2 2 "s_register_operand" "w") > - (match_operand:HI 3 "vpr_register_operand" "Up")] > + (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")] > VQNEGQ_M_S)) > ] > "TARGET_HAVE_MVE" > @@ -3512,7 +3512,7 @@ (define_insn "mve_vqrshlq_m_n_<supf><mode>" > (set (match_operand:MVE_2 0 "s_register_operand" "=w") > (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") > (match_operand:SI 2 "s_register_operand" "r") > - (match_operand:HI 3 "vpr_register_operand" "Up")] > + (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")] > VQRSHLQ_M_N)) > ] > "TARGET_HAVE_MVE" > @@ -3528,7 +3528,7 @@ (define_insn "mve_vqshlq_m_r_<supf><mode>" > (set (match_operand:MVE_2 0 "s_register_operand" "=w") > (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") > (match_operand:SI 2 "s_register_operand" "r") > - (match_operand:HI 3 "vpr_register_operand" "Up")] > + (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")] > VQSHLQ_M_R)) > ] > "TARGET_HAVE_MVE" > @@ -3544,7 +3544,7 @@ (define_insn "mve_vrev64q_m_<supf><mode>" > (set (match_operand:MVE_2 0 "s_register_operand" "=w") > (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") > (match_operand:MVE_2 2 "s_register_operand" "w") > - (match_operand:HI 3 "vpr_register_operand" "Up")] > + (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")] > VREV64Q_M)) > ] > "TARGET_HAVE_MVE" > @@ -3560,7 +3560,7 @@ (define_insn "mve_vrshlq_m_n_<supf><mode>" > (set (match_operand:MVE_2 0 "s_register_operand" "=w") > (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") > (match_operand:SI 2 "s_register_operand" "r") > - (match_operand:HI 3 "vpr_register_operand" "Up")] > + (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")] > VRSHLQ_M_N)) > ] > "TARGET_HAVE_MVE" > @@ -3576,7 +3576,7 @@ (define_insn "mve_vshlq_m_r_<supf><mode>" > (set (match_operand:MVE_2 0 "s_register_operand" "=w") > (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") > (match_operand:SI 2 "s_register_operand" "r") > - (match_operand:HI 3 "vpr_register_operand" "Up")] > + (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")] > VSHLQ_M_R)) > ] > "TARGET_HAVE_MVE" > @@ -3735,7 +3735,7 @@ (define_insn "mve_vabsq_m_f<mode>" > (set (match_operand:MVE_0 0 "s_register_operand" "=w") > (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0") > (match_operand:MVE_0 2 "s_register_operand" "w") > - (match_operand:HI 3 "vpr_register_operand" "Up")] > + (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")] > VABSQ_M_F)) > ] > "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" > @@ -4025,7 +4025,7 @@ (define_insn "mve_vdupq_m_n_f<mode>" > (set (match_operand:MVE_0 0 "s_register_operand" "=w") > (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0") > (match_operand:<V_elem> 2 "s_register_operand" "r") > - (match_operand:HI 3 "vpr_register_operand" "Up")] > + (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")] > VDUPQ_M_N_F)) > ] > "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" > @@ -4104,7 +4104,7 @@ (define_insn "mve_vmaxnmaq_m_f<mode>" > (set (match_operand:MVE_0 0 "s_register_operand" "=w") > (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0") > (match_operand:MVE_0 2 "s_register_operand" "w") > - (match_operand:HI 3 "vpr_register_operand" "Up")] > + (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")] > VMAXNMAQ_M_F)) > ] > "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" > @@ -4119,7 +4119,7 @@ (define_insn "mve_vmaxnmavq_p_f<mode>" > (set (match_operand:<V_elem> 0 "s_register_operand" "=r") > (unspec:<V_elem> [(match_operand:<V_elem> 1 "s_register_operand" "0") > (match_operand:MVE_0 2 "s_register_operand" "w") > - (match_operand:HI 3 "vpr_register_operand" "Up")] > + (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")] > VMAXNMAVQ_P_F)) > ] > "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" > @@ -4135,7 +4135,7 @@ (define_insn "mve_vmaxnmvq_p_f<mode>" > (set (match_operand:<V_elem> 0 "s_register_operand" "=r") > (unspec:<V_elem> [(match_operand:<V_elem> 1 "s_register_operand" "0") > (match_operand:MVE_0 2 "s_register_operand" "w") > - (match_operand:HI 3 "vpr_register_operand" "Up")] > + (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")] > VMAXNMVQ_P_F)) > ] > "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" > @@ -4150,7 +4150,7 @@ (define_insn "mve_vminnmaq_m_f<mode>" > (set (match_operand:MVE_0 0 "s_register_operand" "=w") > (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0") > (match_operand:MVE_0 2 "s_register_operand" "w") > - (match_operand:HI 3 "vpr_register_operand" "Up")] > + (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")] > VMINNMAQ_M_F)) > ] > "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" > @@ -4166,7 +4166,7 @@ (define_insn "mve_vminnmavq_p_f<mode>" > (set (match_operand:<V_elem> 0 "s_register_operand" "=r") > (unspec:<V_elem> [(match_operand:<V_elem> 1 "s_register_operand" "0") > (match_operand:MVE_0 2 "s_register_operand" "w") > - (match_operand:HI 3 "vpr_register_operand" "Up")] > + (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")] > VMINNMAVQ_P_F)) > ] > "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" > @@ -4181,7 +4181,7 @@ (define_insn "mve_vminnmvq_p_f<mode>" > (set (match_operand:<V_elem> 0 "s_register_operand" "=r") > (unspec:<V_elem> [(match_operand:<V_elem> 1 "s_register_operand" "0") > (match_operand:MVE_0 2 "s_register_operand" "w") > - (match_operand:HI 3 "vpr_register_operand" "Up")] > + (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")] > VMINNMVQ_P_F)) > ] > "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" > @@ -4229,7 +4229,7 @@ (define_insn "mve_vmlaldavq_p_<supf><mode>" > (set (match_operand:DI 0 "s_register_operand" "=r") > (unspec:DI [(match_operand:MVE_5 1 "s_register_operand" "w") > (match_operand:MVE_5 2 "s_register_operand" "w") > - (match_operand:HI 3 "vpr_register_operand" "Up")] > + (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")] > VMLALDAVQ_P)) > ] > "TARGET_HAVE_MVE" > @@ -4245,7 +4245,7 @@ (define_insn "mve_vmlaldavxq_p_s<mode>" > (set (match_operand:DI 0 "s_register_operand" "=r") > (unspec:DI [(match_operand:MVE_5 1 "s_register_operand" "w") > (match_operand:MVE_5 2 "s_register_operand" "w") > - (match_operand:HI 3 "vpr_register_operand" "Up")] > + (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")] > VMLALDAVXQ_P_S)) > ] > "TARGET_HAVE_MVE" > @@ -4292,7 +4292,7 @@ (define_insn "mve_vmlsldavq_p_s<mode>" > (set (match_operand:DI 0 "s_register_operand" "=r") > (unspec:DI [(match_operand:MVE_5 1 "s_register_operand" "w") > (match_operand:MVE_5 2 "s_register_operand" "w") > - (match_operand:HI 3 "vpr_register_operand" "Up")] > + (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")] > VMLSLDAVQ_P_S)) > ] > "TARGET_HAVE_MVE" > @@ -4308,7 +4308,7 @@ (define_insn "mve_vmlsldavxq_p_s<mode>" > (set (match_operand:DI 0 "s_register_operand" "=r") > (unspec:DI [(match_operand:MVE_5 1 "s_register_operand" "w") > (match_operand:MVE_5 2 "s_register_operand" "w") > - (match_operand:HI 3 "vpr_register_operand" "Up")] > + (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")] > VMLSLDAVXQ_P_S)) > ] > "TARGET_HAVE_MVE" > @@ -4323,7 +4323,7 @@ (define_insn "mve_vmovlbq_m_<supf><mode>" > (set (match_operand:<V_double_width> 0 "s_register_operand" "=w") > (unspec:<V_double_width> [(match_operand:<V_double_width> 1 "s_register_operand" "0") > (match_operand:MVE_3 2 "s_register_operand" "w") > - (match_operand:HI 3 "vpr_register_operand" "Up")] > + (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")] > VMOVLBQ_M)) > ] > "TARGET_HAVE_MVE" > @@ -4338,7 +4338,7 @@ (define_insn "mve_vmovltq_m_<supf><mode>" > (set (match_operand:<V_double_width> 0 "s_register_operand" "=w") > (unspec:<V_double_width> [(match_operand:<V_double_width> 1 "s_register_operand" "0") > (match_operand:MVE_3 2 "s_register_operand" "w") > - (match_operand:HI 3 "vpr_register_operand" "Up")] > + (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")] > VMOVLTQ_M)) > ] > "TARGET_HAVE_MVE" > @@ -4353,7 +4353,7 @@ (define_insn "mve_vmovnbq_m_<supf><mode>" > (set (match_operand:<V_narrow_pack> 0 "s_register_operand" "=w") > (unspec:<V_narrow_pack> [(match_operand:<V_narrow_pack> 1 "s_register_operand" "0") > (match_operand:MVE_5 2 "s_register_operand" "w") > - (match_operand:HI 3 "vpr_register_operand" "Up")] > + (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")] > VMOVNBQ_M)) > ] > "TARGET_HAVE_MVE" > @@ -4369,7 +4369,7 @@ (define_insn "mve_vmovntq_m_<supf><mode>" > (set (match_operand:<V_narrow_pack> 0 "s_register_operand" "=w") > (unspec:<V_narrow_pack> [(match_operand:<V_narrow_pack> 1 "s_register_operand" "0") > (match_operand:MVE_5 2 "s_register_operand" "w") > - (match_operand:HI 3 "vpr_register_operand" "Up")] > + (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")] > VMOVNTQ_M)) > ] > "TARGET_HAVE_MVE" > @@ -4385,7 +4385,7 @@ (define_insn "mve_vmvnq_m_n_<supf><mode>" > (set (match_operand:MVE_5 0 "s_register_operand" "=w") > (unspec:MVE_5 [(match_operand:MVE_5 1 "s_register_operand" "0") > (match_operand:SI 2 "immediate_operand" "i") > - (match_operand:HI 3 "vpr_register_operand" "Up")] > + (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")] > VMVNQ_M_N)) > ] > "TARGET_HAVE_MVE" > @@ -4400,7 +4400,7 @@ (define_insn "mve_vnegq_m_f<mode>" > (set (match_operand:MVE_0 0 "s_register_operand" "=w") > (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0") > (match_operand:MVE_0 2 "s_register_operand" "w") > - (match_operand:HI 3 "vpr_register_operand" "Up")] > + (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")] > VNEGQ_M_F)) > ] > "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" > @@ -4416,7 +4416,7 @@ (define_insn "mve_vorrq_m_n_<supf><mode>" > (set (match_operand:MVE_5 0 "s_register_operand" "=w") > (unspec:MVE_5 [(match_operand:MVE_5 1 "s_register_operand" "0") > (match_operand:SI 2 "immediate_operand" "i") > - (match_operand:HI 3 "vpr_register_operand" "Up")] > + (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")] > VORRQ_M_N)) > ] > "TARGET_HAVE_MVE" > @@ -4447,7 +4447,7 @@ (define_insn "mve_vqmovnbq_m_<supf><mode>" > (set (match_operand:<V_narrow_pack> 0 "s_register_operand" "=w") > (unspec:<V_narrow_pack> [(match_operand:<V_narrow_pack> 1 "s_register_operand" "0") > (match_operand:MVE_5 2 "s_register_operand" "w") > - (match_operand:HI 3 "vpr_register_operand" "Up")] > + (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")] > VQMOVNBQ_M)) > ] > "TARGET_HAVE_MVE" > @@ -4463,7 +4463,7 @@ (define_insn "mve_vqmovntq_m_<supf><mode>" > (set (match_operand:<V_narrow_pack> 0 "s_register_operand" "=w") > (unspec:<V_narrow_pack> [(match_operand:<V_narrow_pack> 1 "s_register_operand" "0") > (match_operand:MVE_5 2 "s_register_operand" "w") > - (match_operand:HI 3 "vpr_register_operand" "Up")] > + (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")] > VQMOVNTQ_M)) > ] > "TARGET_HAVE_MVE" > @@ -4479,7 +4479,7 @@ (define_insn "mve_vqmovunbq_m_s<mode>" > (set (match_operand:<V_narrow_pack> 0 "s_register_operand" "=w") > (unspec:<V_narrow_pack> [(match_operand:<V_narrow_pack> 1 "s_register_operand" "0") > (match_operand:MVE_5 2 "s_register_operand" "w") > - (match_operand:HI 3 "vpr_register_operand" "Up")] > + (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")] > VQMOVUNBQ_M_S)) > ] > "TARGET_HAVE_MVE" > @@ -4495,7 +4495,7 @@ (define_insn "mve_vqmovuntq_m_s<mode>" > (set (match_operand:<V_narrow_pack> 0 "s_register_operand" "=w") > (unspec:<V_narrow_pack> [(match_operand:<V_narrow_pack> 1 "s_register_operand" "0") > (match_operand:MVE_5 2 "s_register_operand" "w") > - (match_operand:HI 3 "vpr_register_operand" "Up")] > + (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")] > VQMOVUNTQ_M_S)) > ] > "TARGET_HAVE_MVE" > @@ -4623,7 +4623,7 @@ (define_insn "mve_vrev32q_m_<supf><mode>" > (set (match_operand:MVE_3 0 "s_register_operand" "=w") > (unspec:MVE_3 [(match_operand:MVE_3 1 "s_register_operand" "0") > (match_operand:MVE_3 2 "s_register_operand" "w") > - (match_operand:HI 3 "vpr_register_operand" "Up")] > + (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")] > VREV32Q_M)) > ] > "TARGET_HAVE_MVE" > @@ -4639,7 +4639,7 @@ (define_insn "mve_vrev64q_m_f<mode>" > (set (match_operand:MVE_0 0 "s_register_operand" "=w") > (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0") > (match_operand:MVE_0 2 "s_register_operand" "w") > - (match_operand:HI 3 "vpr_register_operand" "Up")] > + (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")] > VREV64Q_M_F)) > ] > "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" > @@ -4735,7 +4735,7 @@ (define_insn "mve_vrndaq_m_f<mode>" > (set (match_operand:MVE_0 0 "s_register_operand" "=w") > (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0") > (match_operand:MVE_0 2 "s_register_operand" "w") > - (match_operand:HI 3 "vpr_register_operand" "Up")] > + (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")] > VRNDAQ_M_F)) > ] > "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" > @@ -4751,7 +4751,7 @@ (define_insn "mve_vrndmq_m_f<mode>" > (set (match_operand:MVE_0 0 "s_register_operand" "=w") > (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0") > (match_operand:MVE_0 2 "s_register_operand" "w") > - (match_operand:HI 3 "vpr_register_operand" "Up")] > + (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")] > VRNDMQ_M_F)) > ] > "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" > @@ -4767,7 +4767,7 @@ (define_insn "mve_vrndnq_m_f<mode>" > (set (match_operand:MVE_0 0 "s_register_operand" "=w") > (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0") > (match_operand:MVE_0 2 "s_register_operand" "w") > - (match_operand:HI 3 "vpr_register_operand" "Up")] > + (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")] > VRNDNQ_M_F)) > ] > "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" > @@ -4783,7 +4783,7 @@ (define_insn "mve_vrndpq_m_f<mode>" > (set (match_operand:MVE_0 0 "s_register_operand" "=w") > (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0") > (match_operand:MVE_0 2 "s_register_operand" "w") > - (match_operand:HI 3 "vpr_register_operand" "Up")] > + (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")] > VRNDPQ_M_F)) > ] > "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" > @@ -4799,7 +4799,7 @@ (define_insn "mve_vrndxq_m_f<mode>" > (set (match_operand:MVE_0 0 "s_register_operand" "=w") > (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0") > (match_operand:MVE_0 2 "s_register_operand" "w") > - (match_operand:HI 3 "vpr_register_operand" "Up")] > + (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")] > VRNDXQ_M_F)) > ] > "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" > @@ -4879,7 +4879,7 @@ (define_insn "mve_vcvtmq_m_<supf><mode>" > (set (match_operand:MVE_5 0 "s_register_operand" "=w") > (unspec:MVE_5 [(match_operand:MVE_5 1 "s_register_operand" "0") > (match_operand:<MVE_CNVT> 2 "s_register_operand" "w") > - (match_operand:HI 3 "vpr_register_operand" "Up")] > + (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")] > VCVTMQ_M)) > ] > "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" > @@ -4895,7 +4895,7 @@ (define_insn "mve_vcvtpq_m_<supf><mode>" > (set (match_operand:MVE_5 0 "s_register_operand" "=w") > (unspec:MVE_5 [(match_operand:MVE_5 1 "s_register_operand" "0") > (match_operand:<MVE_CNVT> 2 "s_register_operand" "w") > - (match_operand:HI 3 "vpr_register_operand" "Up")] > + (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")] > VCVTPQ_M)) > ] > "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" > @@ -4911,7 +4911,7 @@ (define_insn "mve_vcvtnq_m_<supf><mode>" > (set (match_operand:MVE_5 0 "s_register_operand" "=w") > (unspec:MVE_5 [(match_operand:MVE_5 1 "s_register_operand" "0") > (match_operand:<MVE_CNVT> 2 "s_register_operand" "w") > - (match_operand:HI 3 "vpr_register_operand" "Up")] > + (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")] > VCVTNQ_M)) > ] > "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" > @@ -4928,7 +4928,7 @@ (define_insn "mve_vcvtq_m_n_from_f_<supf><mode>" > (unspec:MVE_5 [(match_operand:MVE_5 1 "s_register_operand" "0") > (match_operand:<MVE_CNVT> 2 "s_register_operand" "w") > (match_operand:SI 3 "<MVE_pred2>" "<MVE_constraint2>") > - (match_operand:HI 4 "vpr_register_operand" "Up")] > + (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")] > VCVTQ_M_N_FROM_F)) > ] > "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" > @@ -4960,7 +4960,7 @@ (define_insn "mve_vcvtq_m_from_f_<supf><mode>" > (set (match_operand:MVE_5 0 "s_register_operand" "=w") > (unspec:MVE_5 [(match_operand:MVE_5 1 "s_register_operand" "0") > (match_operand:<MVE_CNVT> 2 "s_register_operand" "w") > - (match_operand:HI 3 "vpr_register_operand" "Up")] > + (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")] > VCVTQ_M_FROM_F)) > ] > "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" > @@ -5009,7 +5009,7 @@ (define_insn "mve_vabavq_p_<supf><mode>" > (unspec:SI [(match_operand:SI 1 "s_register_operand" "0") > (match_operand:MVE_2 2 "s_register_operand" "w") > (match_operand:MVE_2 3 "s_register_operand" "w") > - (match_operand:HI 4 "vpr_register_operand" "Up")] > + (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")] > VABAVQ_P)) > ] > "TARGET_HAVE_MVE" > @@ -5026,7 +5026,7 @@ (define_insn "mve_vqshluq_m_n_s<mode>" > (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") > (match_operand:MVE_2 2 "s_register_operand" "w") > (match_operand:SI 3 "mve_imm_7" "Ra") > - (match_operand:HI 4 "vpr_register_operand" "Up")] > + (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")] > VQSHLUQ_M_N_S)) > ] > "TARGET_HAVE_MVE" > @@ -5042,7 +5042,7 @@ (define_insn "mve_vshlq_m_<supf><mode>" > (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") > (match_operand:MVE_2 2 "s_register_operand" "w") > (match_operand:MVE_2 3 "s_register_operand" "w") > - (match_operand:HI 4 "vpr_register_operand" "Up")] > + (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")] > VSHLQ_M)) > ] > "TARGET_HAVE_MVE" > @@ -5058,7 +5058,7 @@ (define_insn "mve_vsriq_m_n_<supf><mode>" > (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") > (match_operand:MVE_2 2 "s_register_operand" "w") > (match_operand:SI 3 "mve_imm_selective_upto_8" "Rg") > - (match_operand:HI 4 "vpr_register_operand" "Up")] > + (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")] > VSRIQ_M_N)) > ] > "TARGET_HAVE_MVE" > @@ -5074,7 +5074,7 @@ (define_insn "mve_vsubq_m_<supf><mode>" > (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") > (match_operand:MVE_2 2 "s_register_operand" "w") > (match_operand:MVE_2 3 "s_register_operand" "w") > - (match_operand:HI 4 "vpr_register_operand" "Up")] > + (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")] > VSUBQ_M)) > ] > "TARGET_HAVE_MVE" > @@ -5090,7 +5090,7 @@ (define_insn "mve_vcvtq_m_n_to_f_<supf><mode>" > (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0") > (match_operand:<MVE_CNVT> 2 "s_register_operand" "w") > (match_operand:SI 3 "<MVE_pred2>" "<MVE_constraint2>") > - (match_operand:HI 4 "vpr_register_operand" "Up")] > + (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")] > VCVTQ_M_N_TO_F)) > ] > "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" > @@ -5106,7 +5106,7 @@ (define_insn "mve_vabdq_m_<supf><mode>" > (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") > (match_operand:MVE_2 2 "s_register_operand" "w") > (match_operand:MVE_2 3 "s_register_operand" "w") > - (match_operand:HI 4 "vpr_register_operand" "Up")] > + (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")] > VABDQ_M)) > ] > "TARGET_HAVE_MVE" > @@ -5123,7 +5123,7 @@ (define_insn "mve_vaddq_m_n_<supf><mode>" > (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") > (match_operand:MVE_2 2 "s_register_operand" "w") > (match_operand:<V_elem> 3 "s_register_operand" "r") > - (match_operand:HI 4 "vpr_register_operand" "Up")] > + (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")] > VADDQ_M_N)) > ] > "TARGET_HAVE_MVE" > @@ -5140,7 +5140,7 @@ (define_insn "mve_vaddq_m_<supf><mode>" > (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") > (match_operand:MVE_2 2 "s_register_operand" "w") > (match_operand:MVE_2 3 "s_register_operand" "w") > - (match_operand:HI 4 "vpr_register_operand" "Up")] > + (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")] > VADDQ_M)) > ] > "TARGET_HAVE_MVE" > @@ -5157,7 +5157,7 @@ (define_insn "mve_vandq_m_<supf><mode>" > (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") > (match_operand:MVE_2 2 "s_register_operand" "w") > (match_operand:MVE_2 3 "s_register_operand" "w") > - (match_operand:HI 4 "vpr_register_operand" "Up")] > + (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")] > VANDQ_M)) > ] > "TARGET_HAVE_MVE" > @@ -5174,7 +5174,7 @@ (define_insn "mve_vbicq_m_<supf><mode>" > (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") > (match_operand:MVE_2 2 "s_register_operand" "w") > (match_operand:MVE_2 3 "s_register_operand" "w") > - (match_operand:HI 4 "vpr_register_operand" "Up")] > + (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")] > VBICQ_M)) > ] > "TARGET_HAVE_MVE" > @@ -5191,7 +5191,7 @@ (define_insn "mve_vbrsrq_m_n_<supf><mode>" > (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") > (match_operand:MVE_2 2 "s_register_operand" "w") > (match_operand:SI 3 "s_register_operand" "r") > - (match_operand:HI 4 "vpr_register_operand" "Up")] > + (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")] > VBRSRQ_M_N)) > ] > "TARGET_HAVE_MVE" > @@ -5208,7 +5208,7 @@ (define_insn "mve_vcaddq_rot270_m_<supf><mode>" > (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") > (match_operand:MVE_2 2 "s_register_operand" "w") > (match_operand:MVE_2 3 "s_register_operand" "w") > - (match_operand:HI 4 "vpr_register_operand" "Up")] > + (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")] > VCADDQ_ROT270_M)) > ] > "TARGET_HAVE_MVE" > @@ -5225,7 +5225,7 @@ (define_insn "mve_vcaddq_rot90_m_<supf><mode>" > (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") > (match_operand:MVE_2 2 "s_register_operand" "w") > (match_operand:MVE_2 3 "s_register_operand" "w") > - (match_operand:HI 4 "vpr_register_operand" "Up")] > + (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")] > VCADDQ_ROT90_M)) > ] > "TARGET_HAVE_MVE" > @@ -5242,7 +5242,7 @@ (define_insn "mve_veorq_m_<supf><mode>" > (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") > (match_operand:MVE_2 2 "s_register_operand" "w") > (match_operand:MVE_2 3 "s_register_operand" "w") > - (match_operand:HI 4 "vpr_register_operand" "Up")] > + (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")] > VEORQ_M)) > ] > "TARGET_HAVE_MVE" > @@ -5259,7 +5259,7 @@ (define_insn "mve_vhaddq_m_n_<supf><mode>" > (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") > (match_operand:MVE_2 2 "s_register_operand" "w") > (match_operand:<V_elem> 3 "s_register_operand" "r") > - (match_operand:HI 4 "vpr_register_operand" "Up")] > + (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")] > VHADDQ_M_N)) > ] > "TARGET_HAVE_MVE" > @@ -5276,7 +5276,7 @@ (define_insn "mve_vhaddq_m_<supf><mode>" > (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") > (match_operand:MVE_2 2 "s_register_operand" "w") > (match_operand:MVE_2 3 "s_register_operand" "w") > - (match_operand:HI 4 "vpr_register_operand" "Up")] > + (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")] > VHADDQ_M)) > ] > "TARGET_HAVE_MVE" > @@ -5293,7 +5293,7 @@ (define_insn "mve_vhsubq_m_n_<supf><mode>" > (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") > (match_operand:MVE_2 2 "s_register_operand" "w") > (match_operand:<V_elem> 3 "s_register_operand" "r") > - (match_operand:HI 4 "vpr_register_operand" "Up")] > + (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")] > VHSUBQ_M_N)) > ] > "TARGET_HAVE_MVE" > @@ -5310,7 +5310,7 @@ (define_insn "mve_vhsubq_m_<supf><mode>" > (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") > (match_operand:MVE_2 2 "s_register_operand" "w") > (match_operand:MVE_2 3 "s_register_operand" "w") > - (match_operand:HI 4 "vpr_register_operand" "Up")] > + (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")] > VHSUBQ_M)) > ] > "TARGET_HAVE_MVE" > @@ -5327,7 +5327,7 @@ (define_insn "mve_vmaxq_m_<supf><mode>" > (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") > (match_operand:MVE_2 2 "s_register_operand" "w") > (match_operand:MVE_2 3 "s_register_operand" "w") > - (match_operand:HI 4 "vpr_register_operand" "Up")] > + (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")] > VMAXQ_M)) > ] > "TARGET_HAVE_MVE" > @@ -5344,7 +5344,7 @@ (define_insn "mve_vminq_m_<supf><mode>" > (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") > (match_operand:MVE_2 2 "s_register_operand" "w") > (match_operand:MVE_2 3 "s_register_operand" "w") > - (match_operand:HI 4 "vpr_register_operand" "Up")] > + (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")] > VMINQ_M)) > ] > "TARGET_HAVE_MVE" > @@ -5361,7 +5361,7 @@ (define_insn "mve_vmladavaq_p_<supf><mode>" > (unspec:SI [(match_operand:SI 1 "s_register_operand" "0") > (match_operand:MVE_2 2 "s_register_operand" "w") > (match_operand:MVE_2 3 "s_register_operand" "w") > - (match_operand:HI 4 "vpr_register_operand" "Up")] > + (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")] > VMLADAVAQ_P)) > ] > "TARGET_HAVE_MVE" > @@ -5378,7 +5378,7 @@ (define_insn "mve_vmlaq_m_n_<supf><mode>" > (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") > (match_operand:MVE_2 2 "s_register_operand" "w") > (match_operand:<V_elem> 3 "s_register_operand" "r") > - (match_operand:HI 4 "vpr_register_operand" "Up")] > + (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")] > VMLAQ_M_N)) > ] > "TARGET_HAVE_MVE" > @@ -5395,7 +5395,7 @@ (define_insn "mve_vmlasq_m_n_<supf><mode>" > (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") > (match_operand:MVE_2 2 "s_register_operand" "w") > (match_operand:<V_elem> 3 "s_register_operand" "r") > - (match_operand:HI 4 "vpr_register_operand" "Up")] > + (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")] > VMLASQ_M_N)) > ] > "TARGET_HAVE_MVE" > @@ -5412,7 +5412,7 @@ (define_insn "mve_vmulhq_m_<supf><mode>" > (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") > (match_operand:MVE_2 2 "s_register_operand" "w") > (match_operand:MVE_2 3 "s_register_operand" "w") > - (match_operand:HI 4 "vpr_register_operand" "Up")] > + (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")] > VMULHQ_M)) > ] > "TARGET_HAVE_MVE" > @@ -5429,7 +5429,7 @@ (define_insn "mve_vmullbq_int_m_<supf><mode>" > (unspec:<V_double_width> [(match_operand:<V_double_width> 1 "s_register_operand" "0") > (match_operand:MVE_2 2 "s_register_operand" "w") > (match_operand:MVE_2 3 "s_register_operand" "w") > - (match_operand:HI 4 "vpr_register_operand" "Up")] > + (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")] > VMULLBQ_INT_M)) > ] > "TARGET_HAVE_MVE" > @@ -5446,7 +5446,7 @@ (define_insn "mve_vmulltq_int_m_<supf><mode>" > (unspec:<V_double_width> [(match_operand:<V_double_width> 1 "s_register_operand" "0") > (match_operand:MVE_2 2 "s_register_operand" "w") > (match_operand:MVE_2 3 "s_register_operand" "w") > - (match_operand:HI 4 "vpr_register_operand" "Up")] > + (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")] > VMULLTQ_INT_M)) > ] > "TARGET_HAVE_MVE" > @@ -5463,7 +5463,7 @@ (define_insn "mve_vmulq_m_n_<supf><mode>" > (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") > (match_operand:MVE_2 2 "s_register_operand" "w") > (match_operand:<V_elem> 3 "s_register_operand" "r") > - (match_operand:HI 4 "vpr_register_operand" "Up")] > + (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")] > VMULQ_M_N)) > ] > "TARGET_HAVE_MVE" > @@ -5480,7 +5480,7 @@ (define_insn "mve_vmulq_m_<supf><mode>" > (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") > (match_operand:MVE_2 2 "s_register_operand" "w") > (match_operand:MVE_2 3 "s_register_operand" "w") > - (match_operand:HI 4 "vpr_register_operand" "Up")] > + (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")] > VMULQ_M)) > ] > "TARGET_HAVE_MVE" > @@ -5497,7 +5497,7 @@ (define_insn "mve_vornq_m_<supf><mode>" > (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") > (match_operand:MVE_2 2 "s_register_operand" "w") > (match_operand:MVE_2 3 "s_register_operand" "w") > - (match_operand:HI 4 "vpr_register_operand" "Up")] > + (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")] > VORNQ_M)) > ] > "TARGET_HAVE_MVE" > @@ -5514,7 +5514,7 @@ (define_insn "mve_vorrq_m_<supf><mode>" > (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") > (match_operand:MVE_2 2 "s_register_operand" "w") > (match_operand:MVE_2 3 "s_register_operand" "w") > - (match_operand:HI 4 "vpr_register_operand" "Up")] > + (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")] > VORRQ_M)) > ] > "TARGET_HAVE_MVE" > @@ -5531,7 +5531,7 @@ (define_insn "mve_vqaddq_m_n_<supf><mode>" > (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") > (match_operand:MVE_2 2 "s_register_operand" "w") > (match_operand:<V_elem> 3 "s_register_operand" "r") > - (match_operand:HI 4 "vpr_register_operand" "Up")] > + (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")] > VQADDQ_M_N)) > ] > "TARGET_HAVE_MVE" > @@ -5548,7 +5548,7 @@ (define_insn "mve_vqaddq_m_<supf><mode>" > (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") > (match_operand:MVE_2 2 "s_register_operand" "w") > (match_operand:MVE_2 3 "s_register_operand" "w") > - (match_operand:HI 4 "vpr_register_operand" "Up")] > + (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")] > VQADDQ_M)) > ] > "TARGET_HAVE_MVE" > @@ -5565,7 +5565,7 @@ (define_insn "mve_vqdmlahq_m_n_s<mode>" > (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") > (match_operand:MVE_2 2 "s_register_operand" "w") > (match_operand:<V_elem> 3 "s_register_operand" "r") > - (match_operand:HI 4 "vpr_register_operand" "Up")] > + (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")] > VQDMLAHQ_M_N_S)) > ] > "TARGET_HAVE_MVE" > @@ -5582,7 +5582,7 @@ (define_insn "mve_vqdmlashq_m_n_s<mode>" > (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") > (match_operand:MVE_2 2 "s_register_operand" "w") > (match_operand:<V_elem> 3 "s_register_operand" "r") > - (match_operand:HI 4 "vpr_register_operand" "Up")] > + (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")] > VQDMLASHQ_M_N_S)) > ] > "TARGET_HAVE_MVE" > @@ -5599,7 +5599,7 @@ (define_insn "mve_vqrdmlahq_m_n_s<mode>" > (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") > (match_operand:MVE_2 2 "s_register_operand" "w") > (match_operand:<V_elem> 3 "s_register_operand" "r") > - (match_operand:HI 4 "vpr_register_operand" "Up")] > + (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")] > VQRDMLAHQ_M_N_S)) > ] > "TARGET_HAVE_MVE" > @@ -5616,7 +5616,7 @@ (define_insn "mve_vqrdmlashq_m_n_s<mode>" > (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") > (match_operand:MVE_2 2 "s_register_operand" "w") > (match_operand:<V_elem> 3 "s_register_operand" "r") > - (match_operand:HI 4 "vpr_register_operand" "Up")] > + (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")] > VQRDMLASHQ_M_N_S)) > ] > "TARGET_HAVE_MVE" > @@ -5633,7 +5633,7 @@ (define_insn "mve_vqrshlq_m_<supf><mode>" > (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") > (match_operand:MVE_2 2 "s_register_operand" "w") > (match_operand:MVE_2 3 "s_register_operand" "w") > - (match_operand:HI 4 "vpr_register_operand" "Up")] > + (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")] > VQRSHLQ_M)) > ] > "TARGET_HAVE_MVE" > @@ -5650,7 +5650,7 @@ (define_insn "mve_vqshlq_m_n_<supf><mode>" > (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") > (match_operand:MVE_2 2 "s_register_operand" "w") > (match_operand:SI 3 "immediate_operand" "i") > - (match_operand:HI 4 "vpr_register_operand" "Up")] > + (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")] > VQSHLQ_M_N)) > ] > "TARGET_HAVE_MVE" > @@ -5667,7 +5667,7 @@ (define_insn "mve_vqshlq_m_<supf><mode>" > (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") > (match_operand:MVE_2 2 "s_register_operand" "w") > (match_operand:MVE_2 3 "s_register_operand" "w") > - (match_operand:HI 4 "vpr_register_operand" "Up")] > + (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")] > VQSHLQ_M)) > ] > "TARGET_HAVE_MVE" > @@ -5684,7 +5684,7 @@ (define_insn "mve_vqsubq_m_n_<supf><mode>" > (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") > (match_operand:MVE_2 2 "s_register_operand" "w") > (match_operand:<V_elem> 3 "s_register_operand" "r") > - (match_operand:HI 4 "vpr_register_operand" "Up")] > + (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")] > VQSUBQ_M_N)) > ] > "TARGET_HAVE_MVE" > @@ -5701,7 +5701,7 @@ (define_insn "mve_vqsubq_m_<supf><mode>" > (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") > (match_operand:MVE_2 2 "s_register_operand" "w") > (match_operand:MVE_2 3 "s_register_operand" "w") > - (match_operand:HI 4 "vpr_register_operand" "Up")] > + (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")] > VQSUBQ_M)) > ] > "TARGET_HAVE_MVE" > @@ -5718,7 +5718,7 @@ (define_insn "mve_vrhaddq_m_<supf><mode>" > (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") > (match_operand:MVE_2 2 "s_register_operand" "w") > (match_operand:MVE_2 3 "s_register_operand" "w") > - (match_operand:HI 4 "vpr_register_operand" "Up")] > + (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")] > VRHADDQ_M)) > ] > "TARGET_HAVE_MVE" > @@ -5735,7 +5735,7 @@ (define_insn "mve_vrmulhq_m_<supf><mode>" > (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") > (match_operand:MVE_2 2 "s_register_operand" "w") > (match_operand:MVE_2 3 "s_register_operand" "w") > - (match_operand:HI 4 "vpr_register_operand" "Up")] > + (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")] > VRMULHQ_M)) > ] > "TARGET_HAVE_MVE" > @@ -5752,7 +5752,7 @@ (define_insn "mve_vrshlq_m_<supf><mode>" > (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") > (match_operand:MVE_2 2 "s_register_operand" "w") > (match_operand:MVE_2 3 "s_register_operand" "w") > - (match_operand:HI 4 "vpr_register_operand" "Up")] > + (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")] > VRSHLQ_M)) > ] > "TARGET_HAVE_MVE" > @@ -5769,7 +5769,7 @@ (define_insn "mve_vrshrq_m_n_<supf><mode>" > (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") > (match_operand:MVE_2 2 "s_register_operand" "w") > (match_operand:SI 3 "<MVE_pred2>" "<MVE_constraint2>") > - (match_operand:HI 4 "vpr_register_operand" "Up")] > + (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")] > VRSHRQ_M_N)) > ] > "TARGET_HAVE_MVE" > @@ -5786,7 +5786,7 @@ (define_insn "mve_vshlq_m_n_<supf><mode>" > (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") > (match_operand:MVE_2 2 "s_register_operand" "w") > (match_operand:SI 3 "immediate_operand" "i") > - (match_operand:HI 4 "vpr_register_operand" "Up")] > + (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")] > VSHLQ_M_N)) > ] > "TARGET_HAVE_MVE" > @@ -5803,7 +5803,7 @@ (define_insn "mve_vshrq_m_n_<supf><mode>" > (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") > (match_operand:MVE_2 2 "s_register_operand" "w") > (match_operand:SI 3 "<MVE_pred2>" "<MVE_constraint2>") > - (match_operand:HI 4 "vpr_register_operand" "Up")] > + (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")] > VSHRQ_M_N)) > ] > "TARGET_HAVE_MVE" > @@ -5820,7 +5820,7 @@ (define_insn "mve_vsliq_m_n_<supf><mode>" > (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") > (match_operand:MVE_2 2 "s_register_operand" "w") > (match_operand:SI 3 "<MVE_pred>" "<MVE_constraint>") > - (match_operand:HI 4 "vpr_register_operand" "Up")] > + (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")] > VSLIQ_M_N)) > ] > "TARGET_HAVE_MVE" > @@ -5837,7 +5837,7 @@ (define_insn "mve_vsubq_m_n_<supf><mode>" > (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") > (match_operand:MVE_2 2 "s_register_operand" "w") > (match_operand:<V_elem> 3 "s_register_operand" "r") > - (match_operand:HI 4 "vpr_register_operand" "Up")] > + (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")] > VSUBQ_M_N)) > ] > "TARGET_HAVE_MVE" > @@ -5854,7 +5854,7 @@ (define_insn "mve_vhcaddq_rot270_m_s<mode>" > (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") > (match_operand:MVE_2 2 "s_register_operand" "w") > (match_operand:MVE_2 3 "s_register_operand" "w") > - (match_operand:HI 4 "vpr_register_operand" "Up")] > + (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")] > VHCADDQ_ROT270_M_S)) > ] > "TARGET_HAVE_MVE" > @@ -5871,7 +5871,7 @@ (define_insn "mve_vhcaddq_rot90_m_s<mode>" > (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") > (match_operand:MVE_2 2 "s_register_operand" "w") > (match_operand:MVE_2 3 "s_register_operand" "w") > - (match_operand:HI 4 "vpr_register_operand" "Up")] > + (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")] > VHCADDQ_ROT90_M_S)) > ] > "TARGET_HAVE_MVE" > @@ -5888,7 +5888,7 @@ (define_insn "mve_vmladavaxq_p_s<mode>" > (unspec:SI [(match_operand:SI 1 "s_register_operand" "0") > (match_operand:MVE_2 2 "s_register_operand" "w") > (match_operand:MVE_2 3 "s_register_operand" "w") > - (match_operand:HI 4 "vpr_register_operand" "Up")] > + (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")] > VMLADAVAXQ_P_S)) > ] > "TARGET_HAVE_MVE" > @@ -5905,7 +5905,7 @@ (define_insn "mve_vmlsdavaq_p_s<mode>" > (unspec:SI [(match_operand:SI 1 "s_register_operand" "0") > (match_operand:MVE_2 2 "s_register_operand" "w") > (match_operand:MVE_2 3 "s_register_operand" "w") > - (match_operand:HI 4 "vpr_register_operand" "Up")] > + (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")] > VMLSDAVAQ_P_S)) > ] > "TARGET_HAVE_MVE" > @@ -5922,7 +5922,7 @@ (define_insn "mve_vmlsdavaxq_p_s<mode>" > (unspec:SI [(match_operand:SI 1 "s_register_operand" "0") > (match_operand:MVE_2 2 "s_register_operand" "w") > (match_operand:MVE_2 3 "s_register_operand" "w") > - (match_operand:HI 4 "vpr_register_operand" "Up")] > + (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")] > VMLSDAVAXQ_P_S)) > ] > "TARGET_HAVE_MVE" > @@ -5939,7 +5939,7 @@ (define_insn "mve_vqdmladhq_m_s<mode>" > (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") > (match_operand:MVE_2 2 "s_register_operand" "w") > (match_operand:MVE_2 3 "s_register_operand" "w") > - (match_operand:HI 4 "vpr_register_operand" "Up")] > + (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")] > VQDMLADHQ_M_S)) > ] > "TARGET_HAVE_MVE" > @@ -5956,7 +5956,7 @@ (define_insn "mve_vqdmladhxq_m_s<mode>" > (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") > (match_operand:MVE_2 2 "s_register_operand" "w") > (match_operand:MVE_2 3 "s_register_operand" "w") > - (match_operand:HI 4 "vpr_register_operand" "Up")] > + (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")] > VQDMLADHXQ_M_S)) > ] > "TARGET_HAVE_MVE" > @@ -5973,7 +5973,7 @@ (define_insn "mve_vqdmlsdhq_m_s<mode>" > (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") > (match_operand:MVE_2 2 "s_register_operand" "w") > (match_operand:MVE_2 3 "s_register_operand" "w") > - (match_operand:HI 4 "vpr_register_operand" "Up")] > + (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")] > VQDMLSDHQ_M_S)) > ] > "TARGET_HAVE_MVE" > @@ -5990,7 +5990,7 @@ (define_insn "mve_vqdmlsdhxq_m_s<mode>" > (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") > (match_operand:MVE_2 2 "s_register_operand" "w") > (match_operand:MVE_2 3 "s_register_operand" "w") > - (match_operand:HI 4 "vpr_register_operand" "Up")] > + (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")] > VQDMLSDHXQ_M_S)) > ] > "TARGET_HAVE_MVE" > @@ -6007,7 +6007,7 @@ (define_insn "mve_vqdmulhq_m_n_s<mode>" > (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") > (match_operand:MVE_2 2 "s_register_operand" "w") > (match_operand:<V_elem> 3 "s_register_operand" "r") > - (match_operand:HI 4 "vpr_register_operand" "Up")] > + (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")] > VQDMULHQ_M_N_S)) > ] > "TARGET_HAVE_MVE" > @@ -6024,7 +6024,7 @@ (define_insn "mve_vqdmulhq_m_s<mode>" > (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") > (match_operand:MVE_2 2 "s_register_operand" "w") > (match_operand:MVE_2 3 "s_register_operand" "w") > - (match_operand:HI 4 "vpr_register_operand" "Up")] > + (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")] > VQDMULHQ_M_S)) > ] > "TARGET_HAVE_MVE" > @@ -6041,7 +6041,7 @@ (define_insn "mve_vqrdmladhq_m_s<mode>" > (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") > (match_operand:MVE_2 2 "s_register_operand" "w") > (match_operand:MVE_2 3 "s_register_operand" "w") > - (match_operand:HI 4 "vpr_register_operand" "Up")] > + (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")] > VQRDMLADHQ_M_S)) > ] > "TARGET_HAVE_MVE" > @@ -6058,7 +6058,7 @@ (define_insn "mve_vqrdmladhxq_m_s<mode>" > (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") > (match_operand:MVE_2 2 "s_register_operand" "w") > (match_operand:MVE_2 3 "s_register_operand" "w") > - (match_operand:HI 4 "vpr_register_operand" "Up")] > + (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")] > VQRDMLADHXQ_M_S)) > ] > "TARGET_HAVE_MVE" > @@ -6075,7 +6075,7 @@ (define_insn "mve_vqrdmlsdhq_m_s<mode>" > (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") > (match_operand:MVE_2 2 "s_register_operand" "w") > (match_operand:MVE_2 3 "s_register_operand" "w") > - (match_operand:HI 4 "vpr_register_operand" "Up")] > + (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")] > VQRDMLSDHQ_M_S)) > ] > "TARGET_HAVE_MVE" > @@ -6092,7 +6092,7 @@ (define_insn "mve_vqrdmlsdhxq_m_s<mode>" > (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") > (match_operand:MVE_2 2 "s_register_operand" "w") > (match_operand:MVE_2 3 "s_register_operand" "w") > - (match_operand:HI 4 "vpr_register_operand" "Up")] > + (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")] > VQRDMLSDHXQ_M_S)) > ] > "TARGET_HAVE_MVE" > @@ -6109,7 +6109,7 @@ (define_insn "mve_vqrdmulhq_m_n_s<mode>" > (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") > (match_operand:MVE_2 2 "s_register_operand" "w") > (match_operand:<V_elem> 3 "s_register_operand" "r") > - (match_operand:HI 4 "vpr_register_operand" "Up")] > + (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")] > VQRDMULHQ_M_N_S)) > ] > "TARGET_HAVE_MVE" > @@ -6126,7 +6126,7 @@ (define_insn "mve_vqrdmulhq_m_s<mode>" > (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") > (match_operand:MVE_2 2 "s_register_operand" "w") > (match_operand:MVE_2 3 "s_register_operand" "w") > - (match_operand:HI 4 "vpr_register_operand" "Up")] > + (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")] > VQRDMULHQ_M_S)) > ] > "TARGET_HAVE_MVE" > @@ -6143,7 +6143,7 @@ (define_insn "mve_vmlaldavaq_p_<supf><mode>" > (unspec:DI [(match_operand:DI 1 "s_register_operand" "0") > (match_operand:MVE_5 2 "s_register_operand" "w") > (match_operand:MVE_5 3 "s_register_operand" "w") > - (match_operand:HI 4 "vpr_register_operand" "Up")] > + (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")] > VMLALDAVAQ_P)) > ] > "TARGET_HAVE_MVE" > @@ -6160,7 +6160,7 @@ (define_insn "mve_vmlaldavaxq_p_<supf><mode>" > (unspec:DI [(match_operand:DI 1 "s_register_operand" "0") > (match_operand:MVE_5 2 "s_register_operand" "w") > (match_operand:MVE_5 3 "s_register_operand" "w") > - (match_operand:HI 4 "vpr_register_operand" "Up")] > + (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")] > VMLALDAVAXQ_P)) > ] > "TARGET_HAVE_MVE" > @@ -6177,7 +6177,7 @@ (define_insn "mve_vqrshrnbq_m_n_<supf><mode>" > (unspec:<V_narrow_pack> [(match_operand:<V_narrow_pack> 1 "s_register_operand" "0") > (match_operand:MVE_5 2 "s_register_operand" "w") > (match_operand:SI 3 "mve_imm_8" "Rb") > - (match_operand:HI 4 "vpr_register_operand" "Up")] > + (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")] > VQRSHRNBQ_M_N)) > ] > "TARGET_HAVE_MVE" > @@ -6194,7 +6194,7 @@ (define_insn "mve_vqrshrntq_m_n_<supf><mode>" > (unspec:<V_narrow_pack> [(match_operand:<V_narrow_pack> 1 "s_register_operand" "0") > (match_operand:MVE_5 2 "s_register_operand" "w") > (match_operand:SI 3 "mve_imm_8" "Rb") > - (match_operand:HI 4 "vpr_register_operand" "Up")] > + (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")] > VQRSHRNTQ_M_N)) > ] > "TARGET_HAVE_MVE" > @@ -6211,7 +6211,7 @@ (define_insn "mve_vqshrnbq_m_n_<supf><mode>" > (unspec:<V_narrow_pack> [(match_operand:<V_narrow_pack> 1 "s_register_operand" "0") > (match_operand:MVE_5 2 "s_register_operand" "w") > (match_operand:SI 3 "<MVE_pred3>" "<MVE_constraint3>") > - (match_operand:HI 4 "vpr_register_operand" "Up")] > + (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")] > VQSHRNBQ_M_N)) > ] > "TARGET_HAVE_MVE" > @@ -6228,7 +6228,7 @@ (define_insn "mve_vqshrntq_m_n_<supf><mode>" > (unspec:<V_narrow_pack> [(match_operand:<V_narrow_pack> 1 "s_register_operand" "0") > (match_operand:MVE_5 2 "s_register_operand" "w") > (match_operand:SI 3 "<MVE_pred3>" "<MVE_constraint3>") > - (match_operand:HI 4 "vpr_register_operand" "Up")] > + (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")] > VQSHRNTQ_M_N)) > ] > "TARGET_HAVE_MVE" > @@ -6262,7 +6262,7 @@ (define_insn "mve_vrshrnbq_m_n_<supf><mode>" > (unspec:<V_narrow_pack> [(match_operand:<V_narrow_pack> 1 "s_register_operand" "0") > (match_operand:MVE_5 2 "s_register_operand" "w") > (match_operand:SI 3 "mve_imm_8" "Rb") > - (match_operand:HI 4 "vpr_register_operand" "Up")] > + (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")] > VRSHRNBQ_M_N)) > ] > "TARGET_HAVE_MVE" > @@ -6279,7 +6279,7 @@ (define_insn "mve_vrshrntq_m_n_<supf><mode>" > (unspec:<V_narrow_pack> [(match_operand:<V_narrow_pack> 1 "s_register_operand" "0") > (match_operand:MVE_5 2 "s_register_operand" "w") > (match_operand:SI 3 "mve_imm_8" "Rb") > - (match_operand:HI 4 "vpr_register_operand" "Up")] > + (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")] > VRSHRNTQ_M_N)) > ] > "TARGET_HAVE_MVE" > @@ -6296,7 +6296,7 @@ (define_insn "mve_vshllbq_m_n_<supf><mode>" > (unspec:<V_double_width> [(match_operand:<V_double_width> 1 "s_register_operand" "0") > (match_operand:MVE_3 2 "s_register_operand" "w") > (match_operand:SI 3 "immediate_operand" "i") > - (match_operand:HI 4 "vpr_register_operand" "Up")] > + (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")] > VSHLLBQ_M_N)) > ] > "TARGET_HAVE_MVE" > @@ -6313,7 +6313,7 @@ (define_insn "mve_vshlltq_m_n_<supf><mode>" > (unspec:<V_double_width> [(match_operand:<V_double_width> 1 "s_register_operand" "0") > (match_operand:MVE_3 2 "s_register_operand" "w") > (match_operand:SI 3 "immediate_operand" "i") > - (match_operand:HI 4 "vpr_register_operand" "Up")] > + (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")] > VSHLLTQ_M_N)) > ] > "TARGET_HAVE_MVE" > @@ -6330,7 +6330,7 @@ (define_insn "mve_vshrnbq_m_n_<supf><mode>" > (unspec:<V_narrow_pack> [(match_operand:<V_narrow_pack> 1 "s_register_operand" "0") > (match_operand:MVE_5 2 "s_register_operand" "w") > (match_operand:SI 3 "<MVE_pred3>" "<MVE_constraint3>") > - (match_operand:HI 4 "vpr_register_operand" "Up")] > + (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")] > VSHRNBQ_M_N)) > ] > "TARGET_HAVE_MVE" > @@ -6347,7 +6347,7 @@ (define_insn "mve_vshrntq_m_n_<supf><mode>" > (unspec:<V_narrow_pack> [(match_operand:<V_narrow_pack> 1 "s_register_operand" "0") > (match_operand:MVE_5 2 "s_register_operand" "w") > (match_operand:SI 3 "<MVE_pred3>" "<MVE_constraint3>") > - (match_operand:HI 4 "vpr_register_operand" "Up")] > + (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")] > VSHRNTQ_M_N)) > ] > "TARGET_HAVE_MVE" > @@ -6364,7 +6364,7 @@ (define_insn "mve_vmlsldavaq_p_s<mode>" > (unspec:DI [(match_operand:DI 1 "s_register_operand" "0") > (match_operand:MVE_5 2 "s_register_operand" "w") > (match_operand:MVE_5 3 "s_register_operand" "w") > - (match_operand:HI 4 "vpr_register_operand" "Up")] > + (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")] > VMLSLDAVAQ_P_S)) > ] > "TARGET_HAVE_MVE" > @@ -6381,7 +6381,7 @@ (define_insn "mve_vmlsldavaxq_p_s<mode>" > (unspec:DI [(match_operand:DI 1 "s_register_operand" "0") > (match_operand:MVE_5 2 "s_register_operand" "w") > (match_operand:MVE_5 3 "s_register_operand" "w") > - (match_operand:HI 4 "vpr_register_operand" "Up")] > + (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")] > VMLSLDAVAXQ_P_S)) > ] > "TARGET_HAVE_MVE" > @@ -6398,7 +6398,7 @@ (define_insn "mve_vmullbq_poly_m_p<mode>" > (unspec:<V_double_width> [(match_operand:<V_double_width> 1 "s_register_operand" "0") > (match_operand:MVE_3 2 "s_register_operand" "w") > (match_operand:MVE_3 3 "s_register_operand" "w") > - (match_operand:HI 4 "vpr_register_operand" "Up")] > + (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")] > VMULLBQ_POLY_M_P)) > ] > "TARGET_HAVE_MVE" > @@ -6415,7 +6415,7 @@ (define_insn "mve_vmulltq_poly_m_p<mode>" > (unspec:<V_double_width> [(match_operand:<V_double_width> 1 "s_register_operand" "0") > (match_operand:MVE_3 2 "s_register_operand" "w") > (match_operand:MVE_3 3 "s_register_operand" "w") > - (match_operand:HI 4 "vpr_register_operand" "Up")] > + (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")] > VMULLTQ_POLY_M_P)) > ] > "TARGET_HAVE_MVE" > @@ -6432,7 +6432,7 @@ (define_insn "mve_vqdmullbq_m_n_s<mode>" > (unspec:<V_double_width> [(match_operand:<V_double_width> 1 "s_register_operand" "0") > (match_operand:MVE_5 2 "s_register_operand" "w") > (match_operand:<V_elem> 3 "s_register_operand" "r") > - (match_operand:HI 4 "vpr_register_operand" "Up")] > + (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")] > VQDMULLBQ_M_N_S)) > ] > "TARGET_HAVE_MVE" > @@ -6449,7 +6449,7 @@ (define_insn "mve_vqdmullbq_m_s<mode>" > (unspec:<V_double_width> [(match_operand:<V_double_width> 1 "s_register_operand" "0") > (match_operand:MVE_5 2 "s_register_operand" "w") > (match_operand:MVE_5 3 "s_register_operand" "w") > - (match_operand:HI 4 "vpr_register_operand" "Up")] > + (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")] > VQDMULLBQ_M_S)) > ] > "TARGET_HAVE_MVE" > @@ -6466,7 +6466,7 @@ (define_insn "mve_vqdmulltq_m_n_s<mode>" > (unspec:<V_double_width> [(match_operand:<V_double_width> 1 "s_register_operand" "0") > (match_operand:MVE_5 2 "s_register_operand" "w") > (match_operand:<V_elem> 3 "s_register_operand" "r") > - (match_operand:HI 4 "vpr_register_operand" "Up")] > + (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")] > VQDMULLTQ_M_N_S)) > ] > "TARGET_HAVE_MVE" > @@ -6483,7 +6483,7 @@ (define_insn "mve_vqdmulltq_m_s<mode>" > (unspec:<V_double_width> [(match_operand:<V_double_width> 1 "s_register_operand" "0") > (match_operand:MVE_5 2 "s_register_operand" "w") > (match_operand:MVE_5 3 "s_register_operand" "w") > - (match_operand:HI 4 "vpr_register_operand" "Up")] > + (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")] > VQDMULLTQ_M_S)) > ] > "TARGET_HAVE_MVE" > @@ -6500,7 +6500,7 @@ (define_insn "mve_vqrshrunbq_m_n_s<mode>" > (unspec:<V_narrow_pack> [(match_operand:<V_narrow_pack> 1 "s_register_operand" "0") > (match_operand:MVE_5 2 "s_register_operand" "w") > (match_operand:SI 3 "mve_imm_8" "Rb") > - (match_operand:HI 4 "vpr_register_operand" "Up")] > + (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")] > VQRSHRUNBQ_M_N_S)) > ] > "TARGET_HAVE_MVE" > @@ -6517,7 +6517,7 @@ (define_insn "mve_vqrshruntq_m_n_s<mode>" > (unspec:<V_narrow_pack> [(match_operand:<V_narrow_pack> 1 "s_register_operand" "0") > (match_operand:MVE_5 2 "s_register_operand" "w") > (match_operand:SI 3 "<MVE_pred3>" "<MVE_constraint3>") > - (match_operand:HI 4 "vpr_register_operand" "Up")] > + (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")] > VQRSHRUNTQ_M_N_S)) > ] > "TARGET_HAVE_MVE" > @@ -6534,7 +6534,7 @@ (define_insn "mve_vqshrunbq_m_n_s<mode>" > (unspec:<V_narrow_pack> [(match_operand:<V_narrow_pack> 1 "s_register_operand" "0") > (match_operand:MVE_5 2 "s_register_operand" "w") > (match_operand:SI 3 "<MVE_pred3>" "<MVE_constraint3>") > - (match_operand:HI 4 "vpr_register_operand" "Up")] > + (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")] > VQSHRUNBQ_M_N_S)) > ] > "TARGET_HAVE_MVE" > @@ -6551,7 +6551,7 @@ (define_insn "mve_vqshruntq_m_n_s<mode>" > (unspec:<V_narrow_pack> [(match_operand:<V_narrow_pack> 1 "s_register_operand" "0") > (match_operand:MVE_5 2 "s_register_operand" "w") > (match_operand:SI 3 "<MVE_pred3>" "<MVE_constraint3>") > - (match_operand:HI 4 "vpr_register_operand" "Up")] > + (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")] > VQSHRUNTQ_M_N_S)) > ] > "TARGET_HAVE_MVE" > @@ -6635,7 +6635,7 @@ (define_insn "mve_vabdq_m_f<mode>" > (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0") > (match_operand:MVE_0 2 "s_register_operand" "w") > (match_operand:MVE_0 3 "s_register_operand" "w") > - (match_operand:HI 4 "vpr_register_operand" "Up")] > + (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")] > VABDQ_M_F)) > ] > "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" > @@ -6652,7 +6652,7 @@ (define_insn "mve_vaddq_m_f<mode>" > (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0") > (match_operand:MVE_0 2 "s_register_operand" "w") > (match_operand:MVE_0 3 "s_register_operand" "w") > - (match_operand:HI 4 "vpr_register_operand" "Up")] > + (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")] > VADDQ_M_F)) > ] > "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" > @@ -6669,7 +6669,7 @@ (define_insn "mve_vaddq_m_n_f<mode>" > (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0") > (match_operand:MVE_0 2 "s_register_operand" "w") > (match_operand:<V_elem> 3 "s_register_operand" "r") > - (match_operand:HI 4 "vpr_register_operand" "Up")] > + (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")] > VADDQ_M_N_F)) > ] > "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" > @@ -6686,7 +6686,7 @@ (define_insn "mve_vandq_m_f<mode>" > (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0") > (match_operand:MVE_0 2 "s_register_operand" "w") > (match_operand:MVE_0 3 "s_register_operand" "w") > - (match_operand:HI 4 "vpr_register_operand" "Up")] > + (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")] > VANDQ_M_F)) > ] > "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" > @@ -6703,7 +6703,7 @@ (define_insn "mve_vbicq_m_f<mode>" > (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0") > (match_operand:MVE_0 2 "s_register_operand" "w") > (match_operand:MVE_0 3 "s_register_operand" "w") > - (match_operand:HI 4 "vpr_register_operand" "Up")] > + (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")] > VBICQ_M_F)) > ] > "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" > @@ -6720,7 +6720,7 @@ (define_insn "mve_vbrsrq_m_n_f<mode>" > (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0") > (match_operand:MVE_0 2 "s_register_operand" "w") > (match_operand:SI 3 "s_register_operand" "r") > - (match_operand:HI 4 "vpr_register_operand" "Up")] > + (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")] > VBRSRQ_M_N_F)) > ] > "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" > @@ -6737,7 +6737,7 @@ (define_insn "mve_vcaddq_rot270_m_f<mode>" > (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0") > (match_operand:MVE_0 2 "s_register_operand" "w") > (match_operand:MVE_0 3 "s_register_operand" "w") > - (match_operand:HI 4 "vpr_register_operand" "Up")] > + (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")] > VCADDQ_ROT270_M_F)) > ] > "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" > @@ -6754,7 +6754,7 @@ (define_insn "mve_vcaddq_rot90_m_f<mode>" > (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0") > (match_operand:MVE_0 2 "s_register_operand" "w") > (match_operand:MVE_0 3 "s_register_operand" "w") > - (match_operand:HI 4 "vpr_register_operand" "Up")] > + (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")] > VCADDQ_ROT90_M_F)) > ] > "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" > @@ -6771,7 +6771,7 @@ (define_insn "mve_vcmlaq_m_f<mode>" > (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0") > (match_operand:MVE_0 2 "s_register_operand" "w") > (match_operand:MVE_0 3 "s_register_operand" "w") > - (match_operand:HI 4 "vpr_register_operand" "Up")] > + (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")] > VCMLAQ_M_F)) > ] > "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" > @@ -6788,7 +6788,7 @@ (define_insn "mve_vcmlaq_rot180_m_f<mode>" > (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0") > (match_operand:MVE_0 2 "s_register_operand" "w") > (match_operand:MVE_0 3 "s_register_operand" "w") > - (match_operand:HI 4 "vpr_register_operand" "Up")] > + (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")] > VCMLAQ_ROT180_M_F)) > ] > "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" > @@ -6805,7 +6805,7 @@ (define_insn "mve_vcmlaq_rot270_m_f<mode>" > (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0") > (match_operand:MVE_0 2 "s_register_operand" "w") > (match_operand:MVE_0 3 "s_register_operand" "w") > - (match_operand:HI 4 "vpr_register_operand" "Up")] > + (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")] > VCMLAQ_ROT270_M_F)) > ] > "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" > @@ -6822,7 +6822,7 @@ (define_insn "mve_vcmlaq_rot90_m_f<mode>" > (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0") > (match_operand:MVE_0 2 "s_register_operand" "w") > (match_operand:MVE_0 3 "s_register_operand" "w") > - (match_operand:HI 4 "vpr_register_operand" "Up")] > + (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")] > VCMLAQ_ROT90_M_F)) > ] > "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" > @@ -6839,7 +6839,7 @@ (define_insn "mve_vcmulq_m_f<mode>" > (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0") > (match_operand:MVE_0 2 "s_register_operand" "w") > (match_operand:MVE_0 3 "s_register_operand" "w") > - (match_operand:HI 4 "vpr_register_operand" "Up")] > + (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")] > VCMULQ_M_F)) > ] > "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" > @@ -6856,7 +6856,7 @@ (define_insn "mve_vcmulq_rot180_m_f<mode>" > (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0") > (match_operand:MVE_0 2 "s_register_operand" "w") > (match_operand:MVE_0 3 "s_register_operand" "w") > - (match_operand:HI 4 "vpr_register_operand" "Up")] > + (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")] > VCMULQ_ROT180_M_F)) > ] > "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" > @@ -6873,7 +6873,7 @@ (define_insn "mve_vcmulq_rot270_m_f<mode>" > (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0") > (match_operand:MVE_0 2 "s_register_operand" "w") > (match_operand:MVE_0 3 "s_register_operand" "w") > - (match_operand:HI 4 "vpr_register_operand" "Up")] > + (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")] > VCMULQ_ROT270_M_F)) > ] > "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" > @@ -6890,7 +6890,7 @@ (define_insn "mve_vcmulq_rot90_m_f<mode>" > (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0") > (match_operand:MVE_0 2 "s_register_operand" "w") > (match_operand:MVE_0 3 "s_register_operand" "w") > - (match_operand:HI 4 "vpr_register_operand" "Up")] > + (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")] > VCMULQ_ROT90_M_F)) > ] > "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" > @@ -6907,7 +6907,7 @@ (define_insn "mve_veorq_m_f<mode>" > (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0") > (match_operand:MVE_0 2 "s_register_operand" "w") > (match_operand:MVE_0 3 "s_register_operand" "w") > - (match_operand:HI 4 "vpr_register_operand" "Up")] > + (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")] > VEORQ_M_F)) > ] > "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" > @@ -6924,7 +6924,7 @@ (define_insn "mve_vfmaq_m_f<mode>" > (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0") > (match_operand:MVE_0 2 "s_register_operand" "w") > (match_operand:MVE_0 3 "s_register_operand" "w") > - (match_operand:HI 4 "vpr_register_operand" "Up")] > + (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")] > VFMAQ_M_F)) > ] > "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" > @@ -6941,7 +6941,7 @@ (define_insn "mve_vfmaq_m_n_f<mode>" > (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0") > (match_operand:MVE_0 2 "s_register_operand" "w") > (match_operand:<V_elem> 3 "s_register_operand" "r") > - (match_operand:HI 4 "vpr_register_operand" "Up")] > + (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")] > VFMAQ_M_N_F)) > ] > "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" > @@ -6958,7 +6958,7 @@ (define_insn "mve_vfmasq_m_n_f<mode>" > (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0") > (match_operand:MVE_0 2 "s_register_operand" "w") > (match_operand:<V_elem> 3 "s_register_operand" "r") > - (match_operand:HI 4 "vpr_register_operand" "Up")] > + (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")] > VFMASQ_M_N_F)) > ] > "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" > @@ -6975,7 +6975,7 @@ (define_insn "mve_vfmsq_m_f<mode>" > (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0") > (match_operand:MVE_0 2 "s_register_operand" "w") > (match_operand:MVE_0 3 "s_register_operand" "w") > - (match_operand:HI 4 "vpr_register_operand" "Up")] > + (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")] > VFMSQ_M_F)) > ] > "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" > @@ -6992,7 +6992,7 @@ (define_insn "mve_vmaxnmq_m_f<mode>" > (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0") > (match_operand:MVE_0 2 "s_register_operand" "w") > (match_operand:MVE_0 3 "s_register_operand" "w") > - (match_operand:HI 4 "vpr_register_operand" "Up")] > + (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")] > VMAXNMQ_M_F)) > ] > "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" > @@ -7009,7 +7009,7 @@ (define_insn "mve_vminnmq_m_f<mode>" > (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0") > (match_operand:MVE_0 2 "s_register_operand" "w") > (match_operand:MVE_0 3 "s_register_operand" "w") > - (match_operand:HI 4 "vpr_register_operand" "Up")] > + (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")] > VMINNMQ_M_F)) > ] > "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" > @@ -7026,7 +7026,7 @@ (define_insn "mve_vmulq_m_f<mode>" > (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0") > (match_operand:MVE_0 2 "s_register_operand" "w") > (match_operand:MVE_0 3 "s_register_operand" "w") > - (match_operand:HI 4 "vpr_register_operand" "Up")] > + (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")] > VMULQ_M_F)) > ] > "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" > @@ -7043,7 +7043,7 @@ (define_insn "mve_vmulq_m_n_f<mode>" > (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0") > (match_operand:MVE_0 2 "s_register_operand" "w") > (match_operand:<V_elem> 3 "s_register_operand" "r") > - (match_operand:HI 4 "vpr_register_operand" "Up")] > + (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")] > VMULQ_M_N_F)) > ] > "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" > @@ -7060,7 +7060,7 @@ (define_insn "mve_vornq_m_f<mode>" > (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0") > (match_operand:MVE_0 2 "s_register_operand" "w") > (match_operand:MVE_0 3 "s_register_operand" "w") > - (match_operand:HI 4 "vpr_register_operand" "Up")] > + (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")] > VORNQ_M_F)) > ] > "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" > @@ -7077,7 +7077,7 @@ (define_insn "mve_vorrq_m_f<mode>" > (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0") > (match_operand:MVE_0 2 "s_register_operand" "w") > (match_operand:MVE_0 3 "s_register_operand" "w") > - (match_operand:HI 4 "vpr_register_operand" "Up")] > + (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")] > VORRQ_M_F)) > ] > "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" > @@ -7094,7 +7094,7 @@ (define_insn "mve_vsubq_m_f<mode>" > (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0") > (match_operand:MVE_0 2 "s_register_operand" "w") > (match_operand:MVE_0 3 "s_register_operand" "w") > - (match_operand:HI 4 "vpr_register_operand" "Up")] > + (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")] > VSUBQ_M_F)) > ] > "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" > @@ -7111,7 +7111,7 @@ (define_insn "mve_vsubq_m_n_f<mode>" > (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0") > (match_operand:MVE_0 2 "s_register_operand" "w") > (match_operand:<V_elem> 3 "s_register_operand" "r") > - (match_operand:HI 4 "vpr_register_operand" "Up")] > + (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")] > VSUBQ_M_N_F)) > ] > "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" > @@ -7260,7 +7260,7 @@ (define_expand "mve_vstrbq_scatter_offset_p_<supf><mode>" > [(match_operand:<MVE_B_ELEM> 0 "mve_scatter_memory") > (match_operand:MVE_2 1 "s_register_operand") > (match_operand:MVE_2 2 "s_register_operand") > - (match_operand:HI 3 "vpr_register_operand" "Up") > + (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up") > (unspec:V4SI [(const_int 0)] VSTRBSOQ)] > "TARGET_HAVE_MVE" > { > @@ -7279,7 +7279,7 @@ (define_insn "mve_vstrbq_scatter_offset_p_<supf><mode>_insn" > [(match_operand:SI 0 "register_operand" "r") > (match_operand:MVE_2 1 "s_register_operand" "w") > (match_operand:MVE_2 2 "s_register_operand" "w") > - (match_operand:HI 3 "vpr_register_operand" "Up")] > + (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")] > VSTRBSOQ))] > "TARGET_HAVE_MVE" > "vpst\;vstrbt.<V_sz_elem>\t%q2, [%0, %q1]" > @@ -7314,7 +7314,7 @@ (define_insn "mve_vstrwq_scatter_base_p_<supf>v4si" > (define_insn "mve_vstrbq_p_<supf><mode>" > [(set (match_operand:<MVE_B_ELEM> 0 "mve_memory_operand" "=Ux") > (unspec:<MVE_B_ELEM> [(match_operand:MVE_2 1 "s_register_operand" "w") > - (match_operand:HI 2 "vpr_register_operand" "Up")] > + (match_operand:<MVE_VPRED> 2 "vpr_register_operand" "Up")] > VSTRBQ)) > ] > "TARGET_HAVE_MVE" > @@ -7335,7 +7335,7 @@ (define_insn "mve_vldrbq_gather_offset_z_<supf><mode>" > [(set (match_operand:MVE_2 0 "s_register_operand" "=&w") > (unspec:MVE_2 [(match_operand:<MVE_B_ELEM> 1 "memory_operand" "Us") > (match_operand:MVE_2 2 "s_register_operand" "w") > - (match_operand:HI 3 "vpr_register_operand" "Up")] > + (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")] > VLDRBGOQ)) > ] > "TARGET_HAVE_MVE" > @@ -7359,7 +7359,7 @@ (define_insn "mve_vldrbq_gather_offset_z_<supf><mode>" > (define_insn "mve_vldrbq_z_<supf><mode>" > [(set (match_operand:MVE_2 0 "s_register_operand" "=w") > (unspec:MVE_2 [(match_operand:<MVE_B_ELEM> 1 "mve_memory_operand" "Ux") > - (match_operand:HI 2 "vpr_register_operand" "Up")] > + (match_operand:<MVE_VPRED> 2 "vpr_register_operand" "Up")] > VLDRBQ)) > ] > "TARGET_HAVE_MVE" > @@ -7446,7 +7446,7 @@ (define_insn "mve_vldrhq_gather_offset_z_<supf><mode>" > [(set (match_operand:MVE_6 0 "s_register_operand" "=&w") > (unspec:MVE_6 [(match_operand:<MVE_H_ELEM> 1 "memory_operand" "Us") > (match_operand:MVE_6 2 "s_register_operand" "w") > - (match_operand:HI 3 "vpr_register_operand" "Up") > + (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up") > ]VLDRHGOQ)) > ] > "TARGET_HAVE_MVE" > @@ -7494,7 +7494,7 @@ (define_insn "mve_vldrhq_gather_shifted_offset_z_<supf><mode>" > [(set (match_operand:MVE_6 0 "s_register_operand" "=&w") > (unspec:MVE_6 [(match_operand:<MVE_H_ELEM> 1 "memory_operand" "Us") > (match_operand:MVE_6 2 "s_register_operand" "w") > - (match_operand:HI 3 "vpr_register_operand" "Up") > + (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up") > ]VLDRHGSOQ)) > ] > "TARGET_HAVE_MVE" > @@ -7560,7 +7560,7 @@ (define_insn "mve_vldrhq_z_fv8hf" > (define_insn "mve_vldrhq_z_<supf><mode>" > [(set (match_operand:MVE_6 0 "s_register_operand" "=w") > (unspec:MVE_6 [(match_operand:<MVE_H_ELEM> 1 "mve_memory_operand" "Ux") > - (match_operand:HI 2 "vpr_register_operand" "Up")] > + (match_operand:<MVE_VPRED> 2 "vpr_register_operand" "Up")] > VLDRHQ)) > ] > "TARGET_HAVE_MVE" > @@ -8136,7 +8136,7 @@ (define_insn "mve_vstrhq_p_fv8hf" > (define_insn "mve_vstrhq_p_<supf><mode>" > [(set (match_operand:<MVE_H_ELEM> 0 "mve_memory_operand" "=Ux") > (unspec:<MVE_H_ELEM> [(match_operand:MVE_6 1 "s_register_operand" "w") > - (match_operand:HI 2 "vpr_register_operand" "Up")] > + (match_operand:<MVE_VPRED> 2 "vpr_register_operand" "Up")] > VSTRHQ)) > ] > "TARGET_HAVE_MVE" > @@ -8157,7 +8157,7 @@ (define_expand "mve_vstrhq_scatter_offset_p_<supf><mode>" > [(match_operand:<MVE_H_ELEM> 0 "mve_scatter_memory") > (match_operand:MVE_6 1 "s_register_operand") > (match_operand:MVE_6 2 "s_register_operand") > - (match_operand:HI 3 "vpr_register_operand") > + (match_operand:<MVE_VPRED> 3 "vpr_register_operand") > (unspec:V4SI [(const_int 0)] VSTRHSOQ)] > "TARGET_HAVE_MVE" > { > @@ -8176,7 +8176,7 @@ (define_insn "mve_vstrhq_scatter_offset_p_<supf><mode>_insn" > [(match_operand:SI 0 "register_operand" "r") > (match_operand:MVE_6 1 "s_register_operand" "w") > (match_operand:MVE_6 2 "s_register_operand" "w") > - (match_operand:HI 3 "vpr_register_operand" "Up")] > + (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")] > VSTRHSOQ))] > "TARGET_HAVE_MVE" > "vpst\;vstrht.<V_sz_elem>\t%q2, [%0, %q1]" > @@ -8217,7 +8217,7 @@ (define_expand "mve_vstrhq_scatter_shifted_offset_p_<supf><mode>" > [(match_operand:<MVE_H_ELEM> 0 "mve_scatter_memory") > (match_operand:MVE_6 1 "s_register_operand") > (match_operand:MVE_6 2 "s_register_operand") > - (match_operand:HI 3 "vpr_register_operand") > + (match_operand:<MVE_VPRED> 3 "vpr_register_operand") > (unspec:V4SI [(const_int 0)] VSTRHSSOQ)] > "TARGET_HAVE_MVE" > { > @@ -8236,7 +8236,7 @@ (define_insn "mve_vstrhq_scatter_shifted_offset_p_<supf><mode>_insn" > [(match_operand:SI 0 "register_operand" "r") > (match_operand:MVE_6 1 "s_register_operand" "w") > (match_operand:MVE_6 2 "s_register_operand" "w") > - (match_operand:HI 3 "vpr_register_operand" "Up")] > + (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")] > VSTRHSSOQ))] > "TARGET_HAVE_MVE" > "vpst\;vstrht.<V_sz_elem>\t%q2, [%0, %q1, uxtw #1]" > @@ -9023,7 +9023,7 @@ (define_expand "mve_vidupq_m_n_u<mode>" > (match_operand:MVE_2 1 "s_register_operand") > (match_operand:SI 2 "s_register_operand") > (match_operand:SI 3 "mve_imm_selective_upto_8") > - (match_operand:HI 4 "vpr_register_operand")] > + (match_operand:<MVE_VPRED> 4 "vpr_register_operand")] > "TARGET_HAVE_MVE" > { > rtx temp = gen_reg_rtx (SImode); > @@ -9043,7 +9043,7 @@ (define_insn "mve_vidupq_m_wb_u<mode>_insn" > (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") > (match_operand:SI 3 "s_register_operand" "2") > (match_operand:SI 4 "mve_imm_selective_upto_8" "Rg") > - (match_operand:HI 5 "vpr_register_operand" "Up")] > + (match_operand:<MVE_VPRED> 5 "vpr_register_operand" "Up")] > VIDUPQ_M)) > (set (match_operand:SI 2 "s_register_operand" "=Te") > (plus:SI (match_dup 3) > @@ -9091,7 +9091,7 @@ (define_expand "mve_vddupq_m_n_u<mode>" > (match_operand:MVE_2 1 "s_register_operand") > (match_operand:SI 2 "s_register_operand") > (match_operand:SI 3 "mve_imm_selective_upto_8") > - (match_operand:HI 4 "vpr_register_operand")] > + (match_operand:<MVE_VPRED> 4 "vpr_register_operand")] > "TARGET_HAVE_MVE" > { > rtx temp = gen_reg_rtx (SImode); > @@ -9111,7 +9111,7 @@ (define_insn "mve_vddupq_m_wb_u<mode>_insn" > (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") > (match_operand:SI 3 "s_register_operand" "2") > (match_operand:SI 4 "mve_imm_selective_upto_8" "Rg") > - (match_operand:HI 5 "vpr_register_operand" "Up")] > + (match_operand:<MVE_VPRED> 5 "vpr_register_operand" "Up")] > VDDUPQ_M)) > (set (match_operand:SI 2 "s_register_operand" "=Te") > (minus:SI (match_dup 3) > @@ -9182,7 +9182,7 @@ (define_expand "mve_vdwdupq_m_n_u<mode>" > (match_operand:SI 2 "s_register_operand") > (match_operand:DI 3 "s_register_operand") > (match_operand:SI 4 "mve_imm_selective_upto_8") > - (match_operand:HI 5 "vpr_register_operand")] > + (match_operand:<MVE_VPRED> 5 "vpr_register_operand")] > "TARGET_HAVE_MVE" > { > rtx ignore_wb = gen_reg_rtx (SImode); > @@ -9202,7 +9202,7 @@ (define_expand "mve_vdwdupq_m_wb_u<mode>" > (match_operand:SI 2 "s_register_operand") > (match_operand:DI 3 "s_register_operand") > (match_operand:SI 4 "mve_imm_selective_upto_8") > - (match_operand:HI 5 "vpr_register_operand")] > + (match_operand:<MVE_VPRED> 5 "vpr_register_operand")] > "TARGET_HAVE_MVE" > { > rtx ignore_vec = gen_reg_rtx (<MODE>mode); > @@ -9222,7 +9222,7 @@ (define_insn "mve_vdwdupq_m_wb_u<mode>_insn" > (match_operand:SI 3 "s_register_operand" "1") > (subreg:SI (match_operand:DI 4 "s_register_operand" "r") 4) > (match_operand:SI 5 "mve_imm_selective_upto_8" "Rg") > - (match_operand:HI 6 "vpr_register_operand" "Up")] > + (match_operand:<MVE_VPRED> 6 "vpr_register_operand" "Up")] > VDWDUPQ_M)) > (set (match_operand:SI 1 "s_register_operand" "=Te") > (unspec:SI [(match_dup 2) > @@ -9299,7 +9299,7 @@ (define_expand "mve_viwdupq_m_n_u<mode>" > (match_operand:SI 2 "s_register_operand") > (match_operand:DI 3 "s_register_operand") > (match_operand:SI 4 "mve_imm_selective_upto_8") > - (match_operand:HI 5 "vpr_register_operand")] > + (match_operand:<MVE_VPRED> 5 "vpr_register_operand")] > "TARGET_HAVE_MVE" > { > rtx ignore_wb = gen_reg_rtx (SImode); > @@ -9319,7 +9319,7 @@ (define_expand "mve_viwdupq_m_wb_u<mode>" > (match_operand:SI 2 "s_register_operand") > (match_operand:DI 3 "s_register_operand") > (match_operand:SI 4 "mve_imm_selective_upto_8") > - (match_operand:HI 5 "vpr_register_operand")] > + (match_operand:<MVE_VPRED> 5 "vpr_register_operand")] > "TARGET_HAVE_MVE" > { > rtx ignore_vec = gen_reg_rtx (<MODE>mode); > @@ -9339,7 +9339,7 @@ (define_insn "mve_viwdupq_m_wb_u<mode>_insn" > (match_operand:SI 3 "s_register_operand" "1") > (subreg:SI (match_operand:DI 4 "s_register_operand" "r") 4) > (match_operand:SI 5 "mve_imm_selective_upto_8" "Rg") > - (match_operand:HI 6 "vpr_register_operand" "Up")] > + (match_operand:<MVE_VPRED> 6 "vpr_register_operand" "Up")] > VIWDUPQ_M)) > (set (match_operand:SI 1 "s_register_operand" "=Te") > (unspec:SI [(match_dup 2) > @@ -10347,7 +10347,7 @@ (define_expand "mve_vshlcq_m_vec_<supf><mode>" > (match_operand:MVE_2 1 "s_register_operand") > (match_operand:SI 2 "s_register_operand") > (match_operand:SI 3 "mve_imm_32") > - (match_operand:HI 4 "vpr_register_operand") > + (match_operand:<MVE_VPRED> 4 "vpr_register_operand") > (unspec:MVE_2 [(const_int 0)] VSHLCQ_M)] > "TARGET_HAVE_MVE" > { > @@ -10363,7 +10363,7 @@ (define_expand "mve_vshlcq_m_carry_<supf><mode>" > (match_operand:MVE_2 1 "s_register_operand") > (match_operand:SI 2 "s_register_operand") > (match_operand:SI 3 "mve_imm_32") > - (match_operand:HI 4 "vpr_register_operand") > + (match_operand:<MVE_VPRED> 4 "vpr_register_operand") > (unspec:MVE_2 [(const_int 0)] VSHLCQ_M)] > "TARGET_HAVE_MVE" > { > @@ -10379,7 +10379,7 @@ (define_insn "mve_vshlcq_m_<supf><mode>" > (unspec:MVE_2 [(match_operand:MVE_2 2 "s_register_operand" "0") > (match_operand:SI 3 "s_register_operand" "1") > (match_operand:SI 4 "mve_imm_32" "Rf") > - (match_operand:HI 5 "vpr_register_operand" "Up")] > + (match_operand:<MVE_VPRED> 5 "vpr_register_operand" "Up")] > VSHLCQ_M)) > (set (match_operand:SI 1 "s_register_operand" "=r") > (unspec:SI [(match_dup 2) ^ permalink raw reply [flat|nested] 9+ messages in thread
* [PATCH 12/13] arm: Convert more load/store MVE builtins to predicate qualifiers 2021-09-07 9:20 [PATCH 10/13] arm: Convert remaining MVE vcmp builtins to predicate qualifiers Christophe Lyon 2021-09-07 9:20 ` [PATCH 11/13] arm: Convert more MVE " Christophe Lyon @ 2021-09-07 9:20 ` Christophe Lyon 2021-10-11 14:19 ` Richard Sandiford 2021-09-07 9:21 ` [PATCH 13/13] arm: Convert more MVE/CDE " Christophe Lyon 2021-10-11 14:10 ` [PATCH 10/13] arm: Convert remaining MVE vcmp " Richard Sandiford 3 siblings, 1 reply; 9+ messages in thread From: Christophe Lyon @ 2021-09-07 9:20 UTC (permalink / raw) To: gcc-patches This patch covers a few builtins where we do not use the <mode> iterator and thus we cannot use <MVE_vpred>. However this introduces a problem for the v2di instructions, because there is not predicate for this case. For instance, changing STRSBS_P_QUALIFIERS breaks mve_vstrdq_scatter_base_p_<supf>v2di. Similarly, this patch introduces problems with: mve_vldrdq_gather_base_z_<supf>v2di mve_vldrdq_gather_base_wb_z_<supf>v2di mve_vldrdq_gather_base_nowb_z_<supf>v2di mve_vstrdq_scatter_base_wb_p_<supf>v2di 2021-09-02 Christophe Lyon <christophe.lyon@foss.st.com> gcc/ PR target/100757 PR target/101325 * config/arm/arm-builtins.c (STRSBS_P_QUALIFIERS): Use predicate qualifier. (STRSBU_P_QUALIFIERS): Likewise. (LDRGBS_Z_QUALIFIERS): Likewise. (LDRGBU_Z_QUALIFIERS): Likewise. (LDRGBWBXU_Z_QUALIFIERS): Likewise. (LDRGBWBS_Z_QUALIFIERS): Likewise. (LDRGBWBU_Z_QUALIFIERS): Likewise. (STRSBWBS_P_QUALIFIERS): Likewise. (STRSBWBU_P_QUALIFIERS): Likewise. * config/arm/mve.md: Use VxBI instead of HI. diff --git a/gcc/config/arm/arm-builtins.c b/gcc/config/arm/arm-builtins.c index 06ff9d2278a..e58580bb828 100644 --- a/gcc/config/arm/arm-builtins.c +++ b/gcc/config/arm/arm-builtins.c @@ -738,13 +738,13 @@ arm_strss_p_qualifiers[SIMD_MAX_BUILTIN_ARGS] static enum arm_type_qualifiers arm_strsbs_p_qualifiers[SIMD_MAX_BUILTIN_ARGS] = { qualifier_void, qualifier_unsigned, qualifier_immediate, - qualifier_none, qualifier_unsigned}; + qualifier_none, qualifier_predicate}; #define STRSBS_P_QUALIFIERS (arm_strsbs_p_qualifiers) static enum arm_type_qualifiers arm_strsbu_p_qualifiers[SIMD_MAX_BUILTIN_ARGS] = { qualifier_void, qualifier_unsigned, qualifier_immediate, - qualifier_unsigned, qualifier_unsigned}; + qualifier_unsigned, qualifier_predicate}; #define STRSBU_P_QUALIFIERS (arm_strsbu_p_qualifiers) static enum arm_type_qualifiers @@ -780,13 +780,13 @@ arm_ldrgbu_qualifiers[SIMD_MAX_BUILTIN_ARGS] static enum arm_type_qualifiers arm_ldrgbs_z_qualifiers[SIMD_MAX_BUILTIN_ARGS] = { qualifier_none, qualifier_unsigned, qualifier_immediate, - qualifier_unsigned}; + qualifier_predicate}; #define LDRGBS_Z_QUALIFIERS (arm_ldrgbs_z_qualifiers) static enum arm_type_qualifiers arm_ldrgbu_z_qualifiers[SIMD_MAX_BUILTIN_ARGS] = { qualifier_unsigned, qualifier_unsigned, qualifier_immediate, - qualifier_unsigned}; + qualifier_predicate}; #define LDRGBU_Z_QUALIFIERS (arm_ldrgbu_z_qualifiers) static enum arm_type_qualifiers @@ -826,7 +826,7 @@ arm_ldrgbwbxu_qualifiers[SIMD_MAX_BUILTIN_ARGS] static enum arm_type_qualifiers arm_ldrgbwbxu_z_qualifiers[SIMD_MAX_BUILTIN_ARGS] = { qualifier_unsigned, qualifier_unsigned, qualifier_immediate, - qualifier_unsigned}; + qualifier_predicate}; #define LDRGBWBXU_Z_QUALIFIERS (arm_ldrgbwbxu_z_qualifiers) static enum arm_type_qualifiers @@ -842,13 +842,13 @@ arm_ldrgbwbu_qualifiers[SIMD_MAX_BUILTIN_ARGS] static enum arm_type_qualifiers arm_ldrgbwbs_z_qualifiers[SIMD_MAX_BUILTIN_ARGS] = { qualifier_none, qualifier_unsigned, qualifier_immediate, - qualifier_unsigned}; + qualifier_predicate}; #define LDRGBWBS_Z_QUALIFIERS (arm_ldrgbwbs_z_qualifiers) static enum arm_type_qualifiers arm_ldrgbwbu_z_qualifiers[SIMD_MAX_BUILTIN_ARGS] = { qualifier_unsigned, qualifier_unsigned, qualifier_immediate, - qualifier_unsigned}; + qualifier_predicate}; #define LDRGBWBU_Z_QUALIFIERS (arm_ldrgbwbu_z_qualifiers) static enum arm_type_qualifiers @@ -864,13 +864,13 @@ arm_strsbwbu_qualifiers[SIMD_MAX_BUILTIN_ARGS] static enum arm_type_qualifiers arm_strsbwbs_p_qualifiers[SIMD_MAX_BUILTIN_ARGS] = { qualifier_unsigned, qualifier_unsigned, qualifier_const, - qualifier_none, qualifier_unsigned}; + qualifier_none, qualifier_predicate}; #define STRSBWBS_P_QUALIFIERS (arm_strsbwbs_p_qualifiers) static enum arm_type_qualifiers arm_strsbwbu_p_qualifiers[SIMD_MAX_BUILTIN_ARGS] = { qualifier_unsigned, qualifier_unsigned, qualifier_const, - qualifier_unsigned, qualifier_unsigned}; + qualifier_unsigned, qualifier_predicate}; #define STRSBWBU_P_QUALIFIERS (arm_strsbwbu_p_qualifiers) static enum arm_type_qualifiers diff --git a/gcc/config/arm/mve.md b/gcc/config/arm/mve.md index 2f36d47c800..241195909da 100644 --- a/gcc/config/arm/mve.md +++ b/gcc/config/arm/mve.md @@ -7294,7 +7294,7 @@ (define_insn "mve_vstrwq_scatter_base_p_<supf>v4si" [(match_operand:V4SI 0 "s_register_operand" "w") (match_operand:SI 1 "immediate_operand" "i") (match_operand:V4SI 2 "s_register_operand" "w") - (match_operand:HI 3 "vpr_register_operand" "Up")] + (match_operand:V4BI 3 "vpr_register_operand" "Up")] VSTRWSBQ)) ] "TARGET_HAVE_MVE" @@ -7383,7 +7383,7 @@ (define_insn "mve_vldrwq_gather_base_z_<supf>v4si" [(set (match_operand:V4SI 0 "s_register_operand" "=&w") (unspec:V4SI [(match_operand:V4SI 1 "s_register_operand" "w") (match_operand:SI 2 "immediate_operand" "i") - (match_operand:HI 3 "vpr_register_operand" "Up")] + (match_operand:V4BI 3 "vpr_register_operand" "Up")] VLDRWGBQ)) ] "TARGET_HAVE_MVE" @@ -7621,7 +7621,7 @@ (define_insn "mve_vldrwq_<supf>v4si" (define_insn "mve_vldrwq_z_fv4sf" [(set (match_operand:V4SF 0 "s_register_operand" "=w") (unspec:V4SF [(match_operand:V4SI 1 "memory_operand" "Ux") - (match_operand:HI 2 "vpr_register_operand" "Up")] + (match_operand:V4BI 2 "vpr_register_operand" "Up")] VLDRWQ_F)) ] "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" @@ -7641,7 +7641,7 @@ (define_insn "mve_vldrwq_z_fv4sf" (define_insn "mve_vldrwq_z_<supf>v4si" [(set (match_operand:V4SI 0 "s_register_operand" "=w") (unspec:V4SI [(match_operand:V4SI 1 "memory_operand" "Ux") - (match_operand:HI 2 "vpr_register_operand" "Up")] + (match_operand:V4BI 2 "vpr_register_operand" "Up")] VLDRWQ)) ] "TARGET_HAVE_MVE" @@ -7825,7 +7825,7 @@ (define_insn "mve_vldrhq_gather_offset_z_fv8hf" [(set (match_operand:V8HF 0 "s_register_operand" "=&w") (unspec:V8HF [(match_operand:V8HI 1 "memory_operand" "Us") (match_operand:V8HI 2 "s_register_operand" "w") - (match_operand:HI 3 "vpr_register_operand" "Up")] + (match_operand:V8BI 3 "vpr_register_operand" "Up")] VLDRHQGO_F)) ] "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" @@ -7867,7 +7867,7 @@ (define_insn "mve_vldrhq_gather_shifted_offset_z_fv8hf" [(set (match_operand:V8HF 0 "s_register_operand" "=&w") (unspec:V8HF [(match_operand:V8HI 1 "memory_operand" "Us") (match_operand:V8HI 2 "s_register_operand" "w") - (match_operand:HI 3 "vpr_register_operand" "Up")] + (match_operand:V8BI 3 "vpr_register_operand" "Up")] VLDRHQGSO_F)) ] "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" @@ -7909,7 +7909,7 @@ (define_insn "mve_vldrwq_gather_base_z_fv4sf" [(set (match_operand:V4SF 0 "s_register_operand" "=&w") (unspec:V4SF [(match_operand:V4SI 1 "s_register_operand" "w") (match_operand:SI 2 "immediate_operand" "i") - (match_operand:HI 3 "vpr_register_operand" "Up")] + (match_operand:V4BI 3 "vpr_register_operand" "Up")] VLDRWQGB_F)) ] "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" @@ -7970,7 +7970,7 @@ (define_insn "mve_vldrwq_gather_offset_z_fv4sf" [(set (match_operand:V4SF 0 "s_register_operand" "=&w") (unspec:V4SF [(match_operand:V4SI 1 "memory_operand" "Us") (match_operand:V4SI 2 "s_register_operand" "w") - (match_operand:HI 3 "vpr_register_operand" "Up")] + (match_operand:V4BI 3 "vpr_register_operand" "Up")] VLDRWQGO_F)) ] "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" @@ -7992,7 +7992,7 @@ (define_insn "mve_vldrwq_gather_offset_z_<supf>v4si" [(set (match_operand:V4SI 0 "s_register_operand" "=&w") (unspec:V4SI [(match_operand:V4SI 1 "memory_operand" "Us") (match_operand:V4SI 2 "s_register_operand" "w") - (match_operand:HI 3 "vpr_register_operand" "Up")] + (match_operand:V4BI 3 "vpr_register_operand" "Up")] VLDRWGOQ)) ] "TARGET_HAVE_MVE" @@ -8054,7 +8054,7 @@ (define_insn "mve_vldrwq_gather_shifted_offset_z_fv4sf" [(set (match_operand:V4SF 0 "s_register_operand" "=&w") (unspec:V4SF [(match_operand:V4SI 1 "memory_operand" "Us") (match_operand:V4SI 2 "s_register_operand" "w") - (match_operand:HI 3 "vpr_register_operand" "Up")] + (match_operand:V4BI 3 "vpr_register_operand" "Up")] VLDRWQGSO_F)) ] "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" @@ -8076,7 +8076,7 @@ (define_insn "mve_vldrwq_gather_shifted_offset_z_<supf>v4si" [(set (match_operand:V4SI 0 "s_register_operand" "=&w") (unspec:V4SI [(match_operand:V4SI 1 "memory_operand" "Us") (match_operand:V4SI 2 "s_register_operand" "w") - (match_operand:HI 3 "vpr_register_operand" "Up")] + (match_operand:V4BI 3 "vpr_register_operand" "Up")] VLDRWGSOQ)) ] "TARGET_HAVE_MVE" @@ -8116,7 +8116,7 @@ (define_insn "mve_vstrhq_fv8hf" (define_insn "mve_vstrhq_p_fv8hf" [(set (match_operand:V8HI 0 "mve_memory_operand" "=Ux") (unspec:V8HI [(match_operand:V8HF 1 "s_register_operand" "w") - (match_operand:HI 2 "vpr_register_operand" "Up")] + (match_operand:V8BI 2 "vpr_register_operand" "Up")] VSTRHQ_F)) ] "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" @@ -8335,7 +8335,7 @@ (define_insn "mve_vstrwq_p_fv4sf" (define_insn "mve_vstrwq_p_<supf>v4si" [(set (match_operand:V4SI 0 "memory_operand" "=Ux") (unspec:V4SI [(match_operand:V4SI 1 "s_register_operand" "w") - (match_operand:HI 2 "vpr_register_operand" "Up")] + (match_operand:V4BI 2 "vpr_register_operand" "Up")] VSTRWQ)) ] "TARGET_HAVE_MVE" @@ -8588,7 +8588,7 @@ (define_expand "mve_vstrhq_scatter_offset_p_fv8hf" [(match_operand:V8HI 0 "mve_scatter_memory") (match_operand:V8HI 1 "s_register_operand") (match_operand:V8HF 2 "s_register_operand") - (match_operand:HI 3 "vpr_register_operand") + (match_operand:V8BI 3 "vpr_register_operand") (unspec:V4SI [(const_int 0)] VSTRHQSO_F)] "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" { @@ -8606,7 +8606,7 @@ (define_insn "mve_vstrhq_scatter_offset_p_fv8hf_insn" [(match_operand:SI 0 "register_operand" "r") (match_operand:V8HI 1 "s_register_operand" "w") (match_operand:V8HF 2 "s_register_operand" "w") - (match_operand:HI 3 "vpr_register_operand" "Up")] + (match_operand:V8BI 3 "vpr_register_operand" "Up")] VSTRHQSO_F))] "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" "vpst\;vstrht.16\t%q2, [%0, %q1]" @@ -8647,7 +8647,7 @@ (define_expand "mve_vstrhq_scatter_shifted_offset_p_fv8hf" [(match_operand:V8HI 0 "memory_operand" "=Us") (match_operand:V8HI 1 "s_register_operand" "w") (match_operand:V8HF 2 "s_register_operand" "w") - (match_operand:HI 3 "vpr_register_operand" "Up") + (match_operand:V8BI 3 "vpr_register_operand" "Up") (unspec:V4SI [(const_int 0)] VSTRHQSSO_F)] "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" { @@ -8666,7 +8666,7 @@ (define_insn "mve_vstrhq_scatter_shifted_offset_p_fv8hf_insn" [(match_operand:SI 0 "register_operand" "r") (match_operand:V8HI 1 "s_register_operand" "w") (match_operand:V8HF 2 "s_register_operand" "w") - (match_operand:HI 3 "vpr_register_operand" "Up")] + (match_operand:V8BI 3 "vpr_register_operand" "Up")] VSTRHQSSO_F))] "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" "vpst\;vstrht.16\t%q2, [%0, %q1, uxtw #1]" @@ -8703,7 +8703,7 @@ (define_insn "mve_vstrwq_scatter_base_p_fv4sf" [(match_operand:V4SI 0 "s_register_operand" "w") (match_operand:SI 1 "immediate_operand" "i") (match_operand:V4SF 2 "s_register_operand" "w") - (match_operand:HI 3 "vpr_register_operand" "Up")] + (match_operand:V4BI 3 "vpr_register_operand" "Up")] VSTRWQSB_F)) ] "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" @@ -8752,7 +8752,7 @@ (define_expand "mve_vstrwq_scatter_offset_p_fv4sf" [(match_operand:V4SI 0 "mve_scatter_memory") (match_operand:V4SI 1 "s_register_operand") (match_operand:V4SF 2 "s_register_operand") - (match_operand:HI 3 "vpr_register_operand") + (match_operand:V4BI 3 "vpr_register_operand") (unspec:V4SI [(const_int 0)] VSTRWQSO_F)] "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" { @@ -8770,7 +8770,7 @@ (define_insn "mve_vstrwq_scatter_offset_p_fv4sf_insn" [(match_operand:SI 0 "register_operand" "r") (match_operand:V4SI 1 "s_register_operand" "w") (match_operand:V4SF 2 "s_register_operand" "w") - (match_operand:HI 3 "vpr_register_operand" "Up")] + (match_operand:V4BI 3 "vpr_register_operand" "Up")] VSTRWQSO_F))] "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" "vpst\;vstrwt.32\t%q2, [%0, %q1]" @@ -8783,7 +8783,7 @@ (define_expand "mve_vstrwq_scatter_offset_p_<supf>v4si" [(match_operand:V4SI 0 "mve_scatter_memory") (match_operand:V4SI 1 "s_register_operand") (match_operand:V4SI 2 "s_register_operand") - (match_operand:HI 3 "vpr_register_operand") + (match_operand:V4BI 3 "vpr_register_operand") (unspec:V4SI [(const_int 0)] VSTRWSOQ)] "TARGET_HAVE_MVE" { @@ -8801,7 +8801,7 @@ (define_insn "mve_vstrwq_scatter_offset_p_<supf>v4si_insn" [(match_operand:SI 0 "register_operand" "r") (match_operand:V4SI 1 "s_register_operand" "w") (match_operand:V4SI 2 "s_register_operand" "w") - (match_operand:HI 3 "vpr_register_operand" "Up")] + (match_operand:V4BI 3 "vpr_register_operand" "Up")] VSTRWSOQ))] "TARGET_HAVE_MVE" "vpst\;vstrwt.32\t%q2, [%0, %q1]" @@ -8870,7 +8870,7 @@ (define_expand "mve_vstrwq_scatter_shifted_offset_p_fv4sf" [(match_operand:V4SI 0 "mve_scatter_memory") (match_operand:V4SI 1 "s_register_operand") (match_operand:V4SF 2 "s_register_operand") - (match_operand:HI 3 "vpr_register_operand") + (match_operand:V4BI 3 "vpr_register_operand") (unspec:V4SI [(const_int 0)] VSTRWQSSO_F)] "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" { @@ -8889,7 +8889,7 @@ (define_insn "mve_vstrwq_scatter_shifted_offset_p_fv4sf_insn" [(match_operand:SI 0 "register_operand" "r") (match_operand:V4SI 1 "s_register_operand" "w") (match_operand:V4SF 2 "s_register_operand" "w") - (match_operand:HI 3 "vpr_register_operand" "Up")] + (match_operand:V4BI 3 "vpr_register_operand" "Up")] VSTRWQSSO_F))] "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" "vpst\;vstrwt.32\t%q2, [%0, %q1, uxtw #2]" @@ -8902,7 +8902,7 @@ (define_expand "mve_vstrwq_scatter_shifted_offset_p_<supf>v4si" [(match_operand:V4SI 0 "mve_scatter_memory") (match_operand:V4SI 1 "s_register_operand") (match_operand:V4SI 2 "s_register_operand") - (match_operand:HI 3 "vpr_register_operand") + (match_operand:V4BI 3 "vpr_register_operand") (unspec:V4SI [(const_int 0)] VSTRWSSOQ)] "TARGET_HAVE_MVE" { @@ -8921,7 +8921,7 @@ (define_insn "mve_vstrwq_scatter_shifted_offset_p_<supf>v4si_insn" [(match_operand:SI 0 "register_operand" "r") (match_operand:V4SI 1 "s_register_operand" "w") (match_operand:V4SI 2 "s_register_operand" "w") - (match_operand:HI 3 "vpr_register_operand" "Up")] + (match_operand:V4BI 3 "vpr_register_operand" "Up")] VSTRWSSOQ))] "TARGET_HAVE_MVE" "vpst\;vstrwt.32\t%q2, [%0, %q1, uxtw #2]" @@ -9388,7 +9388,7 @@ (define_insn "mve_vstrwq_scatter_base_wb_p_<supf>v4si" [(match_operand:V4SI 1 "s_register_operand" "0") (match_operand:SI 2 "mve_vldrd_immediate" "Ri") (match_operand:V4SI 3 "s_register_operand" "w") - (match_operand:HI 4 "vpr_register_operand")] + (match_operand:V4BI 4 "vpr_register_operand")] VSTRWSBWBQ)) (set (match_operand:V4SI 0 "s_register_operand" "=w") (unspec:V4SI [(match_dup 1) (match_dup 2)] @@ -9439,7 +9439,7 @@ (define_insn "mve_vstrwq_scatter_base_wb_p_fv4sf" [(match_operand:V4SI 1 "s_register_operand" "0") (match_operand:SI 2 "mve_vldrd_immediate" "Ri") (match_operand:V4SF 3 "s_register_operand" "w") - (match_operand:HI 4 "vpr_register_operand")] + (match_operand:V4BI 4 "vpr_register_operand")] VSTRWQSBWB_F)) (set (match_operand:V4SI 0 "s_register_operand" "=w") (unspec:V4SI [(match_dup 1) (match_dup 2)] @@ -9563,7 +9563,7 @@ (define_expand "mve_vldrwq_gather_base_wb_z_<supf>v4si" [(match_operand:V4SI 0 "s_register_operand") (match_operand:V4SI 1 "s_register_operand") (match_operand:SI 2 "mve_vldrd_immediate") - (match_operand:HI 3 "vpr_register_operand") + (match_operand:V4BI 3 "vpr_register_operand") (unspec:V4SI [(const_int 0)] VLDRWGBWBQ)] "TARGET_HAVE_MVE" { @@ -9578,7 +9578,7 @@ (define_expand "mve_vldrwq_gather_base_nowb_z_<supf>v4si" [(match_operand:V4SI 0 "s_register_operand") (match_operand:V4SI 1 "s_register_operand") (match_operand:SI 2 "mve_vldrd_immediate") - (match_operand:HI 3 "vpr_register_operand") + (match_operand:V4BI 3 "vpr_register_operand") (unspec:V4SI [(const_int 0)] VLDRWGBWBQ)] "TARGET_HAVE_MVE" { @@ -9597,7 +9597,7 @@ (define_insn "mve_vldrwq_gather_base_wb_z_<supf>v4si_insn" [(set (match_operand:V4SI 0 "s_register_operand" "=&w") (unspec:V4SI [(match_operand:V4SI 2 "s_register_operand" "1") (match_operand:SI 3 "mve_vldrd_immediate" "Ri") - (match_operand:HI 4 "vpr_register_operand" "Up") + (match_operand:V4BI 4 "vpr_register_operand" "Up") (mem:BLK (scratch))] VLDRWGBWBQ)) (set (match_operand:V4SI 1 "s_register_operand" "=&w") @@ -9671,7 +9671,7 @@ (define_expand "mve_vldrwq_gather_base_wb_z_fv4sf" [(match_operand:V4SI 0 "s_register_operand") (match_operand:V4SI 1 "s_register_operand") (match_operand:SI 2 "mve_vldrd_immediate") - (match_operand:HI 3 "vpr_register_operand") + (match_operand:V4BI 3 "vpr_register_operand") (unspec:V4SI [(const_int 0)] VLDRWQGBWB_F)] "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" { @@ -9687,7 +9687,7 @@ (define_expand "mve_vldrwq_gather_base_nowb_z_fv4sf" [(match_operand:V4SF 0 "s_register_operand") (match_operand:V4SI 1 "s_register_operand") (match_operand:SI 2 "mve_vldrd_immediate") - (match_operand:HI 3 "vpr_register_operand") + (match_operand:V4BI 3 "vpr_register_operand") (unspec:V4SI [(const_int 0)] VLDRWQGBWB_F)] "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" { @@ -9706,7 +9706,7 @@ (define_insn "mve_vldrwq_gather_base_wb_z_fv4sf_insn" [(set (match_operand:V4SF 0 "s_register_operand" "=&w") (unspec:V4SF [(match_operand:V4SI 2 "s_register_operand" "1") (match_operand:SI 3 "mve_vldrd_immediate" "Ri") - (match_operand:HI 4 "vpr_register_operand" "Up") + (match_operand:V4BI 4 "vpr_register_operand" "Up") (mem:BLK (scratch))] VLDRWQGBWB_F)) (set (match_operand:V4SI 1 "s_register_operand" "=&w") -- 2.25.1 ^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH 12/13] arm: Convert more load/store MVE builtins to predicate qualifiers 2021-09-07 9:20 ` [PATCH 12/13] arm: Convert more load/store " Christophe Lyon @ 2021-10-11 14:19 ` Richard Sandiford 2021-10-11 15:03 ` Richard Sandiford 0 siblings, 1 reply; 9+ messages in thread From: Richard Sandiford @ 2021-10-11 14:19 UTC (permalink / raw) To: Christophe Lyon via Gcc-patches Christophe Lyon via Gcc-patches <gcc-patches@gcc.gnu.org> writes: > This patch covers a few builtins where we do not use the <mode> > iterator and thus we cannot use <MVE_vpred>. > > However this introduces a problem for the v2di instructions, because > there is not predicate for this case. For instance, changing > STRSBS_P_QUALIFIERS breaks mve_vstrdq_scatter_base_p_<supf>v2di. > Similarly, this patch introduces problems with: > mve_vldrdq_gather_base_z_<supf>v2di > mve_vldrdq_gather_base_wb_z_<supf>v2di > mve_vldrdq_gather_base_nowb_z_<supf>v2di > mve_vstrdq_scatter_base_wb_p_<supf>v2di I think we should treat HImode as the predicate mode for V2DI, alongside the others, even though it isn't a vector boolean mode. Like you say, it'll end up being too much of a special case otherwise. Thanks, Richard > 2021-09-02 Christophe Lyon <christophe.lyon@foss.st.com> > > gcc/ > PR target/100757 > PR target/101325 > * config/arm/arm-builtins.c (STRSBS_P_QUALIFIERS): Use predicate > qualifier. > (STRSBU_P_QUALIFIERS): Likewise. > (LDRGBS_Z_QUALIFIERS): Likewise. > (LDRGBU_Z_QUALIFIERS): Likewise. > (LDRGBWBXU_Z_QUALIFIERS): Likewise. > (LDRGBWBS_Z_QUALIFIERS): Likewise. > (LDRGBWBU_Z_QUALIFIERS): Likewise. > (STRSBWBS_P_QUALIFIERS): Likewise. > (STRSBWBU_P_QUALIFIERS): Likewise. > * config/arm/mve.md: Use VxBI instead of HI. > > diff --git a/gcc/config/arm/arm-builtins.c b/gcc/config/arm/arm-builtins.c > index 06ff9d2278a..e58580bb828 100644 > --- a/gcc/config/arm/arm-builtins.c > +++ b/gcc/config/arm/arm-builtins.c > @@ -738,13 +738,13 @@ arm_strss_p_qualifiers[SIMD_MAX_BUILTIN_ARGS] > static enum arm_type_qualifiers > arm_strsbs_p_qualifiers[SIMD_MAX_BUILTIN_ARGS] > = { qualifier_void, qualifier_unsigned, qualifier_immediate, > - qualifier_none, qualifier_unsigned}; > + qualifier_none, qualifier_predicate}; > #define STRSBS_P_QUALIFIERS (arm_strsbs_p_qualifiers) > > static enum arm_type_qualifiers > arm_strsbu_p_qualifiers[SIMD_MAX_BUILTIN_ARGS] > = { qualifier_void, qualifier_unsigned, qualifier_immediate, > - qualifier_unsigned, qualifier_unsigned}; > + qualifier_unsigned, qualifier_predicate}; > #define STRSBU_P_QUALIFIERS (arm_strsbu_p_qualifiers) > > static enum arm_type_qualifiers > @@ -780,13 +780,13 @@ arm_ldrgbu_qualifiers[SIMD_MAX_BUILTIN_ARGS] > static enum arm_type_qualifiers > arm_ldrgbs_z_qualifiers[SIMD_MAX_BUILTIN_ARGS] > = { qualifier_none, qualifier_unsigned, qualifier_immediate, > - qualifier_unsigned}; > + qualifier_predicate}; > #define LDRGBS_Z_QUALIFIERS (arm_ldrgbs_z_qualifiers) > > static enum arm_type_qualifiers > arm_ldrgbu_z_qualifiers[SIMD_MAX_BUILTIN_ARGS] > = { qualifier_unsigned, qualifier_unsigned, qualifier_immediate, > - qualifier_unsigned}; > + qualifier_predicate}; > #define LDRGBU_Z_QUALIFIERS (arm_ldrgbu_z_qualifiers) > > static enum arm_type_qualifiers > @@ -826,7 +826,7 @@ arm_ldrgbwbxu_qualifiers[SIMD_MAX_BUILTIN_ARGS] > static enum arm_type_qualifiers > arm_ldrgbwbxu_z_qualifiers[SIMD_MAX_BUILTIN_ARGS] > = { qualifier_unsigned, qualifier_unsigned, qualifier_immediate, > - qualifier_unsigned}; > + qualifier_predicate}; > #define LDRGBWBXU_Z_QUALIFIERS (arm_ldrgbwbxu_z_qualifiers) > > static enum arm_type_qualifiers > @@ -842,13 +842,13 @@ arm_ldrgbwbu_qualifiers[SIMD_MAX_BUILTIN_ARGS] > static enum arm_type_qualifiers > arm_ldrgbwbs_z_qualifiers[SIMD_MAX_BUILTIN_ARGS] > = { qualifier_none, qualifier_unsigned, qualifier_immediate, > - qualifier_unsigned}; > + qualifier_predicate}; > #define LDRGBWBS_Z_QUALIFIERS (arm_ldrgbwbs_z_qualifiers) > > static enum arm_type_qualifiers > arm_ldrgbwbu_z_qualifiers[SIMD_MAX_BUILTIN_ARGS] > = { qualifier_unsigned, qualifier_unsigned, qualifier_immediate, > - qualifier_unsigned}; > + qualifier_predicate}; > #define LDRGBWBU_Z_QUALIFIERS (arm_ldrgbwbu_z_qualifiers) > > static enum arm_type_qualifiers > @@ -864,13 +864,13 @@ arm_strsbwbu_qualifiers[SIMD_MAX_BUILTIN_ARGS] > static enum arm_type_qualifiers > arm_strsbwbs_p_qualifiers[SIMD_MAX_BUILTIN_ARGS] > = { qualifier_unsigned, qualifier_unsigned, qualifier_const, > - qualifier_none, qualifier_unsigned}; > + qualifier_none, qualifier_predicate}; > #define STRSBWBS_P_QUALIFIERS (arm_strsbwbs_p_qualifiers) > > static enum arm_type_qualifiers > arm_strsbwbu_p_qualifiers[SIMD_MAX_BUILTIN_ARGS] > = { qualifier_unsigned, qualifier_unsigned, qualifier_const, > - qualifier_unsigned, qualifier_unsigned}; > + qualifier_unsigned, qualifier_predicate}; > #define STRSBWBU_P_QUALIFIERS (arm_strsbwbu_p_qualifiers) > > static enum arm_type_qualifiers > diff --git a/gcc/config/arm/mve.md b/gcc/config/arm/mve.md > index 2f36d47c800..241195909da 100644 > --- a/gcc/config/arm/mve.md > +++ b/gcc/config/arm/mve.md > @@ -7294,7 +7294,7 @@ (define_insn "mve_vstrwq_scatter_base_p_<supf>v4si" > [(match_operand:V4SI 0 "s_register_operand" "w") > (match_operand:SI 1 "immediate_operand" "i") > (match_operand:V4SI 2 "s_register_operand" "w") > - (match_operand:HI 3 "vpr_register_operand" "Up")] > + (match_operand:V4BI 3 "vpr_register_operand" "Up")] > VSTRWSBQ)) > ] > "TARGET_HAVE_MVE" > @@ -7383,7 +7383,7 @@ (define_insn "mve_vldrwq_gather_base_z_<supf>v4si" > [(set (match_operand:V4SI 0 "s_register_operand" "=&w") > (unspec:V4SI [(match_operand:V4SI 1 "s_register_operand" "w") > (match_operand:SI 2 "immediate_operand" "i") > - (match_operand:HI 3 "vpr_register_operand" "Up")] > + (match_operand:V4BI 3 "vpr_register_operand" "Up")] > VLDRWGBQ)) > ] > "TARGET_HAVE_MVE" > @@ -7621,7 +7621,7 @@ (define_insn "mve_vldrwq_<supf>v4si" > (define_insn "mve_vldrwq_z_fv4sf" > [(set (match_operand:V4SF 0 "s_register_operand" "=w") > (unspec:V4SF [(match_operand:V4SI 1 "memory_operand" "Ux") > - (match_operand:HI 2 "vpr_register_operand" "Up")] > + (match_operand:V4BI 2 "vpr_register_operand" "Up")] > VLDRWQ_F)) > ] > "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" > @@ -7641,7 +7641,7 @@ (define_insn "mve_vldrwq_z_fv4sf" > (define_insn "mve_vldrwq_z_<supf>v4si" > [(set (match_operand:V4SI 0 "s_register_operand" "=w") > (unspec:V4SI [(match_operand:V4SI 1 "memory_operand" "Ux") > - (match_operand:HI 2 "vpr_register_operand" "Up")] > + (match_operand:V4BI 2 "vpr_register_operand" "Up")] > VLDRWQ)) > ] > "TARGET_HAVE_MVE" > @@ -7825,7 +7825,7 @@ (define_insn "mve_vldrhq_gather_offset_z_fv8hf" > [(set (match_operand:V8HF 0 "s_register_operand" "=&w") > (unspec:V8HF [(match_operand:V8HI 1 "memory_operand" "Us") > (match_operand:V8HI 2 "s_register_operand" "w") > - (match_operand:HI 3 "vpr_register_operand" "Up")] > + (match_operand:V8BI 3 "vpr_register_operand" "Up")] > VLDRHQGO_F)) > ] > "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" > @@ -7867,7 +7867,7 @@ (define_insn "mve_vldrhq_gather_shifted_offset_z_fv8hf" > [(set (match_operand:V8HF 0 "s_register_operand" "=&w") > (unspec:V8HF [(match_operand:V8HI 1 "memory_operand" "Us") > (match_operand:V8HI 2 "s_register_operand" "w") > - (match_operand:HI 3 "vpr_register_operand" "Up")] > + (match_operand:V8BI 3 "vpr_register_operand" "Up")] > VLDRHQGSO_F)) > ] > "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" > @@ -7909,7 +7909,7 @@ (define_insn "mve_vldrwq_gather_base_z_fv4sf" > [(set (match_operand:V4SF 0 "s_register_operand" "=&w") > (unspec:V4SF [(match_operand:V4SI 1 "s_register_operand" "w") > (match_operand:SI 2 "immediate_operand" "i") > - (match_operand:HI 3 "vpr_register_operand" "Up")] > + (match_operand:V4BI 3 "vpr_register_operand" "Up")] > VLDRWQGB_F)) > ] > "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" > @@ -7970,7 +7970,7 @@ (define_insn "mve_vldrwq_gather_offset_z_fv4sf" > [(set (match_operand:V4SF 0 "s_register_operand" "=&w") > (unspec:V4SF [(match_operand:V4SI 1 "memory_operand" "Us") > (match_operand:V4SI 2 "s_register_operand" "w") > - (match_operand:HI 3 "vpr_register_operand" "Up")] > + (match_operand:V4BI 3 "vpr_register_operand" "Up")] > VLDRWQGO_F)) > ] > "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" > @@ -7992,7 +7992,7 @@ (define_insn "mve_vldrwq_gather_offset_z_<supf>v4si" > [(set (match_operand:V4SI 0 "s_register_operand" "=&w") > (unspec:V4SI [(match_operand:V4SI 1 "memory_operand" "Us") > (match_operand:V4SI 2 "s_register_operand" "w") > - (match_operand:HI 3 "vpr_register_operand" "Up")] > + (match_operand:V4BI 3 "vpr_register_operand" "Up")] > VLDRWGOQ)) > ] > "TARGET_HAVE_MVE" > @@ -8054,7 +8054,7 @@ (define_insn "mve_vldrwq_gather_shifted_offset_z_fv4sf" > [(set (match_operand:V4SF 0 "s_register_operand" "=&w") > (unspec:V4SF [(match_operand:V4SI 1 "memory_operand" "Us") > (match_operand:V4SI 2 "s_register_operand" "w") > - (match_operand:HI 3 "vpr_register_operand" "Up")] > + (match_operand:V4BI 3 "vpr_register_operand" "Up")] > VLDRWQGSO_F)) > ] > "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" > @@ -8076,7 +8076,7 @@ (define_insn "mve_vldrwq_gather_shifted_offset_z_<supf>v4si" > [(set (match_operand:V4SI 0 "s_register_operand" "=&w") > (unspec:V4SI [(match_operand:V4SI 1 "memory_operand" "Us") > (match_operand:V4SI 2 "s_register_operand" "w") > - (match_operand:HI 3 "vpr_register_operand" "Up")] > + (match_operand:V4BI 3 "vpr_register_operand" "Up")] > VLDRWGSOQ)) > ] > "TARGET_HAVE_MVE" > @@ -8116,7 +8116,7 @@ (define_insn "mve_vstrhq_fv8hf" > (define_insn "mve_vstrhq_p_fv8hf" > [(set (match_operand:V8HI 0 "mve_memory_operand" "=Ux") > (unspec:V8HI [(match_operand:V8HF 1 "s_register_operand" "w") > - (match_operand:HI 2 "vpr_register_operand" "Up")] > + (match_operand:V8BI 2 "vpr_register_operand" "Up")] > VSTRHQ_F)) > ] > "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" > @@ -8335,7 +8335,7 @@ (define_insn "mve_vstrwq_p_fv4sf" > (define_insn "mve_vstrwq_p_<supf>v4si" > [(set (match_operand:V4SI 0 "memory_operand" "=Ux") > (unspec:V4SI [(match_operand:V4SI 1 "s_register_operand" "w") > - (match_operand:HI 2 "vpr_register_operand" "Up")] > + (match_operand:V4BI 2 "vpr_register_operand" "Up")] > VSTRWQ)) > ] > "TARGET_HAVE_MVE" > @@ -8588,7 +8588,7 @@ (define_expand "mve_vstrhq_scatter_offset_p_fv8hf" > [(match_operand:V8HI 0 "mve_scatter_memory") > (match_operand:V8HI 1 "s_register_operand") > (match_operand:V8HF 2 "s_register_operand") > - (match_operand:HI 3 "vpr_register_operand") > + (match_operand:V8BI 3 "vpr_register_operand") > (unspec:V4SI [(const_int 0)] VSTRHQSO_F)] > "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" > { > @@ -8606,7 +8606,7 @@ (define_insn "mve_vstrhq_scatter_offset_p_fv8hf_insn" > [(match_operand:SI 0 "register_operand" "r") > (match_operand:V8HI 1 "s_register_operand" "w") > (match_operand:V8HF 2 "s_register_operand" "w") > - (match_operand:HI 3 "vpr_register_operand" "Up")] > + (match_operand:V8BI 3 "vpr_register_operand" "Up")] > VSTRHQSO_F))] > "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" > "vpst\;vstrht.16\t%q2, [%0, %q1]" > @@ -8647,7 +8647,7 @@ (define_expand "mve_vstrhq_scatter_shifted_offset_p_fv8hf" > [(match_operand:V8HI 0 "memory_operand" "=Us") > (match_operand:V8HI 1 "s_register_operand" "w") > (match_operand:V8HF 2 "s_register_operand" "w") > - (match_operand:HI 3 "vpr_register_operand" "Up") > + (match_operand:V8BI 3 "vpr_register_operand" "Up") > (unspec:V4SI [(const_int 0)] VSTRHQSSO_F)] > "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" > { > @@ -8666,7 +8666,7 @@ (define_insn "mve_vstrhq_scatter_shifted_offset_p_fv8hf_insn" > [(match_operand:SI 0 "register_operand" "r") > (match_operand:V8HI 1 "s_register_operand" "w") > (match_operand:V8HF 2 "s_register_operand" "w") > - (match_operand:HI 3 "vpr_register_operand" "Up")] > + (match_operand:V8BI 3 "vpr_register_operand" "Up")] > VSTRHQSSO_F))] > "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" > "vpst\;vstrht.16\t%q2, [%0, %q1, uxtw #1]" > @@ -8703,7 +8703,7 @@ (define_insn "mve_vstrwq_scatter_base_p_fv4sf" > [(match_operand:V4SI 0 "s_register_operand" "w") > (match_operand:SI 1 "immediate_operand" "i") > (match_operand:V4SF 2 "s_register_operand" "w") > - (match_operand:HI 3 "vpr_register_operand" "Up")] > + (match_operand:V4BI 3 "vpr_register_operand" "Up")] > VSTRWQSB_F)) > ] > "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" > @@ -8752,7 +8752,7 @@ (define_expand "mve_vstrwq_scatter_offset_p_fv4sf" > [(match_operand:V4SI 0 "mve_scatter_memory") > (match_operand:V4SI 1 "s_register_operand") > (match_operand:V4SF 2 "s_register_operand") > - (match_operand:HI 3 "vpr_register_operand") > + (match_operand:V4BI 3 "vpr_register_operand") > (unspec:V4SI [(const_int 0)] VSTRWQSO_F)] > "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" > { > @@ -8770,7 +8770,7 @@ (define_insn "mve_vstrwq_scatter_offset_p_fv4sf_insn" > [(match_operand:SI 0 "register_operand" "r") > (match_operand:V4SI 1 "s_register_operand" "w") > (match_operand:V4SF 2 "s_register_operand" "w") > - (match_operand:HI 3 "vpr_register_operand" "Up")] > + (match_operand:V4BI 3 "vpr_register_operand" "Up")] > VSTRWQSO_F))] > "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" > "vpst\;vstrwt.32\t%q2, [%0, %q1]" > @@ -8783,7 +8783,7 @@ (define_expand "mve_vstrwq_scatter_offset_p_<supf>v4si" > [(match_operand:V4SI 0 "mve_scatter_memory") > (match_operand:V4SI 1 "s_register_operand") > (match_operand:V4SI 2 "s_register_operand") > - (match_operand:HI 3 "vpr_register_operand") > + (match_operand:V4BI 3 "vpr_register_operand") > (unspec:V4SI [(const_int 0)] VSTRWSOQ)] > "TARGET_HAVE_MVE" > { > @@ -8801,7 +8801,7 @@ (define_insn "mve_vstrwq_scatter_offset_p_<supf>v4si_insn" > [(match_operand:SI 0 "register_operand" "r") > (match_operand:V4SI 1 "s_register_operand" "w") > (match_operand:V4SI 2 "s_register_operand" "w") > - (match_operand:HI 3 "vpr_register_operand" "Up")] > + (match_operand:V4BI 3 "vpr_register_operand" "Up")] > VSTRWSOQ))] > "TARGET_HAVE_MVE" > "vpst\;vstrwt.32\t%q2, [%0, %q1]" > @@ -8870,7 +8870,7 @@ (define_expand "mve_vstrwq_scatter_shifted_offset_p_fv4sf" > [(match_operand:V4SI 0 "mve_scatter_memory") > (match_operand:V4SI 1 "s_register_operand") > (match_operand:V4SF 2 "s_register_operand") > - (match_operand:HI 3 "vpr_register_operand") > + (match_operand:V4BI 3 "vpr_register_operand") > (unspec:V4SI [(const_int 0)] VSTRWQSSO_F)] > "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" > { > @@ -8889,7 +8889,7 @@ (define_insn "mve_vstrwq_scatter_shifted_offset_p_fv4sf_insn" > [(match_operand:SI 0 "register_operand" "r") > (match_operand:V4SI 1 "s_register_operand" "w") > (match_operand:V4SF 2 "s_register_operand" "w") > - (match_operand:HI 3 "vpr_register_operand" "Up")] > + (match_operand:V4BI 3 "vpr_register_operand" "Up")] > VSTRWQSSO_F))] > "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" > "vpst\;vstrwt.32\t%q2, [%0, %q1, uxtw #2]" > @@ -8902,7 +8902,7 @@ (define_expand "mve_vstrwq_scatter_shifted_offset_p_<supf>v4si" > [(match_operand:V4SI 0 "mve_scatter_memory") > (match_operand:V4SI 1 "s_register_operand") > (match_operand:V4SI 2 "s_register_operand") > - (match_operand:HI 3 "vpr_register_operand") > + (match_operand:V4BI 3 "vpr_register_operand") > (unspec:V4SI [(const_int 0)] VSTRWSSOQ)] > "TARGET_HAVE_MVE" > { > @@ -8921,7 +8921,7 @@ (define_insn "mve_vstrwq_scatter_shifted_offset_p_<supf>v4si_insn" > [(match_operand:SI 0 "register_operand" "r") > (match_operand:V4SI 1 "s_register_operand" "w") > (match_operand:V4SI 2 "s_register_operand" "w") > - (match_operand:HI 3 "vpr_register_operand" "Up")] > + (match_operand:V4BI 3 "vpr_register_operand" "Up")] > VSTRWSSOQ))] > "TARGET_HAVE_MVE" > "vpst\;vstrwt.32\t%q2, [%0, %q1, uxtw #2]" > @@ -9388,7 +9388,7 @@ (define_insn "mve_vstrwq_scatter_base_wb_p_<supf>v4si" > [(match_operand:V4SI 1 "s_register_operand" "0") > (match_operand:SI 2 "mve_vldrd_immediate" "Ri") > (match_operand:V4SI 3 "s_register_operand" "w") > - (match_operand:HI 4 "vpr_register_operand")] > + (match_operand:V4BI 4 "vpr_register_operand")] > VSTRWSBWBQ)) > (set (match_operand:V4SI 0 "s_register_operand" "=w") > (unspec:V4SI [(match_dup 1) (match_dup 2)] > @@ -9439,7 +9439,7 @@ (define_insn "mve_vstrwq_scatter_base_wb_p_fv4sf" > [(match_operand:V4SI 1 "s_register_operand" "0") > (match_operand:SI 2 "mve_vldrd_immediate" "Ri") > (match_operand:V4SF 3 "s_register_operand" "w") > - (match_operand:HI 4 "vpr_register_operand")] > + (match_operand:V4BI 4 "vpr_register_operand")] > VSTRWQSBWB_F)) > (set (match_operand:V4SI 0 "s_register_operand" "=w") > (unspec:V4SI [(match_dup 1) (match_dup 2)] > @@ -9563,7 +9563,7 @@ (define_expand "mve_vldrwq_gather_base_wb_z_<supf>v4si" > [(match_operand:V4SI 0 "s_register_operand") > (match_operand:V4SI 1 "s_register_operand") > (match_operand:SI 2 "mve_vldrd_immediate") > - (match_operand:HI 3 "vpr_register_operand") > + (match_operand:V4BI 3 "vpr_register_operand") > (unspec:V4SI [(const_int 0)] VLDRWGBWBQ)] > "TARGET_HAVE_MVE" > { > @@ -9578,7 +9578,7 @@ (define_expand "mve_vldrwq_gather_base_nowb_z_<supf>v4si" > [(match_operand:V4SI 0 "s_register_operand") > (match_operand:V4SI 1 "s_register_operand") > (match_operand:SI 2 "mve_vldrd_immediate") > - (match_operand:HI 3 "vpr_register_operand") > + (match_operand:V4BI 3 "vpr_register_operand") > (unspec:V4SI [(const_int 0)] VLDRWGBWBQ)] > "TARGET_HAVE_MVE" > { > @@ -9597,7 +9597,7 @@ (define_insn "mve_vldrwq_gather_base_wb_z_<supf>v4si_insn" > [(set (match_operand:V4SI 0 "s_register_operand" "=&w") > (unspec:V4SI [(match_operand:V4SI 2 "s_register_operand" "1") > (match_operand:SI 3 "mve_vldrd_immediate" "Ri") > - (match_operand:HI 4 "vpr_register_operand" "Up") > + (match_operand:V4BI 4 "vpr_register_operand" "Up") > (mem:BLK (scratch))] > VLDRWGBWBQ)) > (set (match_operand:V4SI 1 "s_register_operand" "=&w") > @@ -9671,7 +9671,7 @@ (define_expand "mve_vldrwq_gather_base_wb_z_fv4sf" > [(match_operand:V4SI 0 "s_register_operand") > (match_operand:V4SI 1 "s_register_operand") > (match_operand:SI 2 "mve_vldrd_immediate") > - (match_operand:HI 3 "vpr_register_operand") > + (match_operand:V4BI 3 "vpr_register_operand") > (unspec:V4SI [(const_int 0)] VLDRWQGBWB_F)] > "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" > { > @@ -9687,7 +9687,7 @@ (define_expand "mve_vldrwq_gather_base_nowb_z_fv4sf" > [(match_operand:V4SF 0 "s_register_operand") > (match_operand:V4SI 1 "s_register_operand") > (match_operand:SI 2 "mve_vldrd_immediate") > - (match_operand:HI 3 "vpr_register_operand") > + (match_operand:V4BI 3 "vpr_register_operand") > (unspec:V4SI [(const_int 0)] VLDRWQGBWB_F)] > "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" > { > @@ -9706,7 +9706,7 @@ (define_insn "mve_vldrwq_gather_base_wb_z_fv4sf_insn" > [(set (match_operand:V4SF 0 "s_register_operand" "=&w") > (unspec:V4SF [(match_operand:V4SI 2 "s_register_operand" "1") > (match_operand:SI 3 "mve_vldrd_immediate" "Ri") > - (match_operand:HI 4 "vpr_register_operand" "Up") > + (match_operand:V4BI 4 "vpr_register_operand" "Up") > (mem:BLK (scratch))] > VLDRWQGBWB_F)) > (set (match_operand:V4SI 1 "s_register_operand" "=&w") ^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH 12/13] arm: Convert more load/store MVE builtins to predicate qualifiers 2021-10-11 14:19 ` Richard Sandiford @ 2021-10-11 15:03 ` Richard Sandiford 0 siblings, 0 replies; 9+ messages in thread From: Richard Sandiford @ 2021-10-11 15:03 UTC (permalink / raw) To: Christophe Lyon via Gcc-patches Richard Sandiford via Gcc-patches <gcc-patches@gcc.gnu.org> writes: > Christophe Lyon via Gcc-patches <gcc-patches@gcc.gnu.org> writes: >> This patch covers a few builtins where we do not use the <mode> >> iterator and thus we cannot use <MVE_vpred>. >> >> However this introduces a problem for the v2di instructions, because >> there is not predicate for this case. For instance, changing >> STRSBS_P_QUALIFIERS breaks mve_vstrdq_scatter_base_p_<supf>v2di. >> Similarly, this patch introduces problems with: >> mve_vldrdq_gather_base_z_<supf>v2di >> mve_vldrdq_gather_base_wb_z_<supf>v2di >> mve_vldrdq_gather_base_nowb_z_<supf>v2di >> mve_vstrdq_scatter_base_wb_p_<supf>v2di > > I think we should treat HImode as the predicate mode for V2DI, > alongside the others, even though it isn't a vector boolean mode. > Like you say, it'll end up being too much of a special case otherwise. Actually: couldn't we have a V8BI too? Sorry, I was getting confused with something else and thought that that wouldn't be possible for some reason. V8BI might not be used as much as the other boolean modes, but it still seems like conceptually the right thing to do. Thanks, Richard > > Thanks, > Richard > >> 2021-09-02 Christophe Lyon <christophe.lyon@foss.st.com> >> >> gcc/ >> PR target/100757 >> PR target/101325 >> * config/arm/arm-builtins.c (STRSBS_P_QUALIFIERS): Use predicate >> qualifier. >> (STRSBU_P_QUALIFIERS): Likewise. >> (LDRGBS_Z_QUALIFIERS): Likewise. >> (LDRGBU_Z_QUALIFIERS): Likewise. >> (LDRGBWBXU_Z_QUALIFIERS): Likewise. >> (LDRGBWBS_Z_QUALIFIERS): Likewise. >> (LDRGBWBU_Z_QUALIFIERS): Likewise. >> (STRSBWBS_P_QUALIFIERS): Likewise. >> (STRSBWBU_P_QUALIFIERS): Likewise. >> * config/arm/mve.md: Use VxBI instead of HI. >> >> diff --git a/gcc/config/arm/arm-builtins.c b/gcc/config/arm/arm-builtins.c >> index 06ff9d2278a..e58580bb828 100644 >> --- a/gcc/config/arm/arm-builtins.c >> +++ b/gcc/config/arm/arm-builtins.c >> @@ -738,13 +738,13 @@ arm_strss_p_qualifiers[SIMD_MAX_BUILTIN_ARGS] >> static enum arm_type_qualifiers >> arm_strsbs_p_qualifiers[SIMD_MAX_BUILTIN_ARGS] >> = { qualifier_void, qualifier_unsigned, qualifier_immediate, >> - qualifier_none, qualifier_unsigned}; >> + qualifier_none, qualifier_predicate}; >> #define STRSBS_P_QUALIFIERS (arm_strsbs_p_qualifiers) >> >> static enum arm_type_qualifiers >> arm_strsbu_p_qualifiers[SIMD_MAX_BUILTIN_ARGS] >> = { qualifier_void, qualifier_unsigned, qualifier_immediate, >> - qualifier_unsigned, qualifier_unsigned}; >> + qualifier_unsigned, qualifier_predicate}; >> #define STRSBU_P_QUALIFIERS (arm_strsbu_p_qualifiers) >> >> static enum arm_type_qualifiers >> @@ -780,13 +780,13 @@ arm_ldrgbu_qualifiers[SIMD_MAX_BUILTIN_ARGS] >> static enum arm_type_qualifiers >> arm_ldrgbs_z_qualifiers[SIMD_MAX_BUILTIN_ARGS] >> = { qualifier_none, qualifier_unsigned, qualifier_immediate, >> - qualifier_unsigned}; >> + qualifier_predicate}; >> #define LDRGBS_Z_QUALIFIERS (arm_ldrgbs_z_qualifiers) >> >> static enum arm_type_qualifiers >> arm_ldrgbu_z_qualifiers[SIMD_MAX_BUILTIN_ARGS] >> = { qualifier_unsigned, qualifier_unsigned, qualifier_immediate, >> - qualifier_unsigned}; >> + qualifier_predicate}; >> #define LDRGBU_Z_QUALIFIERS (arm_ldrgbu_z_qualifiers) >> >> static enum arm_type_qualifiers >> @@ -826,7 +826,7 @@ arm_ldrgbwbxu_qualifiers[SIMD_MAX_BUILTIN_ARGS] >> static enum arm_type_qualifiers >> arm_ldrgbwbxu_z_qualifiers[SIMD_MAX_BUILTIN_ARGS] >> = { qualifier_unsigned, qualifier_unsigned, qualifier_immediate, >> - qualifier_unsigned}; >> + qualifier_predicate}; >> #define LDRGBWBXU_Z_QUALIFIERS (arm_ldrgbwbxu_z_qualifiers) >> >> static enum arm_type_qualifiers >> @@ -842,13 +842,13 @@ arm_ldrgbwbu_qualifiers[SIMD_MAX_BUILTIN_ARGS] >> static enum arm_type_qualifiers >> arm_ldrgbwbs_z_qualifiers[SIMD_MAX_BUILTIN_ARGS] >> = { qualifier_none, qualifier_unsigned, qualifier_immediate, >> - qualifier_unsigned}; >> + qualifier_predicate}; >> #define LDRGBWBS_Z_QUALIFIERS (arm_ldrgbwbs_z_qualifiers) >> >> static enum arm_type_qualifiers >> arm_ldrgbwbu_z_qualifiers[SIMD_MAX_BUILTIN_ARGS] >> = { qualifier_unsigned, qualifier_unsigned, qualifier_immediate, >> - qualifier_unsigned}; >> + qualifier_predicate}; >> #define LDRGBWBU_Z_QUALIFIERS (arm_ldrgbwbu_z_qualifiers) >> >> static enum arm_type_qualifiers >> @@ -864,13 +864,13 @@ arm_strsbwbu_qualifiers[SIMD_MAX_BUILTIN_ARGS] >> static enum arm_type_qualifiers >> arm_strsbwbs_p_qualifiers[SIMD_MAX_BUILTIN_ARGS] >> = { qualifier_unsigned, qualifier_unsigned, qualifier_const, >> - qualifier_none, qualifier_unsigned}; >> + qualifier_none, qualifier_predicate}; >> #define STRSBWBS_P_QUALIFIERS (arm_strsbwbs_p_qualifiers) >> >> static enum arm_type_qualifiers >> arm_strsbwbu_p_qualifiers[SIMD_MAX_BUILTIN_ARGS] >> = { qualifier_unsigned, qualifier_unsigned, qualifier_const, >> - qualifier_unsigned, qualifier_unsigned}; >> + qualifier_unsigned, qualifier_predicate}; >> #define STRSBWBU_P_QUALIFIERS (arm_strsbwbu_p_qualifiers) >> >> static enum arm_type_qualifiers >> diff --git a/gcc/config/arm/mve.md b/gcc/config/arm/mve.md >> index 2f36d47c800..241195909da 100644 >> --- a/gcc/config/arm/mve.md >> +++ b/gcc/config/arm/mve.md >> @@ -7294,7 +7294,7 @@ (define_insn "mve_vstrwq_scatter_base_p_<supf>v4si" >> [(match_operand:V4SI 0 "s_register_operand" "w") >> (match_operand:SI 1 "immediate_operand" "i") >> (match_operand:V4SI 2 "s_register_operand" "w") >> - (match_operand:HI 3 "vpr_register_operand" "Up")] >> + (match_operand:V4BI 3 "vpr_register_operand" "Up")] >> VSTRWSBQ)) >> ] >> "TARGET_HAVE_MVE" >> @@ -7383,7 +7383,7 @@ (define_insn "mve_vldrwq_gather_base_z_<supf>v4si" >> [(set (match_operand:V4SI 0 "s_register_operand" "=&w") >> (unspec:V4SI [(match_operand:V4SI 1 "s_register_operand" "w") >> (match_operand:SI 2 "immediate_operand" "i") >> - (match_operand:HI 3 "vpr_register_operand" "Up")] >> + (match_operand:V4BI 3 "vpr_register_operand" "Up")] >> VLDRWGBQ)) >> ] >> "TARGET_HAVE_MVE" >> @@ -7621,7 +7621,7 @@ (define_insn "mve_vldrwq_<supf>v4si" >> (define_insn "mve_vldrwq_z_fv4sf" >> [(set (match_operand:V4SF 0 "s_register_operand" "=w") >> (unspec:V4SF [(match_operand:V4SI 1 "memory_operand" "Ux") >> - (match_operand:HI 2 "vpr_register_operand" "Up")] >> + (match_operand:V4BI 2 "vpr_register_operand" "Up")] >> VLDRWQ_F)) >> ] >> "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" >> @@ -7641,7 +7641,7 @@ (define_insn "mve_vldrwq_z_fv4sf" >> (define_insn "mve_vldrwq_z_<supf>v4si" >> [(set (match_operand:V4SI 0 "s_register_operand" "=w") >> (unspec:V4SI [(match_operand:V4SI 1 "memory_operand" "Ux") >> - (match_operand:HI 2 "vpr_register_operand" "Up")] >> + (match_operand:V4BI 2 "vpr_register_operand" "Up")] >> VLDRWQ)) >> ] >> "TARGET_HAVE_MVE" >> @@ -7825,7 +7825,7 @@ (define_insn "mve_vldrhq_gather_offset_z_fv8hf" >> [(set (match_operand:V8HF 0 "s_register_operand" "=&w") >> (unspec:V8HF [(match_operand:V8HI 1 "memory_operand" "Us") >> (match_operand:V8HI 2 "s_register_operand" "w") >> - (match_operand:HI 3 "vpr_register_operand" "Up")] >> + (match_operand:V8BI 3 "vpr_register_operand" "Up")] >> VLDRHQGO_F)) >> ] >> "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" >> @@ -7867,7 +7867,7 @@ (define_insn "mve_vldrhq_gather_shifted_offset_z_fv8hf" >> [(set (match_operand:V8HF 0 "s_register_operand" "=&w") >> (unspec:V8HF [(match_operand:V8HI 1 "memory_operand" "Us") >> (match_operand:V8HI 2 "s_register_operand" "w") >> - (match_operand:HI 3 "vpr_register_operand" "Up")] >> + (match_operand:V8BI 3 "vpr_register_operand" "Up")] >> VLDRHQGSO_F)) >> ] >> "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" >> @@ -7909,7 +7909,7 @@ (define_insn "mve_vldrwq_gather_base_z_fv4sf" >> [(set (match_operand:V4SF 0 "s_register_operand" "=&w") >> (unspec:V4SF [(match_operand:V4SI 1 "s_register_operand" "w") >> (match_operand:SI 2 "immediate_operand" "i") >> - (match_operand:HI 3 "vpr_register_operand" "Up")] >> + (match_operand:V4BI 3 "vpr_register_operand" "Up")] >> VLDRWQGB_F)) >> ] >> "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" >> @@ -7970,7 +7970,7 @@ (define_insn "mve_vldrwq_gather_offset_z_fv4sf" >> [(set (match_operand:V4SF 0 "s_register_operand" "=&w") >> (unspec:V4SF [(match_operand:V4SI 1 "memory_operand" "Us") >> (match_operand:V4SI 2 "s_register_operand" "w") >> - (match_operand:HI 3 "vpr_register_operand" "Up")] >> + (match_operand:V4BI 3 "vpr_register_operand" "Up")] >> VLDRWQGO_F)) >> ] >> "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" >> @@ -7992,7 +7992,7 @@ (define_insn "mve_vldrwq_gather_offset_z_<supf>v4si" >> [(set (match_operand:V4SI 0 "s_register_operand" "=&w") >> (unspec:V4SI [(match_operand:V4SI 1 "memory_operand" "Us") >> (match_operand:V4SI 2 "s_register_operand" "w") >> - (match_operand:HI 3 "vpr_register_operand" "Up")] >> + (match_operand:V4BI 3 "vpr_register_operand" "Up")] >> VLDRWGOQ)) >> ] >> "TARGET_HAVE_MVE" >> @@ -8054,7 +8054,7 @@ (define_insn "mve_vldrwq_gather_shifted_offset_z_fv4sf" >> [(set (match_operand:V4SF 0 "s_register_operand" "=&w") >> (unspec:V4SF [(match_operand:V4SI 1 "memory_operand" "Us") >> (match_operand:V4SI 2 "s_register_operand" "w") >> - (match_operand:HI 3 "vpr_register_operand" "Up")] >> + (match_operand:V4BI 3 "vpr_register_operand" "Up")] >> VLDRWQGSO_F)) >> ] >> "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" >> @@ -8076,7 +8076,7 @@ (define_insn "mve_vldrwq_gather_shifted_offset_z_<supf>v4si" >> [(set (match_operand:V4SI 0 "s_register_operand" "=&w") >> (unspec:V4SI [(match_operand:V4SI 1 "memory_operand" "Us") >> (match_operand:V4SI 2 "s_register_operand" "w") >> - (match_operand:HI 3 "vpr_register_operand" "Up")] >> + (match_operand:V4BI 3 "vpr_register_operand" "Up")] >> VLDRWGSOQ)) >> ] >> "TARGET_HAVE_MVE" >> @@ -8116,7 +8116,7 @@ (define_insn "mve_vstrhq_fv8hf" >> (define_insn "mve_vstrhq_p_fv8hf" >> [(set (match_operand:V8HI 0 "mve_memory_operand" "=Ux") >> (unspec:V8HI [(match_operand:V8HF 1 "s_register_operand" "w") >> - (match_operand:HI 2 "vpr_register_operand" "Up")] >> + (match_operand:V8BI 2 "vpr_register_operand" "Up")] >> VSTRHQ_F)) >> ] >> "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" >> @@ -8335,7 +8335,7 @@ (define_insn "mve_vstrwq_p_fv4sf" >> (define_insn "mve_vstrwq_p_<supf>v4si" >> [(set (match_operand:V4SI 0 "memory_operand" "=Ux") >> (unspec:V4SI [(match_operand:V4SI 1 "s_register_operand" "w") >> - (match_operand:HI 2 "vpr_register_operand" "Up")] >> + (match_operand:V4BI 2 "vpr_register_operand" "Up")] >> VSTRWQ)) >> ] >> "TARGET_HAVE_MVE" >> @@ -8588,7 +8588,7 @@ (define_expand "mve_vstrhq_scatter_offset_p_fv8hf" >> [(match_operand:V8HI 0 "mve_scatter_memory") >> (match_operand:V8HI 1 "s_register_operand") >> (match_operand:V8HF 2 "s_register_operand") >> - (match_operand:HI 3 "vpr_register_operand") >> + (match_operand:V8BI 3 "vpr_register_operand") >> (unspec:V4SI [(const_int 0)] VSTRHQSO_F)] >> "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" >> { >> @@ -8606,7 +8606,7 @@ (define_insn "mve_vstrhq_scatter_offset_p_fv8hf_insn" >> [(match_operand:SI 0 "register_operand" "r") >> (match_operand:V8HI 1 "s_register_operand" "w") >> (match_operand:V8HF 2 "s_register_operand" "w") >> - (match_operand:HI 3 "vpr_register_operand" "Up")] >> + (match_operand:V8BI 3 "vpr_register_operand" "Up")] >> VSTRHQSO_F))] >> "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" >> "vpst\;vstrht.16\t%q2, [%0, %q1]" >> @@ -8647,7 +8647,7 @@ (define_expand "mve_vstrhq_scatter_shifted_offset_p_fv8hf" >> [(match_operand:V8HI 0 "memory_operand" "=Us") >> (match_operand:V8HI 1 "s_register_operand" "w") >> (match_operand:V8HF 2 "s_register_operand" "w") >> - (match_operand:HI 3 "vpr_register_operand" "Up") >> + (match_operand:V8BI 3 "vpr_register_operand" "Up") >> (unspec:V4SI [(const_int 0)] VSTRHQSSO_F)] >> "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" >> { >> @@ -8666,7 +8666,7 @@ (define_insn "mve_vstrhq_scatter_shifted_offset_p_fv8hf_insn" >> [(match_operand:SI 0 "register_operand" "r") >> (match_operand:V8HI 1 "s_register_operand" "w") >> (match_operand:V8HF 2 "s_register_operand" "w") >> - (match_operand:HI 3 "vpr_register_operand" "Up")] >> + (match_operand:V8BI 3 "vpr_register_operand" "Up")] >> VSTRHQSSO_F))] >> "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" >> "vpst\;vstrht.16\t%q2, [%0, %q1, uxtw #1]" >> @@ -8703,7 +8703,7 @@ (define_insn "mve_vstrwq_scatter_base_p_fv4sf" >> [(match_operand:V4SI 0 "s_register_operand" "w") >> (match_operand:SI 1 "immediate_operand" "i") >> (match_operand:V4SF 2 "s_register_operand" "w") >> - (match_operand:HI 3 "vpr_register_operand" "Up")] >> + (match_operand:V4BI 3 "vpr_register_operand" "Up")] >> VSTRWQSB_F)) >> ] >> "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" >> @@ -8752,7 +8752,7 @@ (define_expand "mve_vstrwq_scatter_offset_p_fv4sf" >> [(match_operand:V4SI 0 "mve_scatter_memory") >> (match_operand:V4SI 1 "s_register_operand") >> (match_operand:V4SF 2 "s_register_operand") >> - (match_operand:HI 3 "vpr_register_operand") >> + (match_operand:V4BI 3 "vpr_register_operand") >> (unspec:V4SI [(const_int 0)] VSTRWQSO_F)] >> "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" >> { >> @@ -8770,7 +8770,7 @@ (define_insn "mve_vstrwq_scatter_offset_p_fv4sf_insn" >> [(match_operand:SI 0 "register_operand" "r") >> (match_operand:V4SI 1 "s_register_operand" "w") >> (match_operand:V4SF 2 "s_register_operand" "w") >> - (match_operand:HI 3 "vpr_register_operand" "Up")] >> + (match_operand:V4BI 3 "vpr_register_operand" "Up")] >> VSTRWQSO_F))] >> "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" >> "vpst\;vstrwt.32\t%q2, [%0, %q1]" >> @@ -8783,7 +8783,7 @@ (define_expand "mve_vstrwq_scatter_offset_p_<supf>v4si" >> [(match_operand:V4SI 0 "mve_scatter_memory") >> (match_operand:V4SI 1 "s_register_operand") >> (match_operand:V4SI 2 "s_register_operand") >> - (match_operand:HI 3 "vpr_register_operand") >> + (match_operand:V4BI 3 "vpr_register_operand") >> (unspec:V4SI [(const_int 0)] VSTRWSOQ)] >> "TARGET_HAVE_MVE" >> { >> @@ -8801,7 +8801,7 @@ (define_insn "mve_vstrwq_scatter_offset_p_<supf>v4si_insn" >> [(match_operand:SI 0 "register_operand" "r") >> (match_operand:V4SI 1 "s_register_operand" "w") >> (match_operand:V4SI 2 "s_register_operand" "w") >> - (match_operand:HI 3 "vpr_register_operand" "Up")] >> + (match_operand:V4BI 3 "vpr_register_operand" "Up")] >> VSTRWSOQ))] >> "TARGET_HAVE_MVE" >> "vpst\;vstrwt.32\t%q2, [%0, %q1]" >> @@ -8870,7 +8870,7 @@ (define_expand "mve_vstrwq_scatter_shifted_offset_p_fv4sf" >> [(match_operand:V4SI 0 "mve_scatter_memory") >> (match_operand:V4SI 1 "s_register_operand") >> (match_operand:V4SF 2 "s_register_operand") >> - (match_operand:HI 3 "vpr_register_operand") >> + (match_operand:V4BI 3 "vpr_register_operand") >> (unspec:V4SI [(const_int 0)] VSTRWQSSO_F)] >> "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" >> { >> @@ -8889,7 +8889,7 @@ (define_insn "mve_vstrwq_scatter_shifted_offset_p_fv4sf_insn" >> [(match_operand:SI 0 "register_operand" "r") >> (match_operand:V4SI 1 "s_register_operand" "w") >> (match_operand:V4SF 2 "s_register_operand" "w") >> - (match_operand:HI 3 "vpr_register_operand" "Up")] >> + (match_operand:V4BI 3 "vpr_register_operand" "Up")] >> VSTRWQSSO_F))] >> "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" >> "vpst\;vstrwt.32\t%q2, [%0, %q1, uxtw #2]" >> @@ -8902,7 +8902,7 @@ (define_expand "mve_vstrwq_scatter_shifted_offset_p_<supf>v4si" >> [(match_operand:V4SI 0 "mve_scatter_memory") >> (match_operand:V4SI 1 "s_register_operand") >> (match_operand:V4SI 2 "s_register_operand") >> - (match_operand:HI 3 "vpr_register_operand") >> + (match_operand:V4BI 3 "vpr_register_operand") >> (unspec:V4SI [(const_int 0)] VSTRWSSOQ)] >> "TARGET_HAVE_MVE" >> { >> @@ -8921,7 +8921,7 @@ (define_insn "mve_vstrwq_scatter_shifted_offset_p_<supf>v4si_insn" >> [(match_operand:SI 0 "register_operand" "r") >> (match_operand:V4SI 1 "s_register_operand" "w") >> (match_operand:V4SI 2 "s_register_operand" "w") >> - (match_operand:HI 3 "vpr_register_operand" "Up")] >> + (match_operand:V4BI 3 "vpr_register_operand" "Up")] >> VSTRWSSOQ))] >> "TARGET_HAVE_MVE" >> "vpst\;vstrwt.32\t%q2, [%0, %q1, uxtw #2]" >> @@ -9388,7 +9388,7 @@ (define_insn "mve_vstrwq_scatter_base_wb_p_<supf>v4si" >> [(match_operand:V4SI 1 "s_register_operand" "0") >> (match_operand:SI 2 "mve_vldrd_immediate" "Ri") >> (match_operand:V4SI 3 "s_register_operand" "w") >> - (match_operand:HI 4 "vpr_register_operand")] >> + (match_operand:V4BI 4 "vpr_register_operand")] >> VSTRWSBWBQ)) >> (set (match_operand:V4SI 0 "s_register_operand" "=w") >> (unspec:V4SI [(match_dup 1) (match_dup 2)] >> @@ -9439,7 +9439,7 @@ (define_insn "mve_vstrwq_scatter_base_wb_p_fv4sf" >> [(match_operand:V4SI 1 "s_register_operand" "0") >> (match_operand:SI 2 "mve_vldrd_immediate" "Ri") >> (match_operand:V4SF 3 "s_register_operand" "w") >> - (match_operand:HI 4 "vpr_register_operand")] >> + (match_operand:V4BI 4 "vpr_register_operand")] >> VSTRWQSBWB_F)) >> (set (match_operand:V4SI 0 "s_register_operand" "=w") >> (unspec:V4SI [(match_dup 1) (match_dup 2)] >> @@ -9563,7 +9563,7 @@ (define_expand "mve_vldrwq_gather_base_wb_z_<supf>v4si" >> [(match_operand:V4SI 0 "s_register_operand") >> (match_operand:V4SI 1 "s_register_operand") >> (match_operand:SI 2 "mve_vldrd_immediate") >> - (match_operand:HI 3 "vpr_register_operand") >> + (match_operand:V4BI 3 "vpr_register_operand") >> (unspec:V4SI [(const_int 0)] VLDRWGBWBQ)] >> "TARGET_HAVE_MVE" >> { >> @@ -9578,7 +9578,7 @@ (define_expand "mve_vldrwq_gather_base_nowb_z_<supf>v4si" >> [(match_operand:V4SI 0 "s_register_operand") >> (match_operand:V4SI 1 "s_register_operand") >> (match_operand:SI 2 "mve_vldrd_immediate") >> - (match_operand:HI 3 "vpr_register_operand") >> + (match_operand:V4BI 3 "vpr_register_operand") >> (unspec:V4SI [(const_int 0)] VLDRWGBWBQ)] >> "TARGET_HAVE_MVE" >> { >> @@ -9597,7 +9597,7 @@ (define_insn "mve_vldrwq_gather_base_wb_z_<supf>v4si_insn" >> [(set (match_operand:V4SI 0 "s_register_operand" "=&w") >> (unspec:V4SI [(match_operand:V4SI 2 "s_register_operand" "1") >> (match_operand:SI 3 "mve_vldrd_immediate" "Ri") >> - (match_operand:HI 4 "vpr_register_operand" "Up") >> + (match_operand:V4BI 4 "vpr_register_operand" "Up") >> (mem:BLK (scratch))] >> VLDRWGBWBQ)) >> (set (match_operand:V4SI 1 "s_register_operand" "=&w") >> @@ -9671,7 +9671,7 @@ (define_expand "mve_vldrwq_gather_base_wb_z_fv4sf" >> [(match_operand:V4SI 0 "s_register_operand") >> (match_operand:V4SI 1 "s_register_operand") >> (match_operand:SI 2 "mve_vldrd_immediate") >> - (match_operand:HI 3 "vpr_register_operand") >> + (match_operand:V4BI 3 "vpr_register_operand") >> (unspec:V4SI [(const_int 0)] VLDRWQGBWB_F)] >> "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" >> { >> @@ -9687,7 +9687,7 @@ (define_expand "mve_vldrwq_gather_base_nowb_z_fv4sf" >> [(match_operand:V4SF 0 "s_register_operand") >> (match_operand:V4SI 1 "s_register_operand") >> (match_operand:SI 2 "mve_vldrd_immediate") >> - (match_operand:HI 3 "vpr_register_operand") >> + (match_operand:V4BI 3 "vpr_register_operand") >> (unspec:V4SI [(const_int 0)] VLDRWQGBWB_F)] >> "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" >> { >> @@ -9706,7 +9706,7 @@ (define_insn "mve_vldrwq_gather_base_wb_z_fv4sf_insn" >> [(set (match_operand:V4SF 0 "s_register_operand" "=&w") >> (unspec:V4SF [(match_operand:V4SI 2 "s_register_operand" "1") >> (match_operand:SI 3 "mve_vldrd_immediate" "Ri") >> - (match_operand:HI 4 "vpr_register_operand" "Up") >> + (match_operand:V4BI 4 "vpr_register_operand" "Up") >> (mem:BLK (scratch))] >> VLDRWQGBWB_F)) >> (set (match_operand:V4SI 1 "s_register_operand" "=&w") ^ permalink raw reply [flat|nested] 9+ messages in thread
* [PATCH 13/13] arm: Convert more MVE/CDE builtins to predicate qualifiers 2021-09-07 9:20 [PATCH 10/13] arm: Convert remaining MVE vcmp builtins to predicate qualifiers Christophe Lyon 2021-09-07 9:20 ` [PATCH 11/13] arm: Convert more MVE " Christophe Lyon 2021-09-07 9:20 ` [PATCH 12/13] arm: Convert more load/store " Christophe Lyon @ 2021-09-07 9:21 ` Christophe Lyon 2021-10-11 14:21 ` Richard Sandiford 2021-10-11 14:10 ` [PATCH 10/13] arm: Convert remaining MVE vcmp " Richard Sandiford 3 siblings, 1 reply; 9+ messages in thread From: Christophe Lyon @ 2021-09-07 9:21 UTC (permalink / raw) To: gcc-patches This patch covers a few non-load/store builtins where we do not use the <mode> iterator and thus we cannot use <MVE_vpred>. We need to update the expected code in cde-mve-full-assembly.c because we now use mve_movv16qi instead of movhi to generate the vmsr instruction. 2021-09-02 Christophe Lyon <christophe.lyon@foss.st.com> gcc/ PR target/100757 PR target/101325 * config/arm/arm-builtins.c (CX_UNARY_UNONE_QUALIFIERS): Use predicate. (CX_BINARY_UNONE_QUALIFIERS): Likewise. (CX_TERNARY_UNONE_QUALIFIERS): Likewise. (TERNOP_NONE_NONE_NONE_UNONE_QUALIFIERS): Delete. (QUADOP_NONE_NONE_NONE_NONE_UNONE_QUALIFIERS): Delete. (QUADOP_UNONE_UNONE_UNONE_UNONE_UNONE_QUALIFIERS): Delete. * config/arm/arm_mve_builtins.def: Use predicated qualifiers. * config/arm/mve.md: Use VxBI instead of HI. gcc/testsuite/ * gcc.target/arm/acle/cde-mve-full-assembly.c: Remove expected '@ movhi'. diff --git a/gcc/config/arm/arm-builtins.c b/gcc/config/arm/arm-builtins.c index e58580bb828..d725458f1ad 100644 --- a/gcc/config/arm/arm-builtins.c +++ b/gcc/config/arm/arm-builtins.c @@ -344,7 +344,7 @@ static enum arm_type_qualifiers arm_cx_unary_unone_qualifiers[SIMD_MAX_BUILTIN_ARGS] = { qualifier_none, qualifier_immediate, qualifier_none, qualifier_unsigned_immediate, - qualifier_unsigned }; + qualifier_predicate }; #define CX_UNARY_UNONE_QUALIFIERS (arm_cx_unary_unone_qualifiers) /* T (immediate, T, T, unsigned immediate). */ @@ -353,7 +353,7 @@ arm_cx_binary_unone_qualifiers[SIMD_MAX_BUILTIN_ARGS] = { qualifier_none, qualifier_immediate, qualifier_none, qualifier_none, qualifier_unsigned_immediate, - qualifier_unsigned }; + qualifier_predicate }; #define CX_BINARY_UNONE_QUALIFIERS (arm_cx_binary_unone_qualifiers) /* T (immediate, T, T, T, unsigned immediate). */ @@ -362,7 +362,7 @@ arm_cx_ternary_unone_qualifiers[SIMD_MAX_BUILTIN_ARGS] = { qualifier_none, qualifier_immediate, qualifier_none, qualifier_none, qualifier_none, qualifier_unsigned_immediate, - qualifier_unsigned }; + qualifier_predicate }; #define CX_TERNARY_UNONE_QUALIFIERS (arm_cx_ternary_unone_qualifiers) /* The first argument (return type) of a store should be void type, @@ -558,12 +558,6 @@ arm_ternop_none_none_none_imm_qualifiers[SIMD_MAX_BUILTIN_ARGS] #define TERNOP_NONE_NONE_NONE_IMM_QUALIFIERS \ (arm_ternop_none_none_none_imm_qualifiers) -static enum arm_type_qualifiers -arm_ternop_none_none_none_unone_qualifiers[SIMD_MAX_BUILTIN_ARGS] - = { qualifier_none, qualifier_none, qualifier_none, qualifier_unsigned }; -#define TERNOP_NONE_NONE_NONE_UNONE_QUALIFIERS \ - (arm_ternop_none_none_none_unone_qualifiers) - static enum arm_type_qualifiers arm_ternop_none_none_none_pred_qualifiers[SIMD_MAX_BUILTIN_ARGS] = { qualifier_none, qualifier_none, qualifier_none, qualifier_predicate }; @@ -616,13 +610,6 @@ arm_quadop_unone_unone_none_none_pred_qualifiers[SIMD_MAX_BUILTIN_ARGS] #define QUADOP_UNONE_UNONE_NONE_NONE_PRED_QUALIFIERS \ (arm_quadop_unone_unone_none_none_pred_qualifiers) -static enum arm_type_qualifiers -arm_quadop_none_none_none_none_unone_qualifiers[SIMD_MAX_BUILTIN_ARGS] - = { qualifier_none, qualifier_none, qualifier_none, qualifier_none, - qualifier_unsigned }; -#define QUADOP_NONE_NONE_NONE_NONE_UNONE_QUALIFIERS \ - (arm_quadop_none_none_none_none_unone_qualifiers) - static enum arm_type_qualifiers arm_quadop_none_none_none_none_pred_qualifiers[SIMD_MAX_BUILTIN_ARGS] = { qualifier_none, qualifier_none, qualifier_none, qualifier_none, @@ -637,13 +624,6 @@ arm_quadop_none_none_none_imm_pred_qualifiers[SIMD_MAX_BUILTIN_ARGS] #define QUADOP_NONE_NONE_NONE_IMM_PRED_QUALIFIERS \ (arm_quadop_none_none_none_imm_pred_qualifiers) -static enum arm_type_qualifiers -arm_quadop_unone_unone_unone_unone_unone_qualifiers[SIMD_MAX_BUILTIN_ARGS] - = { qualifier_unsigned, qualifier_unsigned, qualifier_unsigned, - qualifier_unsigned, qualifier_unsigned }; -#define QUADOP_UNONE_UNONE_UNONE_UNONE_UNONE_QUALIFIERS \ - (arm_quadop_unone_unone_unone_unone_unone_qualifiers) - static enum arm_type_qualifiers arm_quadop_unone_unone_unone_unone_pred_qualifiers[SIMD_MAX_BUILTIN_ARGS] = { qualifier_unsigned, qualifier_unsigned, qualifier_unsigned, diff --git a/gcc/config/arm/arm_mve_builtins.def b/gcc/config/arm/arm_mve_builtins.def index bb79edf83ca..0fb53d866ec 100644 --- a/gcc/config/arm/arm_mve_builtins.def +++ b/gcc/config/arm/arm_mve_builtins.def @@ -87,8 +87,8 @@ VAR4 (BINOP_UNONE_UNONE_UNONE, vcreateq_u, v16qi, v8hi, v4si, v2di) VAR4 (BINOP_NONE_UNONE_UNONE, vcreateq_s, v16qi, v8hi, v4si, v2di) VAR3 (BINOP_UNONE_UNONE_IMM, vshrq_n_u, v16qi, v8hi, v4si) VAR3 (BINOP_NONE_NONE_IMM, vshrq_n_s, v16qi, v8hi, v4si) -VAR1 (BINOP_NONE_NONE_UNONE, vaddlvq_p_s, v4si) -VAR1 (BINOP_UNONE_UNONE_UNONE, vaddlvq_p_u, v4si) +VAR1 (BINOP_NONE_NONE_PRED, vaddlvq_p_s, v4si) +VAR1 (BINOP_UNONE_UNONE_PRED, vaddlvq_p_u, v4si) VAR3 (BINOP_PRED_NONE_NONE, vcmpneq_, v16qi, v8hi, v4si) VAR3 (BINOP_NONE_NONE_NONE, vshlq_s, v16qi, v8hi, v4si) VAR3 (BINOP_UNONE_UNONE_NONE, vshlq_u, v16qi, v8hi, v4si) @@ -465,20 +465,20 @@ VAR2 (TERNOP_NONE_NONE_NONE_IMM, vqshrnbq_n_s, v8hi, v4si) VAR2 (TERNOP_NONE_NONE_NONE_IMM, vqrshrntq_n_s, v8hi, v4si) VAR2 (TERNOP_NONE_NONE_IMM_PRED, vorrq_m_n_s, v8hi, v4si) VAR2 (TERNOP_NONE_NONE_IMM_PRED, vmvnq_m_n_s, v8hi, v4si) -VAR1 (TERNOP_UNONE_UNONE_UNONE_UNONE, vrmlaldavhq_p_u, v4si) -VAR1 (TERNOP_UNONE_UNONE_UNONE_UNONE, vrev16q_m_u, v16qi) -VAR1 (TERNOP_UNONE_UNONE_UNONE_UNONE, vaddlvaq_p_u, v4si) -VAR1 (TERNOP_NONE_NONE_NONE_UNONE, vrmlsldavhxq_p_s, v4si) -VAR1 (TERNOP_NONE_NONE_NONE_UNONE, vrmlsldavhq_p_s, v4si) -VAR1 (TERNOP_NONE_NONE_NONE_UNONE, vrmlaldavhxq_p_s, v4si) -VAR1 (TERNOP_NONE_NONE_NONE_UNONE, vrmlaldavhq_p_s, v4si) -VAR1 (TERNOP_NONE_NONE_NONE_UNONE, vrev32q_m_f, v8hf) -VAR1 (TERNOP_NONE_NONE_NONE_UNONE, vrev16q_m_s, v16qi) -VAR1 (TERNOP_NONE_NONE_NONE_UNONE, vcvttq_m_f32_f16, v4sf) -VAR1 (TERNOP_NONE_NONE_NONE_UNONE, vcvttq_m_f16_f32, v8hf) -VAR1 (TERNOP_NONE_NONE_NONE_UNONE, vcvtbq_m_f32_f16, v4sf) -VAR1 (TERNOP_NONE_NONE_NONE_UNONE, vcvtbq_m_f16_f32, v8hf) -VAR1 (TERNOP_NONE_NONE_NONE_UNONE, vaddlvaq_p_s, v4si) +VAR1 (TERNOP_UNONE_UNONE_UNONE_PRED, vrmlaldavhq_p_u, v4si) +VAR1 (TERNOP_UNONE_UNONE_UNONE_PRED, vrev16q_m_u, v16qi) +VAR1 (TERNOP_UNONE_UNONE_UNONE_PRED, vaddlvaq_p_u, v4si) +VAR1 (TERNOP_NONE_NONE_NONE_PRED, vrmlsldavhxq_p_s, v4si) +VAR1 (TERNOP_NONE_NONE_NONE_PRED, vrmlsldavhq_p_s, v4si) +VAR1 (TERNOP_NONE_NONE_NONE_PRED, vrmlaldavhxq_p_s, v4si) +VAR1 (TERNOP_NONE_NONE_NONE_PRED, vrmlaldavhq_p_s, v4si) +VAR1 (TERNOP_NONE_NONE_NONE_PRED, vrev32q_m_f, v8hf) +VAR1 (TERNOP_NONE_NONE_NONE_PRED, vrev16q_m_s, v16qi) +VAR1 (TERNOP_NONE_NONE_NONE_PRED, vcvttq_m_f32_f16, v4sf) +VAR1 (TERNOP_NONE_NONE_NONE_PRED, vcvttq_m_f16_f32, v8hf) +VAR1 (TERNOP_NONE_NONE_NONE_PRED, vcvtbq_m_f32_f16, v4sf) +VAR1 (TERNOP_NONE_NONE_NONE_PRED, vcvtbq_m_f16_f32, v8hf) +VAR1 (TERNOP_NONE_NONE_NONE_PRED, vaddlvaq_p_s, v4si) VAR1 (TERNOP_NONE_NONE_NONE_NONE, vrmlsldavhaxq_s, v4si) VAR1 (TERNOP_NONE_NONE_NONE_NONE, vrmlsldavhaq_s, v4si) VAR1 (TERNOP_NONE_NONE_NONE_NONE, vrmlaldavhaxq_s, v4si) @@ -629,11 +629,11 @@ VAR2 (QUADOP_NONE_NONE_NONE_IMM_PRED, vqshrntq_m_n_s, v8hi, v4si) VAR2 (QUADOP_NONE_NONE_NONE_IMM_PRED, vqshrnbq_m_n_s, v8hi, v4si) VAR2 (QUADOP_NONE_NONE_NONE_IMM_PRED, vqrshrntq_m_n_s, v8hi, v4si) VAR2 (QUADOP_NONE_NONE_NONE_IMM_PRED, vqrshrnbq_m_n_s, v8hi, v4si) -VAR1 (QUADOP_UNONE_UNONE_UNONE_UNONE_UNONE, vrmlaldavhaq_p_u, v4si) -VAR1 (QUADOP_NONE_NONE_NONE_NONE_UNONE, vrmlsldavhaxq_p_s, v4si) -VAR1 (QUADOP_NONE_NONE_NONE_NONE_UNONE, vrmlsldavhaq_p_s, v4si) -VAR1 (QUADOP_NONE_NONE_NONE_NONE_UNONE, vrmlaldavhaxq_p_s, v4si) -VAR1 (QUADOP_NONE_NONE_NONE_NONE_UNONE, vrmlaldavhaq_p_s, v4si) +VAR1 (QUADOP_UNONE_UNONE_UNONE_UNONE_PRED, vrmlaldavhaq_p_u, v4si) +VAR1 (QUADOP_NONE_NONE_NONE_NONE_PRED, vrmlsldavhaxq_p_s, v4si) +VAR1 (QUADOP_NONE_NONE_NONE_NONE_PRED, vrmlsldavhaq_p_s, v4si) +VAR1 (QUADOP_NONE_NONE_NONE_NONE_PRED, vrmlaldavhaxq_p_s, v4si) +VAR1 (QUADOP_NONE_NONE_NONE_NONE_PRED, vrmlaldavhaq_p_s, v4si) VAR2 (QUADOP_UNONE_UNONE_NONE_IMM_PRED, vcvtq_m_n_from_f_u, v8hi, v4si) VAR2 (QUADOP_NONE_NONE_NONE_IMM_PRED, vcvtq_m_n_from_f_s, v8hi, v4si) VAR2 (QUADOP_NONE_NONE_NONE_NONE_PRED, vbrsrq_m_n_f, v8hf, v4sf) @@ -845,14 +845,14 @@ VAR1 (BINOP_NONE_NONE_NONE, vsbciq_s, v4si) VAR1 (BINOP_UNONE_UNONE_UNONE, vsbciq_u, v4si) VAR1 (BINOP_NONE_NONE_NONE, vsbcq_s, v4si) VAR1 (BINOP_UNONE_UNONE_UNONE, vsbcq_u, v4si) -VAR1 (QUADOP_NONE_NONE_NONE_NONE_UNONE, vadciq_m_s, v4si) -VAR1 (QUADOP_UNONE_UNONE_UNONE_UNONE_UNONE, vadciq_m_u, v4si) -VAR1 (QUADOP_NONE_NONE_NONE_NONE_UNONE, vadcq_m_s, v4si) -VAR1 (QUADOP_UNONE_UNONE_UNONE_UNONE_UNONE, vadcq_m_u, v4si) -VAR1 (QUADOP_NONE_NONE_NONE_NONE_UNONE, vsbciq_m_s, v4si) -VAR1 (QUADOP_UNONE_UNONE_UNONE_UNONE_UNONE, vsbciq_m_u, v4si) -VAR1 (QUADOP_NONE_NONE_NONE_NONE_UNONE, vsbcq_m_s, v4si) -VAR1 (QUADOP_UNONE_UNONE_UNONE_UNONE_UNONE, vsbcq_m_u, v4si) +VAR1 (QUADOP_NONE_NONE_NONE_NONE_PRED, vadciq_m_s, v4si) +VAR1 (QUADOP_UNONE_UNONE_UNONE_UNONE_PRED, vadciq_m_u, v4si) +VAR1 (QUADOP_NONE_NONE_NONE_NONE_PRED, vadcq_m_s, v4si) +VAR1 (QUADOP_UNONE_UNONE_UNONE_UNONE_PRED, vadcq_m_u, v4si) +VAR1 (QUADOP_NONE_NONE_NONE_NONE_PRED, vsbciq_m_s, v4si) +VAR1 (QUADOP_UNONE_UNONE_UNONE_UNONE_PRED, vsbciq_m_u, v4si) +VAR1 (QUADOP_NONE_NONE_NONE_NONE_PRED, vsbcq_m_s, v4si) +VAR1 (QUADOP_UNONE_UNONE_UNONE_UNONE_PRED, vsbcq_m_u, v4si) VAR5 (STORE1, vst2q, v16qi, v8hi, v4si, v8hf, v4sf) VAR5 (LOAD1, vld4q, v16qi, v8hi, v4si, v8hf, v4sf) VAR5 (LOAD1, vld2q, v16qi, v8hi, v4si, v8hf, v4sf) diff --git a/gcc/config/arm/mve.md b/gcc/config/arm/mve.md index 241195909da..f73b5f6f1f1 100644 --- a/gcc/config/arm/mve.md +++ b/gcc/config/arm/mve.md @@ -826,7 +826,7 @@ (define_insn "mve_vaddlvq_p_<supf>v4si" [ (set (match_operand:DI 0 "s_register_operand" "=r") (unspec:DI [(match_operand:V4SI 1 "s_register_operand" "w") - (match_operand:HI 2 "vpr_register_operand" "Up")] + (match_operand:V4BI 2 "vpr_register_operand" "Up")] VADDLVQ_P)) ] "TARGET_HAVE_MVE" @@ -3751,7 +3751,7 @@ (define_insn "mve_vaddlvaq_p_<supf>v4si" (set (match_operand:DI 0 "s_register_operand" "=r") (unspec:DI [(match_operand:DI 1 "s_register_operand" "0") (match_operand:V4SI 2 "s_register_operand" "w") - (match_operand:HI 3 "vpr_register_operand" "Up")] + (match_operand:V4BI 3 "vpr_register_operand" "Up")] VADDLVAQ_P)) ] "TARGET_HAVE_MVE" @@ -3961,7 +3961,7 @@ (define_insn "mve_vcvtbq_m_f16_f32v8hf" (set (match_operand:V8HF 0 "s_register_operand" "=w") (unspec:V8HF [(match_operand:V8HF 1 "s_register_operand" "0") (match_operand:V4SF 2 "s_register_operand" "w") - (match_operand:HI 3 "vpr_register_operand" "Up")] + (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")] VCVTBQ_M_F16_F32)) ] "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" @@ -3977,7 +3977,7 @@ (define_insn "mve_vcvtbq_m_f32_f16v4sf" (set (match_operand:V4SF 0 "s_register_operand" "=w") (unspec:V4SF [(match_operand:V4SF 1 "s_register_operand" "0") (match_operand:V8HF 2 "s_register_operand" "w") - (match_operand:HI 3 "vpr_register_operand" "Up")] + (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")] VCVTBQ_M_F32_F16)) ] "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" @@ -3993,7 +3993,7 @@ (define_insn "mve_vcvttq_m_f16_f32v8hf" (set (match_operand:V8HF 0 "s_register_operand" "=w") (unspec:V8HF [(match_operand:V8HF 1 "s_register_operand" "0") (match_operand:V4SF 2 "s_register_operand" "w") - (match_operand:HI 3 "vpr_register_operand" "Up")] + (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")] VCVTTQ_M_F16_F32)) ] "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" @@ -4009,7 +4009,7 @@ (define_insn "mve_vcvttq_m_f32_f16v4sf" (set (match_operand:V4SF 0 "s_register_operand" "=w") (unspec:V4SF [(match_operand:V4SF 1 "s_register_operand" "0") (match_operand:V8HF 2 "s_register_operand" "w") - (match_operand:HI 3 "vpr_register_operand" "Up")] + (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")] VCVTTQ_M_F32_F16)) ] "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" @@ -4607,7 +4607,7 @@ (define_insn "mve_vrev32q_m_fv8hf" (set (match_operand:V8HF 0 "s_register_operand" "=w") (unspec:V8HF [(match_operand:V8HF 1 "s_register_operand" "0") (match_operand:V8HF 2 "s_register_operand" "w") - (match_operand:HI 3 "vpr_register_operand" "Up")] + (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")] VREV32Q_M_F)) ] "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" @@ -4671,7 +4671,7 @@ (define_insn "mve_vrmlaldavhxq_p_sv4si" (set (match_operand:DI 0 "s_register_operand" "=r") (unspec:DI [(match_operand:V4SI 1 "s_register_operand" "w") (match_operand:V4SI 2 "s_register_operand" "w") - (match_operand:HI 3 "vpr_register_operand" "Up")] + (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")] VRMLALDAVHXQ_P_S)) ] "TARGET_HAVE_MVE" @@ -4703,7 +4703,7 @@ (define_insn "mve_vrmlsldavhq_p_sv4si" (set (match_operand:DI 0 "s_register_operand" "=r") (unspec:DI [(match_operand:V4SI 1 "s_register_operand" "w") (match_operand:V4SI 2 "s_register_operand" "w") - (match_operand:HI 3 "vpr_register_operand" "Up")] + (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")] VRMLSLDAVHQ_P_S)) ] "TARGET_HAVE_MVE" @@ -4719,7 +4719,7 @@ (define_insn "mve_vrmlsldavhxq_p_sv4si" (set (match_operand:DI 0 "s_register_operand" "=r") (unspec:DI [(match_operand:V4SI 1 "s_register_operand" "w") (match_operand:V4SI 2 "s_register_operand" "w") - (match_operand:HI 3 "vpr_register_operand" "Up")] + (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")] VRMLSLDAVHXQ_P_S)) ] "TARGET_HAVE_MVE" @@ -4944,7 +4944,7 @@ (define_insn "mve_vrev16q_m_<supf>v16qi" (set (match_operand:V16QI 0 "s_register_operand" "=w") (unspec:V16QI [(match_operand:V16QI 1 "s_register_operand" "0") (match_operand:V16QI 2 "s_register_operand" "w") - (match_operand:HI 3 "vpr_register_operand" "Up")] + (match_operand:V16BI 3 "vpr_register_operand" "Up")] VREV16Q_M)) ] "TARGET_HAVE_MVE" @@ -4976,7 +4976,7 @@ (define_insn "mve_vrmlaldavhq_p_<supf>v4si" (set (match_operand:DI 0 "s_register_operand" "=r") (unspec:DI [(match_operand:V4SI 1 "s_register_operand" "w") (match_operand:V4SI 2 "s_register_operand" "w") - (match_operand:HI 3 "vpr_register_operand" "Up")] + (match_operand:V4BI 3 "vpr_register_operand" "Up")] VRMLALDAVHQ_P)) ] "TARGET_HAVE_MVE" @@ -6245,7 +6245,7 @@ (define_insn "mve_vrmlaldavhaq_p_sv4si" (unspec:DI [(match_operand:DI 1 "s_register_operand" "0") (match_operand:V4SI 2 "s_register_operand" "w") (match_operand:V4SI 3 "s_register_operand" "w") - (match_operand:HI 4 "vpr_register_operand" "Up")] + (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")] VRMLALDAVHAQ_P_S)) ] "TARGET_HAVE_MVE" @@ -6568,7 +6568,7 @@ (define_insn "mve_vrmlaldavhaq_p_uv4si" (unspec:DI [(match_operand:DI 1 "s_register_operand" "0") (match_operand:V4SI 2 "s_register_operand" "w") (match_operand:V4SI 3 "s_register_operand" "w") - (match_operand:HI 4 "vpr_register_operand" "Up")] + (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")] VRMLALDAVHAQ_P_U)) ] "TARGET_HAVE_MVE" @@ -6585,7 +6585,7 @@ (define_insn "mve_vrmlaldavhaxq_p_sv4si" (unspec:DI [(match_operand:DI 1 "s_register_operand" "0") (match_operand:V4SI 2 "s_register_operand" "w") (match_operand:V4SI 3 "s_register_operand" "w") - (match_operand:HI 4 "vpr_register_operand" "Up")] + (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")] VRMLALDAVHAXQ_P_S)) ] "TARGET_HAVE_MVE" @@ -6602,7 +6602,7 @@ (define_insn "mve_vrmlsldavhaq_p_sv4si" (unspec:DI [(match_operand:DI 1 "s_register_operand" "0") (match_operand:V4SI 2 "s_register_operand" "w") (match_operand:V4SI 3 "s_register_operand" "w") - (match_operand:HI 4 "vpr_register_operand" "Up")] + (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")] VRMLSLDAVHAQ_P_S)) ] "TARGET_HAVE_MVE" @@ -6619,7 +6619,7 @@ (define_insn "mve_vrmlsldavhaxq_p_sv4si" (unspec:DI [(match_operand:DI 1 "s_register_operand" "0") (match_operand:V4SI 2 "s_register_operand" "w") (match_operand:V4SI 3 "s_register_operand" "w") - (match_operand:HI 4 "vpr_register_operand" "Up")] + (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")] VRMLSLDAVHAXQ_P_S)) ] "TARGET_HAVE_MVE" @@ -7540,7 +7540,7 @@ (define_insn "mve_vldrhq_<supf><mode>" (define_insn "mve_vldrhq_z_fv8hf" [(set (match_operand:V8HF 0 "s_register_operand" "=w") (unspec:V8HF [(match_operand:V8HI 1 "mve_memory_operand" "Ux") - (match_operand:HI 2 "vpr_register_operand" "Up")] + (match_operand:<MVE_VPRED> 2 "vpr_register_operand" "Up")] VLDRHQ_F)) ] "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" @@ -8315,7 +8315,7 @@ (define_insn "mve_vstrwq_fv4sf" (define_insn "mve_vstrwq_p_fv4sf" [(set (match_operand:V4SI 0 "memory_operand" "=Ux") (unspec:V4SI [(match_operand:V4SF 1 "s_register_operand" "w") - (match_operand:HI 2 "vpr_register_operand" "Up")] + (match_operand:<MVE_VPRED> 2 "vpr_register_operand" "Up")] VSTRWQ_F)) ] "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" @@ -9856,7 +9856,7 @@ (define_insn "mve_vadciq_m_<supf>v4si" (unspec:V4SI [(match_operand:V4SI 1 "s_register_operand" "0") (match_operand:V4SI 2 "s_register_operand" "w") (match_operand:V4SI 3 "s_register_operand" "w") - (match_operand:HI 4 "vpr_register_operand" "Up")] + (match_operand:V4BI 4 "vpr_register_operand" "Up")] VADCIQ_M)) (set (reg:SI VFPCC_REGNUM) (unspec:SI [(const_int 0)] @@ -9892,7 +9892,7 @@ (define_insn "mve_vadcq_m_<supf>v4si" (unspec:V4SI [(match_operand:V4SI 1 "s_register_operand" "0") (match_operand:V4SI 2 "s_register_operand" "w") (match_operand:V4SI 3 "s_register_operand" "w") - (match_operand:HI 4 "vpr_register_operand" "Up")] + (match_operand:V4BI 4 "vpr_register_operand" "Up")] VADCQ_M)) (set (reg:SI VFPCC_REGNUM) (unspec:SI [(reg:SI VFPCC_REGNUM)] @@ -9929,7 +9929,7 @@ (define_insn "mve_vsbciq_m_<supf>v4si" (unspec:V4SI [(match_operand:V4SI 1 "s_register_operand" "w") (match_operand:V4SI 2 "s_register_operand" "w") (match_operand:V4SI 3 "s_register_operand" "w") - (match_operand:HI 4 "vpr_register_operand" "Up")] + (match_operand:V4BI 4 "vpr_register_operand" "Up")] VSBCIQ_M)) (set (reg:SI VFPCC_REGNUM) (unspec:SI [(const_int 0)] @@ -9965,7 +9965,7 @@ (define_insn "mve_vsbcq_m_<supf>v4si" (unspec:V4SI [(match_operand:V4SI 1 "s_register_operand" "w") (match_operand:V4SI 2 "s_register_operand" "w") (match_operand:V4SI 3 "s_register_operand" "w") - (match_operand:HI 4 "vpr_register_operand" "Up")] + (match_operand:V4BI 4 "vpr_register_operand" "Up")] VSBCQ_M)) (set (reg:SI VFPCC_REGNUM) (unspec:SI [(reg:SI VFPCC_REGNUM)] @@ -10469,7 +10469,7 @@ (define_insn "arm_vcx1q<a>_p_v16qi" (unspec:V16QI [(match_operand:SI 1 "const_int_coproc_operand" "i") (match_operand:V16QI 2 "register_operand" "0") (match_operand:SI 3 "const_int_mve_cde1_operand" "i") - (match_operand:HI 4 "vpr_register_operand" "Up")] + (match_operand:V16BI 4 "vpr_register_operand" "Up")] CDE_VCX))] "TARGET_CDE && TARGET_HAVE_MVE" "vpst\;vcx1<a>t\\tp%c1, %q0, #%c3" @@ -10483,7 +10483,7 @@ (define_insn "arm_vcx2q<a>_p_v16qi" (match_operand:V16QI 2 "register_operand" "0") (match_operand:V16QI 3 "register_operand" "t") (match_operand:SI 4 "const_int_mve_cde2_operand" "i") - (match_operand:HI 5 "vpr_register_operand" "Up")] + (match_operand:V16BI 5 "vpr_register_operand" "Up")] CDE_VCX))] "TARGET_CDE && TARGET_HAVE_MVE" "vpst\;vcx2<a>t\\tp%c1, %q0, %q3, #%c4" @@ -10498,7 +10498,7 @@ (define_insn "arm_vcx3q<a>_p_v16qi" (match_operand:V16QI 3 "register_operand" "t") (match_operand:V16QI 4 "register_operand" "t") (match_operand:SI 5 "const_int_mve_cde3_operand" "i") - (match_operand:HI 6 "vpr_register_operand" "Up")] + (match_operand:V16BI 6 "vpr_register_operand" "Up")] CDE_VCX))] "TARGET_CDE && TARGET_HAVE_MVE" "vpst\;vcx3<a>t\\tp%c1, %q0, %q3, %q4, #%c5" diff --git a/gcc/testsuite/gcc.target/arm/acle/cde-mve-full-assembly.c b/gcc/testsuite/gcc.target/arm/acle/cde-mve-full-assembly.c index 501cc84da10..77ea2866ad2 100644 --- a/gcc/testsuite/gcc.target/arm/acle/cde-mve-full-assembly.c +++ b/gcc/testsuite/gcc.target/arm/acle/cde-mve-full-assembly.c @@ -567,80 +567,80 @@ contain back references). */ /* ** test_cde_vcx1q_mfloat16x8_tintint: -** (?:vldr\.64 d0, \.L[0-9]*\n\tvldr\.64 d1, \.L[0-9]*\+8|vmsr P0, r2 @ movhi) -** (?:vldr\.64 d0, \.L[0-9]*\n\tvldr\.64 d1, \.L[0-9]*\+8|vmsr P0, r2 @ movhi) +** (?:vldr\.64 d0, \.L[0-9]*\n\tvldr\.64 d1, \.L[0-9]*\+8|vmsr P0, r2) +** (?:vldr\.64 d0, \.L[0-9]*\n\tvldr\.64 d1, \.L[0-9]*\+8|vmsr P0, r2) ** vpst ** vcx1t p0, q0, #32 ** bx lr */ /* ** test_cde_vcx1q_mfloat32x4_tintint: -** (?:vldr\.64 d0, \.L[0-9]*\n\tvldr\.64 d1, \.L[0-9]*\+8|vmsr P0, r2 @ movhi) -** (?:vldr\.64 d0, \.L[0-9]*\n\tvldr\.64 d1, \.L[0-9]*\+8|vmsr P0, r2 @ movhi) +** (?:vldr\.64 d0, \.L[0-9]*\n\tvldr\.64 d1, \.L[0-9]*\+8|vmsr P0, r2) +** (?:vldr\.64 d0, \.L[0-9]*\n\tvldr\.64 d1, \.L[0-9]*\+8|vmsr P0, r2) ** vpst ** vcx1t p0, q0, #32 ** bx lr */ /* ** test_cde_vcx1q_muint8x16_tintint: -** (?:vldr\.64 d0, \.L[0-9]*\n\tvldr\.64 d1, \.L[0-9]*\+8|vmsr P0, r2 @ movhi) -** (?:vldr\.64 d0, \.L[0-9]*\n\tvldr\.64 d1, \.L[0-9]*\+8|vmsr P0, r2 @ movhi) +** (?:vldr\.64 d0, \.L[0-9]*\n\tvldr\.64 d1, \.L[0-9]*\+8|vmsr P0, r2) +** (?:vldr\.64 d0, \.L[0-9]*\n\tvldr\.64 d1, \.L[0-9]*\+8|vmsr P0, r2) ** vpst ** vcx1t p0, q0, #32 ** bx lr */ /* ** test_cde_vcx1q_muint16x8_tintint: -** (?:vldr\.64 d0, \.L[0-9]*\n\tvldr\.64 d1, \.L[0-9]*\+8|vmsr P0, r2 @ movhi) -** (?:vldr\.64 d0, \.L[0-9]*\n\tvldr\.64 d1, \.L[0-9]*\+8|vmsr P0, r2 @ movhi) +** (?:vldr\.64 d0, \.L[0-9]*\n\tvldr\.64 d1, \.L[0-9]*\+8|vmsr P0, r2) +** (?:vldr\.64 d0, \.L[0-9]*\n\tvldr\.64 d1, \.L[0-9]*\+8|vmsr P0, r2) ** vpst ** vcx1t p0, q0, #32 ** bx lr */ /* ** test_cde_vcx1q_muint32x4_tintint: -** (?:vldr\.64 d0, \.L[0-9]*\n\tvldr\.64 d1, \.L[0-9]*\+8|vmsr P0, r2 @ movhi) -** (?:vldr\.64 d0, \.L[0-9]*\n\tvldr\.64 d1, \.L[0-9]*\+8|vmsr P0, r2 @ movhi) +** (?:vldr\.64 d0, \.L[0-9]*\n\tvldr\.64 d1, \.L[0-9]*\+8|vmsr P0, r2) +** (?:vldr\.64 d0, \.L[0-9]*\n\tvldr\.64 d1, \.L[0-9]*\+8|vmsr P0, r2) ** vpst ** vcx1t p0, q0, #32 ** bx lr */ /* ** test_cde_vcx1q_muint64x2_tintint: -** (?:vldr\.64 d0, \.L[0-9]*\n\tvldr\.64 d1, \.L[0-9]*\+8|vmsr P0, r2 @ movhi) -** (?:vldr\.64 d0, \.L[0-9]*\n\tvldr\.64 d1, \.L[0-9]*\+8|vmsr P0, r2 @ movhi) +** (?:vldr\.64 d0, \.L[0-9]*\n\tvldr\.64 d1, \.L[0-9]*\+8|vmsr P0, r2) +** (?:vldr\.64 d0, \.L[0-9]*\n\tvldr\.64 d1, \.L[0-9]*\+8|vmsr P0, r2) ** vpst ** vcx1t p0, q0, #32 ** bx lr */ /* ** test_cde_vcx1q_mint8x16_tintint: -** (?:vldr\.64 d0, \.L[0-9]*\n\tvldr\.64 d1, \.L[0-9]*\+8|vmsr P0, r2 @ movhi) -** (?:vldr\.64 d0, \.L[0-9]*\n\tvldr\.64 d1, \.L[0-9]*\+8|vmsr P0, r2 @ movhi) +** (?:vldr\.64 d0, \.L[0-9]*\n\tvldr\.64 d1, \.L[0-9]*\+8|vmsr P0, r2) +** (?:vldr\.64 d0, \.L[0-9]*\n\tvldr\.64 d1, \.L[0-9]*\+8|vmsr P0, r2) ** vpst ** vcx1t p0, q0, #32 ** bx lr */ /* ** test_cde_vcx1q_mint16x8_tintint: -** (?:vldr\.64 d0, \.L[0-9]*\n\tvldr\.64 d1, \.L[0-9]*\+8|vmsr P0, r2 @ movhi) -** (?:vldr\.64 d0, \.L[0-9]*\n\tvldr\.64 d1, \.L[0-9]*\+8|vmsr P0, r2 @ movhi) +** (?:vldr\.64 d0, \.L[0-9]*\n\tvldr\.64 d1, \.L[0-9]*\+8|vmsr P0, r2) +** (?:vldr\.64 d0, \.L[0-9]*\n\tvldr\.64 d1, \.L[0-9]*\+8|vmsr P0, r2) ** vpst ** vcx1t p0, q0, #32 ** bx lr */ /* ** test_cde_vcx1q_mint32x4_tintint: -** (?:vldr\.64 d0, \.L[0-9]*\n\tvldr\.64 d1, \.L[0-9]*\+8|vmsr P0, r2 @ movhi) -** (?:vldr\.64 d0, \.L[0-9]*\n\tvldr\.64 d1, \.L[0-9]*\+8|vmsr P0, r2 @ movhi) +** (?:vldr\.64 d0, \.L[0-9]*\n\tvldr\.64 d1, \.L[0-9]*\+8|vmsr P0, r2) +** (?:vldr\.64 d0, \.L[0-9]*\n\tvldr\.64 d1, \.L[0-9]*\+8|vmsr P0, r2) ** vpst ** vcx1t p0, q0, #32 ** bx lr */ /* ** test_cde_vcx1q_mint64x2_tintint: -** (?:vldr\.64 d0, \.L[0-9]*\n\tvldr\.64 d1, \.L[0-9]*\+8|vmsr P0, r2 @ movhi) -** (?:vldr\.64 d0, \.L[0-9]*\n\tvldr\.64 d1, \.L[0-9]*\+8|vmsr P0, r2 @ movhi) +** (?:vldr\.64 d0, \.L[0-9]*\n\tvldr\.64 d1, \.L[0-9]*\+8|vmsr P0, r2) +** (?:vldr\.64 d0, \.L[0-9]*\n\tvldr\.64 d1, \.L[0-9]*\+8|vmsr P0, r2) ** vpst ** vcx1t p0, q0, #32 ** bx lr @@ -649,80 +649,80 @@ /* ** test_cde_vcx1qa_mfloat16x8_tintint: -** (?:vldr\.64 d0, \.L[0-9]*\n\tvldr\.64 d1, \.L[0-9]*\+8|vmsr P0, r2 @ movhi) -** (?:vldr\.64 d0, \.L[0-9]*\n\tvldr\.64 d1, \.L[0-9]*\+8|vmsr P0, r2 @ movhi) +** (?:vldr\.64 d0, \.L[0-9]*\n\tvldr\.64 d1, \.L[0-9]*\+8|vmsr P0, r2) +** (?:vldr\.64 d0, \.L[0-9]*\n\tvldr\.64 d1, \.L[0-9]*\+8|vmsr P0, r2) ** vpst ** vcx1at p0, q0, #32 ** bx lr */ /* ** test_cde_vcx1qa_mfloat32x4_tintint: -** (?:vldr\.64 d0, \.L[0-9]*\n\tvldr\.64 d1, \.L[0-9]*\+8|vmsr P0, r2 @ movhi) -** (?:vldr\.64 d0, \.L[0-9]*\n\tvldr\.64 d1, \.L[0-9]*\+8|vmsr P0, r2 @ movhi) +** (?:vldr\.64 d0, \.L[0-9]*\n\tvldr\.64 d1, \.L[0-9]*\+8|vmsr P0, r2) +** (?:vldr\.64 d0, \.L[0-9]*\n\tvldr\.64 d1, \.L[0-9]*\+8|vmsr P0, r2) ** vpst ** vcx1at p0, q0, #32 ** bx lr */ /* ** test_cde_vcx1qa_muint8x16_tintint: -** (?:vldr\.64 d0, \.L[0-9]*\n\tvldr\.64 d1, \.L[0-9]*\+8|vmsr P0, r2 @ movhi) -** (?:vldr\.64 d0, \.L[0-9]*\n\tvldr\.64 d1, \.L[0-9]*\+8|vmsr P0, r2 @ movhi) +** (?:vldr\.64 d0, \.L[0-9]*\n\tvldr\.64 d1, \.L[0-9]*\+8|vmsr P0, r2) +** (?:vldr\.64 d0, \.L[0-9]*\n\tvldr\.64 d1, \.L[0-9]*\+8|vmsr P0, r2) ** vpst ** vcx1at p0, q0, #32 ** bx lr */ /* ** test_cde_vcx1qa_muint16x8_tintint: -** (?:vldr\.64 d0, \.L[0-9]*\n\tvldr\.64 d1, \.L[0-9]*\+8|vmsr P0, r2 @ movhi) -** (?:vldr\.64 d0, \.L[0-9]*\n\tvldr\.64 d1, \.L[0-9]*\+8|vmsr P0, r2 @ movhi) +** (?:vldr\.64 d0, \.L[0-9]*\n\tvldr\.64 d1, \.L[0-9]*\+8|vmsr P0, r2) +** (?:vldr\.64 d0, \.L[0-9]*\n\tvldr\.64 d1, \.L[0-9]*\+8|vmsr P0, r2) ** vpst ** vcx1at p0, q0, #32 ** bx lr */ /* ** test_cde_vcx1qa_muint32x4_tintint: -** (?:vldr\.64 d0, \.L[0-9]*\n\tvldr\.64 d1, \.L[0-9]*\+8|vmsr P0, r2 @ movhi) -** (?:vldr\.64 d0, \.L[0-9]*\n\tvldr\.64 d1, \.L[0-9]*\+8|vmsr P0, r2 @ movhi) +** (?:vldr\.64 d0, \.L[0-9]*\n\tvldr\.64 d1, \.L[0-9]*\+8|vmsr P0, r2) +** (?:vldr\.64 d0, \.L[0-9]*\n\tvldr\.64 d1, \.L[0-9]*\+8|vmsr P0, r2) ** vpst ** vcx1at p0, q0, #32 ** bx lr */ /* ** test_cde_vcx1qa_muint64x2_tintint: -** (?:vldr\.64 d0, \.L[0-9]*\n\tvldr\.64 d1, \.L[0-9]*\+8|vmsr P0, r2 @ movhi) -** (?:vldr\.64 d0, \.L[0-9]*\n\tvldr\.64 d1, \.L[0-9]*\+8|vmsr P0, r2 @ movhi) +** (?:vldr\.64 d0, \.L[0-9]*\n\tvldr\.64 d1, \.L[0-9]*\+8|vmsr P0, r2) +** (?:vldr\.64 d0, \.L[0-9]*\n\tvldr\.64 d1, \.L[0-9]*\+8|vmsr P0, r2) ** vpst ** vcx1at p0, q0, #32 ** bx lr */ /* ** test_cde_vcx1qa_mint8x16_tintint: -** (?:vldr\.64 d0, \.L[0-9]*\n\tvldr\.64 d1, \.L[0-9]*\+8|vmsr P0, r2 @ movhi) -** (?:vldr\.64 d0, \.L[0-9]*\n\tvldr\.64 d1, \.L[0-9]*\+8|vmsr P0, r2 @ movhi) +** (?:vldr\.64 d0, \.L[0-9]*\n\tvldr\.64 d1, \.L[0-9]*\+8|vmsr P0, r2) +** (?:vldr\.64 d0, \.L[0-9]*\n\tvldr\.64 d1, \.L[0-9]*\+8|vmsr P0, r2) ** vpst ** vcx1at p0, q0, #32 ** bx lr */ /* ** test_cde_vcx1qa_mint16x8_tintint: -** (?:vldr\.64 d0, \.L[0-9]*\n\tvldr\.64 d1, \.L[0-9]*\+8|vmsr P0, r2 @ movhi) -** (?:vldr\.64 d0, \.L[0-9]*\n\tvldr\.64 d1, \.L[0-9]*\+8|vmsr P0, r2 @ movhi) +** (?:vldr\.64 d0, \.L[0-9]*\n\tvldr\.64 d1, \.L[0-9]*\+8|vmsr P0, r2) +** (?:vldr\.64 d0, \.L[0-9]*\n\tvldr\.64 d1, \.L[0-9]*\+8|vmsr P0, r2) ** vpst ** vcx1at p0, q0, #32 ** bx lr */ /* ** test_cde_vcx1qa_mint32x4_tintint: -** (?:vldr\.64 d0, \.L[0-9]*\n\tvldr\.64 d1, \.L[0-9]*\+8|vmsr P0, r2 @ movhi) -** (?:vldr\.64 d0, \.L[0-9]*\n\tvldr\.64 d1, \.L[0-9]*\+8|vmsr P0, r2 @ movhi) +** (?:vldr\.64 d0, \.L[0-9]*\n\tvldr\.64 d1, \.L[0-9]*\+8|vmsr P0, r2) +** (?:vldr\.64 d0, \.L[0-9]*\n\tvldr\.64 d1, \.L[0-9]*\+8|vmsr P0, r2) ** vpst ** vcx1at p0, q0, #32 ** bx lr */ /* ** test_cde_vcx1qa_mint64x2_tintint: -** (?:vldr\.64 d0, \.L[0-9]*\n\tvldr\.64 d1, \.L[0-9]*\+8|vmsr P0, r2 @ movhi) -** (?:vldr\.64 d0, \.L[0-9]*\n\tvldr\.64 d1, \.L[0-9]*\+8|vmsr P0, r2 @ movhi) +** (?:vldr\.64 d0, \.L[0-9]*\n\tvldr\.64 d1, \.L[0-9]*\+8|vmsr P0, r2) +** (?:vldr\.64 d0, \.L[0-9]*\n\tvldr\.64 d1, \.L[0-9]*\+8|vmsr P0, r2) ** vpst ** vcx1at p0, q0, #32 ** bx lr @@ -731,8 +731,8 @@ /* ** test_cde_vcx2q_mfloat16x8_tuint16x8_tint: -** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r1 @ movhi) -** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r1 @ movhi) +** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r1) +** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r1) ** vpst ** vcx2t p0, (q[0-7]), q0, #32 ** vmov q0, \1([[:space:]]+@ [^\n]*)? @@ -740,8 +740,8 @@ */ /* ** test_cde_vcx2q_mfloat16x8_tfloat32x4_tint: -** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r1 @ movhi) -** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r1 @ movhi) +** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r1) +** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r1) ** vpst ** vcx2t p0, (q[0-7]), q0, #32 ** vmov q0, \1([[:space:]]+@ [^\n]*)? @@ -749,8 +749,8 @@ */ /* ** test_cde_vcx2q_mfloat32x4_tuint8x16_tint: -** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r1 @ movhi) -** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r1 @ movhi) +** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r1) +** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r1) ** vpst ** vcx2t p0, (q[0-7]), q0, #32 ** vmov q0, \1([[:space:]]+@ [^\n]*)? @@ -758,8 +758,8 @@ */ /* ** test_cde_vcx2q_mint64x2_tuint8x16_tint: -** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r1 @ movhi) -** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r1 @ movhi) +** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r1) +** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r1) ** vpst ** vcx2t p0, (q[0-7]), q0, #32 ** vmov q0, \1([[:space:]]+@ [^\n]*)? @@ -767,8 +767,8 @@ */ /* ** test_cde_vcx2q_mint8x16_tuint8x16_tint: -** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r1 @ movhi) -** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r1 @ movhi) +** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r1) +** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r1) ** vpst ** vcx2t p0, (q[0-7]), q0, #32 ** vmov q0, \1([[:space:]]+@ [^\n]*)? @@ -776,8 +776,8 @@ */ /* ** test_cde_vcx2q_muint16x8_tuint8x16_tint: -** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r1 @ movhi) -** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r1 @ movhi) +** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r1) +** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r1) ** vpst ** vcx2t p0, (q[0-7]), q0, #32 ** vmov q0, \1([[:space:]]+@ [^\n]*)? @@ -785,8 +785,8 @@ */ /* ** test_cde_vcx2q_muint8x16_tint64x2_tint: -** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r1 @ movhi) -** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r1 @ movhi) +** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r1) +** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r1) ** vpst ** vcx2t p0, (q[0-7]), q0, #32 ** vmov q0, \1([[:space:]]+@ [^\n]*)? @@ -794,8 +794,8 @@ */ /* ** test_cde_vcx2q_muint8x16_tint8x16_tint: -** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r1 @ movhi) -** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r1 @ movhi) +** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r1) +** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r1) ** vpst ** vcx2t p0, (q[0-7]), q0, #32 ** vmov q0, \1([[:space:]]+@ [^\n]*)? @@ -803,8 +803,8 @@ */ /* ** test_cde_vcx2q_muint8x16_tuint16x8_tint: -** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r1 @ movhi) -** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r1 @ movhi) +** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r1) +** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r1) ** vpst ** vcx2t p0, (q[0-7]), q0, #32 ** vmov q0, \1([[:space:]]+@ [^\n]*)? @@ -812,8 +812,8 @@ */ /* ** test_cde_vcx2q_muint8x16_tuint8x16_tint: -** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r1 @ movhi) -** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r1 @ movhi) +** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r1) +** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r1) ** vpst ** vcx2t p0, (q[0-7]), q0, #32 ** vmov q0, \1([[:space:]]+@ [^\n]*)? @@ -823,8 +823,8 @@ /* ** test_cde_vcx2qa_mfloat16x8_tuint16x8_tint: -** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r1 @ movhi) -** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r1 @ movhi) +** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r1) +** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r1) ** vpst ** vcx2at p0, (q[0-7]), q0, #32 ** vmov q0, \1([[:space:]]+@ [^\n]*)? @@ -832,8 +832,8 @@ */ /* ** test_cde_vcx2qa_mfloat16x8_tfloat32x4_tint: -** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r1 @ movhi) -** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r1 @ movhi) +** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r1) +** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r1) ** vpst ** vcx2at p0, (q[0-7]), q0, #32 ** vmov q0, \1([[:space:]]+@ [^\n]*)? @@ -841,8 +841,8 @@ */ /* ** test_cde_vcx2qa_mfloat32x4_tuint8x16_tint: -** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r1 @ movhi) -** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r1 @ movhi) +** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r1) +** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r1) ** vpst ** vcx2at p0, (q[0-7]), q0, #32 ** vmov q0, \1([[:space:]]+@ [^\n]*)? @@ -850,8 +850,8 @@ */ /* ** test_cde_vcx2qa_mint64x2_tuint8x16_tint: -** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r1 @ movhi) -** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r1 @ movhi) +** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r1) +** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r1) ** vpst ** vcx2at p0, (q[0-7]), q0, #32 ** vmov q0, \1([[:space:]]+@ [^\n]*)? @@ -859,8 +859,8 @@ */ /* ** test_cde_vcx2qa_mint8x16_tuint8x16_tint: -** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r1 @ movhi) -** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r1 @ movhi) +** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r1) +** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r1) ** vpst ** vcx2at p0, (q[0-7]), q0, #32 ** vmov q0, \1([[:space:]]+@ [^\n]*)? @@ -868,8 +868,8 @@ */ /* ** test_cde_vcx2qa_muint16x8_tuint8x16_tint: -** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r1 @ movhi) -** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r1 @ movhi) +** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r1) +** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r1) ** vpst ** vcx2at p0, (q[0-7]), q0, #32 ** vmov q0, \1([[:space:]]+@ [^\n]*)? @@ -877,8 +877,8 @@ */ /* ** test_cde_vcx2qa_muint8x16_tint64x2_tint: -** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r1 @ movhi) -** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r1 @ movhi) +** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r1) +** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r1) ** vpst ** vcx2at p0, (q[0-7]), q0, #32 ** vmov q0, \1([[:space:]]+@ [^\n]*)? @@ -886,8 +886,8 @@ */ /* ** test_cde_vcx2qa_muint8x16_tint8x16_tint: -** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r1 @ movhi) -** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r1 @ movhi) +** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r1) +** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r1) ** vpst ** vcx2at p0, (q[0-7]), q0, #32 ** vmov q0, \1([[:space:]]+@ [^\n]*)? @@ -895,8 +895,8 @@ */ /* ** test_cde_vcx2qa_muint8x16_tuint16x8_tint: -** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r1 @ movhi) -** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r1 @ movhi) +** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r1) +** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r1) ** vpst ** vcx2at p0, (q[0-7]), q0, #32 ** vmov q0, \1([[:space:]]+@ [^\n]*)? @@ -904,8 +904,8 @@ */ /* ** test_cde_vcx2qa_muint8x16_tuint8x16_tint: -** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r1 @ movhi) -** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r1 @ movhi) +** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r1) +** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r1) ** vpst ** vcx2at p0, (q[0-7]), q0, #32 ** vmov q0, \1([[:space:]]+@ [^\n]*)? @@ -915,8 +915,8 @@ /* ** test_cde_vcx3q_muint8x16_tuint8x16_tuint8x16_t: -** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r0 @ movhi) -** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r0 @ movhi) +** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r0) +** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r0) ** vpst ** vcx3t p0, (q[0-7]), q0, q1, #15 ** vmov q0, \1([[:space:]]+@ [^\n]*)? @@ -924,8 +924,8 @@ */ /* ** test_cde_vcx3q_mfloat16x8_tfloat16x8_tfloat16x8_t: -** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r0 @ movhi) -** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r0 @ movhi) +** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r0) +** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r0) ** vpst ** vcx3t p0, (q[0-7]), q0, q1, #15 ** vmov q0, \1([[:space:]]+@ [^\n]*)? @@ -933,8 +933,8 @@ */ /* ** test_cde_vcx3q_mfloat32x4_tuint64x2_tfloat16x8_t: -** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r0 @ movhi) -** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r0 @ movhi) +** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r0) +** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r0) ** vpst ** vcx3t p0, (q[0-7]), q0, q1, #15 ** vmov q0, \1([[:space:]]+@ [^\n]*)? @@ -942,8 +942,8 @@ */ /* ** test_cde_vcx3q_muint16x8_tuint8x16_tuint8x16_t: -** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r0 @ movhi) -** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r0 @ movhi) +** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r0) +** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r0) ** vpst ** vcx3t p0, (q[0-7]), q0, q1, #15 ** vmov q0, \1([[:space:]]+@ [^\n]*)? @@ -951,8 +951,8 @@ */ /* ** test_cde_vcx3q_muint8x16_tuint16x8_tuint8x16_t: -** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r0 @ movhi) -** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r0 @ movhi) +** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r0) +** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r0) ** vpst ** vcx3t p0, (q[0-7]), q0, q1, #15 ** vmov q0, \1([[:space:]]+@ [^\n]*)? @@ -960,8 +960,8 @@ */ /* ** test_cde_vcx3q_muint8x16_tuint8x16_tuint16x8_t: -** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r0 @ movhi) -** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r0 @ movhi) +** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r0) +** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r0) ** vpst ** vcx3t p0, (q[0-7]), q0, q1, #15 ** vmov q0, \1([[:space:]]+@ [^\n]*)? @@ -969,8 +969,8 @@ */ /* ** test_cde_vcx3q_mint8x16_tuint8x16_tuint8x16_t: -** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r0 @ movhi) -** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r0 @ movhi) +** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r0) +** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r0) ** vpst ** vcx3t p0, (q[0-7]), q0, q1, #15 ** vmov q0, \1([[:space:]]+@ [^\n]*)? @@ -978,8 +978,8 @@ */ /* ** test_cde_vcx3q_muint8x16_tint8x16_tuint8x16_t: -** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r0 @ movhi) -** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r0 @ movhi) +** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r0) +** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r0) ** vpst ** vcx3t p0, (q[0-7]), q0, q1, #15 ** vmov q0, \1([[:space:]]+@ [^\n]*)? @@ -987,8 +987,8 @@ */ /* ** test_cde_vcx3q_muint8x16_tuint8x16_tint8x16_t: -** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r0 @ movhi) -** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r0 @ movhi) +** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r0) +** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r0) ** vpst ** vcx3t p0, (q[0-7]), q0, q1, #15 ** vmov q0, \1([[:space:]]+@ [^\n]*)? @@ -996,8 +996,8 @@ */ /* ** test_cde_vcx3q_mint64x2_tuint8x16_tuint8x16_t: -** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r0 @ movhi) -** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r0 @ movhi) +** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r0) +** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r0) ** vpst ** vcx3t p0, (q[0-7]), q0, q1, #15 ** vmov q0, \1([[:space:]]+@ [^\n]*)? @@ -1005,8 +1005,8 @@ */ /* ** test_cde_vcx3q_muint8x16_tint64x2_tuint8x16_t: -** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r0 @ movhi) -** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r0 @ movhi) +** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r0) +** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r0) ** vpst ** vcx3t p0, (q[0-7]), q0, q1, #15 ** vmov q0, \1([[:space:]]+@ [^\n]*)? @@ -1014,8 +1014,8 @@ */ /* ** test_cde_vcx3q_muint8x16_tuint8x16_tint64x2_t: -** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r0 @ movhi) -** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r0 @ movhi) +** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r0) +** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r0) ** vpst ** vcx3t p0, (q[0-7]), q0, q1, #15 ** vmov q0, \1([[:space:]]+@ [^\n]*)? @@ -1023,8 +1023,8 @@ */ /* ** test_cde_vcx3q_muint8x16_tint64x2_tint64x2_t: -** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r0 @ movhi) -** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r0 @ movhi) +** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r0) +** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r0) ** vpst ** vcx3t p0, (q[0-7]), q0, q1, #15 ** vmov q0, \1([[:space:]]+@ [^\n]*)? @@ -1034,8 +1034,8 @@ /* ** test_cde_vcx3qa_muint8x16_tuint8x16_tuint8x16_t: -** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r0 @ movhi) -** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r0 @ movhi) +** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r0) +** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r0) ** vpst ** vcx3at p0, (q[0-7]), q0, q1, #15 ** vmov q0, \1([[:space:]]+@ [^\n]*)? @@ -1043,8 +1043,8 @@ */ /* ** test_cde_vcx3qa_mfloat16x8_tfloat16x8_tfloat16x8_t: -** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r0 @ movhi) -** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r0 @ movhi) +** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r0) +** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r0) ** vpst ** vcx3at p0, (q[0-7]), q0, q1, #15 ** vmov q0, \1([[:space:]]+@ [^\n]*)? @@ -1052,8 +1052,8 @@ */ /* ** test_cde_vcx3qa_mfloat32x4_tuint64x2_tfloat16x8_t: -** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r0 @ movhi) -** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r0 @ movhi) +** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r0) +** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r0) ** vpst ** vcx3at p0, (q[0-7]), q0, q1, #15 ** vmov q0, \1([[:space:]]+@ [^\n]*)? @@ -1061,8 +1061,8 @@ */ /* ** test_cde_vcx3qa_muint16x8_tuint8x16_tuint8x16_t: -** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r0 @ movhi) -** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r0 @ movhi) +** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r0) +** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r0) ** vpst ** vcx3at p0, (q[0-7]), q0, q1, #15 ** vmov q0, \1([[:space:]]+@ [^\n]*)? @@ -1070,8 +1070,8 @@ */ /* ** test_cde_vcx3qa_muint8x16_tuint16x8_tuint8x16_t: -** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r0 @ movhi) -** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r0 @ movhi) +** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r0) +** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r0) ** vpst ** vcx3at p0, (q[0-7]), q0, q1, #15 ** vmov q0, \1([[:space:]]+@ [^\n]*)? @@ -1079,8 +1079,8 @@ */ /* ** test_cde_vcx3qa_muint8x16_tuint8x16_tuint16x8_t: -** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r0 @ movhi) -** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r0 @ movhi) +** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r0) +** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r0) ** vpst ** vcx3at p0, (q[0-7]), q0, q1, #15 ** vmov q0, \1([[:space:]]+@ [^\n]*)? @@ -1088,8 +1088,8 @@ */ /* ** test_cde_vcx3qa_mint8x16_tuint8x16_tuint8x16_t: -** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r0 @ movhi) -** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r0 @ movhi) +** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r0) +** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r0) ** vpst ** vcx3at p0, (q[0-7]), q0, q1, #15 ** vmov q0, \1([[:space:]]+@ [^\n]*)? @@ -1097,8 +1097,8 @@ */ /* ** test_cde_vcx3qa_muint8x16_tint8x16_tuint8x16_t: -** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r0 @ movhi) -** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r0 @ movhi) +** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r0) +** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r0) ** vpst ** vcx3at p0, (q[0-7]), q0, q1, #15 ** vmov q0, \1([[:space:]]+@ [^\n]*)? @@ -1106,8 +1106,8 @@ */ /* ** test_cde_vcx3qa_muint8x16_tuint8x16_tint8x16_t: -** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r0 @ movhi) -** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r0 @ movhi) +** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r0) +** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r0) ** vpst ** vcx3at p0, (q[0-7]), q0, q1, #15 ** vmov q0, \1([[:space:]]+@ [^\n]*)? @@ -1115,8 +1115,8 @@ */ /* ** test_cde_vcx3qa_mint64x2_tuint8x16_tuint8x16_t: -** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r0 @ movhi) -** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r0 @ movhi) +** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r0) +** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r0) ** vpst ** vcx3at p0, (q[0-7]), q0, q1, #15 ** vmov q0, \1([[:space:]]+@ [^\n]*)? @@ -1124,8 +1124,8 @@ */ /* ** test_cde_vcx3qa_muint8x16_tint64x2_tuint8x16_t: -** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r0 @ movhi) -** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r0 @ movhi) +** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r0) +** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r0) ** vpst ** vcx3at p0, (q[0-7]), q0, q1, #15 ** vmov q0, \1([[:space:]]+@ [^\n]*)? @@ -1133,8 +1133,8 @@ */ /* ** test_cde_vcx3qa_muint8x16_tuint8x16_tint64x2_t: -** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r0 @ movhi) -** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r0 @ movhi) +** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r0) +** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r0) ** vpst ** vcx3at p0, (q[0-7]), q0, q1, #15 ** vmov q0, \1([[:space:]]+@ [^\n]*)? @@ -1142,8 +1142,8 @@ */ /* ** test_cde_vcx3qa_muint8x16_tint64x2_tint64x2_t: -** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r0 @ movhi) -** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r0 @ movhi) +** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r0) +** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r0) ** vpst ** vcx3at p0, (q[0-7]), q0, q1, #15 ** vmov q0, \1([[:space:]]+@ [^\n]*)? -- 2.25.1 ^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH 13/13] arm: Convert more MVE/CDE builtins to predicate qualifiers 2021-09-07 9:21 ` [PATCH 13/13] arm: Convert more MVE/CDE " Christophe Lyon @ 2021-10-11 14:21 ` Richard Sandiford 0 siblings, 0 replies; 9+ messages in thread From: Richard Sandiford @ 2021-10-11 14:21 UTC (permalink / raw) To: Christophe Lyon via Gcc-patches Christophe Lyon via Gcc-patches <gcc-patches@gcc.gnu.org> writes: > This patch covers a few non-load/store builtins where we do not use > the <mode> iterator and thus we cannot use <MVE_vpred>. > > We need to update the expected code in cde-mve-full-assembly.c because > we now use mve_movv16qi instead of movhi to generate the vmsr > instruction. > > 2021-09-02 Christophe Lyon <christophe.lyon@foss.st.com> > > gcc/ > PR target/100757 > PR target/101325 > * config/arm/arm-builtins.c (CX_UNARY_UNONE_QUALIFIERS): Use > predicate. > (CX_BINARY_UNONE_QUALIFIERS): Likewise. > (CX_TERNARY_UNONE_QUALIFIERS): Likewise. > (TERNOP_NONE_NONE_NONE_UNONE_QUALIFIERS): Delete. > (QUADOP_NONE_NONE_NONE_NONE_UNONE_QUALIFIERS): Delete. > (QUADOP_UNONE_UNONE_UNONE_UNONE_UNONE_QUALIFIERS): Delete. > * config/arm/arm_mve_builtins.def: Use predicated qualifiers. > * config/arm/mve.md: Use VxBI instead of HI. > > gcc/testsuite/ > * gcc.target/arm/acle/cde-mve-full-assembly.c: Remove expected '@ movhi'. OK, thanks. Richard > diff --git a/gcc/config/arm/arm-builtins.c b/gcc/config/arm/arm-builtins.c > index e58580bb828..d725458f1ad 100644 > --- a/gcc/config/arm/arm-builtins.c > +++ b/gcc/config/arm/arm-builtins.c > @@ -344,7 +344,7 @@ static enum arm_type_qualifiers > arm_cx_unary_unone_qualifiers[SIMD_MAX_BUILTIN_ARGS] > = { qualifier_none, qualifier_immediate, qualifier_none, > qualifier_unsigned_immediate, > - qualifier_unsigned }; > + qualifier_predicate }; > #define CX_UNARY_UNONE_QUALIFIERS (arm_cx_unary_unone_qualifiers) > > /* T (immediate, T, T, unsigned immediate). */ > @@ -353,7 +353,7 @@ arm_cx_binary_unone_qualifiers[SIMD_MAX_BUILTIN_ARGS] > = { qualifier_none, qualifier_immediate, > qualifier_none, qualifier_none, > qualifier_unsigned_immediate, > - qualifier_unsigned }; > + qualifier_predicate }; > #define CX_BINARY_UNONE_QUALIFIERS (arm_cx_binary_unone_qualifiers) > > /* T (immediate, T, T, T, unsigned immediate). */ > @@ -362,7 +362,7 @@ arm_cx_ternary_unone_qualifiers[SIMD_MAX_BUILTIN_ARGS] > = { qualifier_none, qualifier_immediate, > qualifier_none, qualifier_none, qualifier_none, > qualifier_unsigned_immediate, > - qualifier_unsigned }; > + qualifier_predicate }; > #define CX_TERNARY_UNONE_QUALIFIERS (arm_cx_ternary_unone_qualifiers) > > /* The first argument (return type) of a store should be void type, > @@ -558,12 +558,6 @@ arm_ternop_none_none_none_imm_qualifiers[SIMD_MAX_BUILTIN_ARGS] > #define TERNOP_NONE_NONE_NONE_IMM_QUALIFIERS \ > (arm_ternop_none_none_none_imm_qualifiers) > > -static enum arm_type_qualifiers > -arm_ternop_none_none_none_unone_qualifiers[SIMD_MAX_BUILTIN_ARGS] > - = { qualifier_none, qualifier_none, qualifier_none, qualifier_unsigned }; > -#define TERNOP_NONE_NONE_NONE_UNONE_QUALIFIERS \ > - (arm_ternop_none_none_none_unone_qualifiers) > - > static enum arm_type_qualifiers > arm_ternop_none_none_none_pred_qualifiers[SIMD_MAX_BUILTIN_ARGS] > = { qualifier_none, qualifier_none, qualifier_none, qualifier_predicate }; > @@ -616,13 +610,6 @@ arm_quadop_unone_unone_none_none_pred_qualifiers[SIMD_MAX_BUILTIN_ARGS] > #define QUADOP_UNONE_UNONE_NONE_NONE_PRED_QUALIFIERS \ > (arm_quadop_unone_unone_none_none_pred_qualifiers) > > -static enum arm_type_qualifiers > -arm_quadop_none_none_none_none_unone_qualifiers[SIMD_MAX_BUILTIN_ARGS] > - = { qualifier_none, qualifier_none, qualifier_none, qualifier_none, > - qualifier_unsigned }; > -#define QUADOP_NONE_NONE_NONE_NONE_UNONE_QUALIFIERS \ > - (arm_quadop_none_none_none_none_unone_qualifiers) > - > static enum arm_type_qualifiers > arm_quadop_none_none_none_none_pred_qualifiers[SIMD_MAX_BUILTIN_ARGS] > = { qualifier_none, qualifier_none, qualifier_none, qualifier_none, > @@ -637,13 +624,6 @@ arm_quadop_none_none_none_imm_pred_qualifiers[SIMD_MAX_BUILTIN_ARGS] > #define QUADOP_NONE_NONE_NONE_IMM_PRED_QUALIFIERS \ > (arm_quadop_none_none_none_imm_pred_qualifiers) > > -static enum arm_type_qualifiers > -arm_quadop_unone_unone_unone_unone_unone_qualifiers[SIMD_MAX_BUILTIN_ARGS] > - = { qualifier_unsigned, qualifier_unsigned, qualifier_unsigned, > - qualifier_unsigned, qualifier_unsigned }; > -#define QUADOP_UNONE_UNONE_UNONE_UNONE_UNONE_QUALIFIERS \ > - (arm_quadop_unone_unone_unone_unone_unone_qualifiers) > - > static enum arm_type_qualifiers > arm_quadop_unone_unone_unone_unone_pred_qualifiers[SIMD_MAX_BUILTIN_ARGS] > = { qualifier_unsigned, qualifier_unsigned, qualifier_unsigned, > diff --git a/gcc/config/arm/arm_mve_builtins.def b/gcc/config/arm/arm_mve_builtins.def > index bb79edf83ca..0fb53d866ec 100644 > --- a/gcc/config/arm/arm_mve_builtins.def > +++ b/gcc/config/arm/arm_mve_builtins.def > @@ -87,8 +87,8 @@ VAR4 (BINOP_UNONE_UNONE_UNONE, vcreateq_u, v16qi, v8hi, v4si, v2di) > VAR4 (BINOP_NONE_UNONE_UNONE, vcreateq_s, v16qi, v8hi, v4si, v2di) > VAR3 (BINOP_UNONE_UNONE_IMM, vshrq_n_u, v16qi, v8hi, v4si) > VAR3 (BINOP_NONE_NONE_IMM, vshrq_n_s, v16qi, v8hi, v4si) > -VAR1 (BINOP_NONE_NONE_UNONE, vaddlvq_p_s, v4si) > -VAR1 (BINOP_UNONE_UNONE_UNONE, vaddlvq_p_u, v4si) > +VAR1 (BINOP_NONE_NONE_PRED, vaddlvq_p_s, v4si) > +VAR1 (BINOP_UNONE_UNONE_PRED, vaddlvq_p_u, v4si) > VAR3 (BINOP_PRED_NONE_NONE, vcmpneq_, v16qi, v8hi, v4si) > VAR3 (BINOP_NONE_NONE_NONE, vshlq_s, v16qi, v8hi, v4si) > VAR3 (BINOP_UNONE_UNONE_NONE, vshlq_u, v16qi, v8hi, v4si) > @@ -465,20 +465,20 @@ VAR2 (TERNOP_NONE_NONE_NONE_IMM, vqshrnbq_n_s, v8hi, v4si) > VAR2 (TERNOP_NONE_NONE_NONE_IMM, vqrshrntq_n_s, v8hi, v4si) > VAR2 (TERNOP_NONE_NONE_IMM_PRED, vorrq_m_n_s, v8hi, v4si) > VAR2 (TERNOP_NONE_NONE_IMM_PRED, vmvnq_m_n_s, v8hi, v4si) > -VAR1 (TERNOP_UNONE_UNONE_UNONE_UNONE, vrmlaldavhq_p_u, v4si) > -VAR1 (TERNOP_UNONE_UNONE_UNONE_UNONE, vrev16q_m_u, v16qi) > -VAR1 (TERNOP_UNONE_UNONE_UNONE_UNONE, vaddlvaq_p_u, v4si) > -VAR1 (TERNOP_NONE_NONE_NONE_UNONE, vrmlsldavhxq_p_s, v4si) > -VAR1 (TERNOP_NONE_NONE_NONE_UNONE, vrmlsldavhq_p_s, v4si) > -VAR1 (TERNOP_NONE_NONE_NONE_UNONE, vrmlaldavhxq_p_s, v4si) > -VAR1 (TERNOP_NONE_NONE_NONE_UNONE, vrmlaldavhq_p_s, v4si) > -VAR1 (TERNOP_NONE_NONE_NONE_UNONE, vrev32q_m_f, v8hf) > -VAR1 (TERNOP_NONE_NONE_NONE_UNONE, vrev16q_m_s, v16qi) > -VAR1 (TERNOP_NONE_NONE_NONE_UNONE, vcvttq_m_f32_f16, v4sf) > -VAR1 (TERNOP_NONE_NONE_NONE_UNONE, vcvttq_m_f16_f32, v8hf) > -VAR1 (TERNOP_NONE_NONE_NONE_UNONE, vcvtbq_m_f32_f16, v4sf) > -VAR1 (TERNOP_NONE_NONE_NONE_UNONE, vcvtbq_m_f16_f32, v8hf) > -VAR1 (TERNOP_NONE_NONE_NONE_UNONE, vaddlvaq_p_s, v4si) > +VAR1 (TERNOP_UNONE_UNONE_UNONE_PRED, vrmlaldavhq_p_u, v4si) > +VAR1 (TERNOP_UNONE_UNONE_UNONE_PRED, vrev16q_m_u, v16qi) > +VAR1 (TERNOP_UNONE_UNONE_UNONE_PRED, vaddlvaq_p_u, v4si) > +VAR1 (TERNOP_NONE_NONE_NONE_PRED, vrmlsldavhxq_p_s, v4si) > +VAR1 (TERNOP_NONE_NONE_NONE_PRED, vrmlsldavhq_p_s, v4si) > +VAR1 (TERNOP_NONE_NONE_NONE_PRED, vrmlaldavhxq_p_s, v4si) > +VAR1 (TERNOP_NONE_NONE_NONE_PRED, vrmlaldavhq_p_s, v4si) > +VAR1 (TERNOP_NONE_NONE_NONE_PRED, vrev32q_m_f, v8hf) > +VAR1 (TERNOP_NONE_NONE_NONE_PRED, vrev16q_m_s, v16qi) > +VAR1 (TERNOP_NONE_NONE_NONE_PRED, vcvttq_m_f32_f16, v4sf) > +VAR1 (TERNOP_NONE_NONE_NONE_PRED, vcvttq_m_f16_f32, v8hf) > +VAR1 (TERNOP_NONE_NONE_NONE_PRED, vcvtbq_m_f32_f16, v4sf) > +VAR1 (TERNOP_NONE_NONE_NONE_PRED, vcvtbq_m_f16_f32, v8hf) > +VAR1 (TERNOP_NONE_NONE_NONE_PRED, vaddlvaq_p_s, v4si) > VAR1 (TERNOP_NONE_NONE_NONE_NONE, vrmlsldavhaxq_s, v4si) > VAR1 (TERNOP_NONE_NONE_NONE_NONE, vrmlsldavhaq_s, v4si) > VAR1 (TERNOP_NONE_NONE_NONE_NONE, vrmlaldavhaxq_s, v4si) > @@ -629,11 +629,11 @@ VAR2 (QUADOP_NONE_NONE_NONE_IMM_PRED, vqshrntq_m_n_s, v8hi, v4si) > VAR2 (QUADOP_NONE_NONE_NONE_IMM_PRED, vqshrnbq_m_n_s, v8hi, v4si) > VAR2 (QUADOP_NONE_NONE_NONE_IMM_PRED, vqrshrntq_m_n_s, v8hi, v4si) > VAR2 (QUADOP_NONE_NONE_NONE_IMM_PRED, vqrshrnbq_m_n_s, v8hi, v4si) > -VAR1 (QUADOP_UNONE_UNONE_UNONE_UNONE_UNONE, vrmlaldavhaq_p_u, v4si) > -VAR1 (QUADOP_NONE_NONE_NONE_NONE_UNONE, vrmlsldavhaxq_p_s, v4si) > -VAR1 (QUADOP_NONE_NONE_NONE_NONE_UNONE, vrmlsldavhaq_p_s, v4si) > -VAR1 (QUADOP_NONE_NONE_NONE_NONE_UNONE, vrmlaldavhaxq_p_s, v4si) > -VAR1 (QUADOP_NONE_NONE_NONE_NONE_UNONE, vrmlaldavhaq_p_s, v4si) > +VAR1 (QUADOP_UNONE_UNONE_UNONE_UNONE_PRED, vrmlaldavhaq_p_u, v4si) > +VAR1 (QUADOP_NONE_NONE_NONE_NONE_PRED, vrmlsldavhaxq_p_s, v4si) > +VAR1 (QUADOP_NONE_NONE_NONE_NONE_PRED, vrmlsldavhaq_p_s, v4si) > +VAR1 (QUADOP_NONE_NONE_NONE_NONE_PRED, vrmlaldavhaxq_p_s, v4si) > +VAR1 (QUADOP_NONE_NONE_NONE_NONE_PRED, vrmlaldavhaq_p_s, v4si) > VAR2 (QUADOP_UNONE_UNONE_NONE_IMM_PRED, vcvtq_m_n_from_f_u, v8hi, v4si) > VAR2 (QUADOP_NONE_NONE_NONE_IMM_PRED, vcvtq_m_n_from_f_s, v8hi, v4si) > VAR2 (QUADOP_NONE_NONE_NONE_NONE_PRED, vbrsrq_m_n_f, v8hf, v4sf) > @@ -845,14 +845,14 @@ VAR1 (BINOP_NONE_NONE_NONE, vsbciq_s, v4si) > VAR1 (BINOP_UNONE_UNONE_UNONE, vsbciq_u, v4si) > VAR1 (BINOP_NONE_NONE_NONE, vsbcq_s, v4si) > VAR1 (BINOP_UNONE_UNONE_UNONE, vsbcq_u, v4si) > -VAR1 (QUADOP_NONE_NONE_NONE_NONE_UNONE, vadciq_m_s, v4si) > -VAR1 (QUADOP_UNONE_UNONE_UNONE_UNONE_UNONE, vadciq_m_u, v4si) > -VAR1 (QUADOP_NONE_NONE_NONE_NONE_UNONE, vadcq_m_s, v4si) > -VAR1 (QUADOP_UNONE_UNONE_UNONE_UNONE_UNONE, vadcq_m_u, v4si) > -VAR1 (QUADOP_NONE_NONE_NONE_NONE_UNONE, vsbciq_m_s, v4si) > -VAR1 (QUADOP_UNONE_UNONE_UNONE_UNONE_UNONE, vsbciq_m_u, v4si) > -VAR1 (QUADOP_NONE_NONE_NONE_NONE_UNONE, vsbcq_m_s, v4si) > -VAR1 (QUADOP_UNONE_UNONE_UNONE_UNONE_UNONE, vsbcq_m_u, v4si) > +VAR1 (QUADOP_NONE_NONE_NONE_NONE_PRED, vadciq_m_s, v4si) > +VAR1 (QUADOP_UNONE_UNONE_UNONE_UNONE_PRED, vadciq_m_u, v4si) > +VAR1 (QUADOP_NONE_NONE_NONE_NONE_PRED, vadcq_m_s, v4si) > +VAR1 (QUADOP_UNONE_UNONE_UNONE_UNONE_PRED, vadcq_m_u, v4si) > +VAR1 (QUADOP_NONE_NONE_NONE_NONE_PRED, vsbciq_m_s, v4si) > +VAR1 (QUADOP_UNONE_UNONE_UNONE_UNONE_PRED, vsbciq_m_u, v4si) > +VAR1 (QUADOP_NONE_NONE_NONE_NONE_PRED, vsbcq_m_s, v4si) > +VAR1 (QUADOP_UNONE_UNONE_UNONE_UNONE_PRED, vsbcq_m_u, v4si) > VAR5 (STORE1, vst2q, v16qi, v8hi, v4si, v8hf, v4sf) > VAR5 (LOAD1, vld4q, v16qi, v8hi, v4si, v8hf, v4sf) > VAR5 (LOAD1, vld2q, v16qi, v8hi, v4si, v8hf, v4sf) > diff --git a/gcc/config/arm/mve.md b/gcc/config/arm/mve.md > index 241195909da..f73b5f6f1f1 100644 > --- a/gcc/config/arm/mve.md > +++ b/gcc/config/arm/mve.md > @@ -826,7 +826,7 @@ (define_insn "mve_vaddlvq_p_<supf>v4si" > [ > (set (match_operand:DI 0 "s_register_operand" "=r") > (unspec:DI [(match_operand:V4SI 1 "s_register_operand" "w") > - (match_operand:HI 2 "vpr_register_operand" "Up")] > + (match_operand:V4BI 2 "vpr_register_operand" "Up")] > VADDLVQ_P)) > ] > "TARGET_HAVE_MVE" > @@ -3751,7 +3751,7 @@ (define_insn "mve_vaddlvaq_p_<supf>v4si" > (set (match_operand:DI 0 "s_register_operand" "=r") > (unspec:DI [(match_operand:DI 1 "s_register_operand" "0") > (match_operand:V4SI 2 "s_register_operand" "w") > - (match_operand:HI 3 "vpr_register_operand" "Up")] > + (match_operand:V4BI 3 "vpr_register_operand" "Up")] > VADDLVAQ_P)) > ] > "TARGET_HAVE_MVE" > @@ -3961,7 +3961,7 @@ (define_insn "mve_vcvtbq_m_f16_f32v8hf" > (set (match_operand:V8HF 0 "s_register_operand" "=w") > (unspec:V8HF [(match_operand:V8HF 1 "s_register_operand" "0") > (match_operand:V4SF 2 "s_register_operand" "w") > - (match_operand:HI 3 "vpr_register_operand" "Up")] > + (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")] > VCVTBQ_M_F16_F32)) > ] > "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" > @@ -3977,7 +3977,7 @@ (define_insn "mve_vcvtbq_m_f32_f16v4sf" > (set (match_operand:V4SF 0 "s_register_operand" "=w") > (unspec:V4SF [(match_operand:V4SF 1 "s_register_operand" "0") > (match_operand:V8HF 2 "s_register_operand" "w") > - (match_operand:HI 3 "vpr_register_operand" "Up")] > + (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")] > VCVTBQ_M_F32_F16)) > ] > "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" > @@ -3993,7 +3993,7 @@ (define_insn "mve_vcvttq_m_f16_f32v8hf" > (set (match_operand:V8HF 0 "s_register_operand" "=w") > (unspec:V8HF [(match_operand:V8HF 1 "s_register_operand" "0") > (match_operand:V4SF 2 "s_register_operand" "w") > - (match_operand:HI 3 "vpr_register_operand" "Up")] > + (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")] > VCVTTQ_M_F16_F32)) > ] > "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" > @@ -4009,7 +4009,7 @@ (define_insn "mve_vcvttq_m_f32_f16v4sf" > (set (match_operand:V4SF 0 "s_register_operand" "=w") > (unspec:V4SF [(match_operand:V4SF 1 "s_register_operand" "0") > (match_operand:V8HF 2 "s_register_operand" "w") > - (match_operand:HI 3 "vpr_register_operand" "Up")] > + (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")] > VCVTTQ_M_F32_F16)) > ] > "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" > @@ -4607,7 +4607,7 @@ (define_insn "mve_vrev32q_m_fv8hf" > (set (match_operand:V8HF 0 "s_register_operand" "=w") > (unspec:V8HF [(match_operand:V8HF 1 "s_register_operand" "0") > (match_operand:V8HF 2 "s_register_operand" "w") > - (match_operand:HI 3 "vpr_register_operand" "Up")] > + (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")] > VREV32Q_M_F)) > ] > "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" > @@ -4671,7 +4671,7 @@ (define_insn "mve_vrmlaldavhxq_p_sv4si" > (set (match_operand:DI 0 "s_register_operand" "=r") > (unspec:DI [(match_operand:V4SI 1 "s_register_operand" "w") > (match_operand:V4SI 2 "s_register_operand" "w") > - (match_operand:HI 3 "vpr_register_operand" "Up")] > + (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")] > VRMLALDAVHXQ_P_S)) > ] > "TARGET_HAVE_MVE" > @@ -4703,7 +4703,7 @@ (define_insn "mve_vrmlsldavhq_p_sv4si" > (set (match_operand:DI 0 "s_register_operand" "=r") > (unspec:DI [(match_operand:V4SI 1 "s_register_operand" "w") > (match_operand:V4SI 2 "s_register_operand" "w") > - (match_operand:HI 3 "vpr_register_operand" "Up")] > + (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")] > VRMLSLDAVHQ_P_S)) > ] > "TARGET_HAVE_MVE" > @@ -4719,7 +4719,7 @@ (define_insn "mve_vrmlsldavhxq_p_sv4si" > (set (match_operand:DI 0 "s_register_operand" "=r") > (unspec:DI [(match_operand:V4SI 1 "s_register_operand" "w") > (match_operand:V4SI 2 "s_register_operand" "w") > - (match_operand:HI 3 "vpr_register_operand" "Up")] > + (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")] > VRMLSLDAVHXQ_P_S)) > ] > "TARGET_HAVE_MVE" > @@ -4944,7 +4944,7 @@ (define_insn "mve_vrev16q_m_<supf>v16qi" > (set (match_operand:V16QI 0 "s_register_operand" "=w") > (unspec:V16QI [(match_operand:V16QI 1 "s_register_operand" "0") > (match_operand:V16QI 2 "s_register_operand" "w") > - (match_operand:HI 3 "vpr_register_operand" "Up")] > + (match_operand:V16BI 3 "vpr_register_operand" "Up")] > VREV16Q_M)) > ] > "TARGET_HAVE_MVE" > @@ -4976,7 +4976,7 @@ (define_insn "mve_vrmlaldavhq_p_<supf>v4si" > (set (match_operand:DI 0 "s_register_operand" "=r") > (unspec:DI [(match_operand:V4SI 1 "s_register_operand" "w") > (match_operand:V4SI 2 "s_register_operand" "w") > - (match_operand:HI 3 "vpr_register_operand" "Up")] > + (match_operand:V4BI 3 "vpr_register_operand" "Up")] > VRMLALDAVHQ_P)) > ] > "TARGET_HAVE_MVE" > @@ -6245,7 +6245,7 @@ (define_insn "mve_vrmlaldavhaq_p_sv4si" > (unspec:DI [(match_operand:DI 1 "s_register_operand" "0") > (match_operand:V4SI 2 "s_register_operand" "w") > (match_operand:V4SI 3 "s_register_operand" "w") > - (match_operand:HI 4 "vpr_register_operand" "Up")] > + (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")] > VRMLALDAVHAQ_P_S)) > ] > "TARGET_HAVE_MVE" > @@ -6568,7 +6568,7 @@ (define_insn "mve_vrmlaldavhaq_p_uv4si" > (unspec:DI [(match_operand:DI 1 "s_register_operand" "0") > (match_operand:V4SI 2 "s_register_operand" "w") > (match_operand:V4SI 3 "s_register_operand" "w") > - (match_operand:HI 4 "vpr_register_operand" "Up")] > + (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")] > VRMLALDAVHAQ_P_U)) > ] > "TARGET_HAVE_MVE" > @@ -6585,7 +6585,7 @@ (define_insn "mve_vrmlaldavhaxq_p_sv4si" > (unspec:DI [(match_operand:DI 1 "s_register_operand" "0") > (match_operand:V4SI 2 "s_register_operand" "w") > (match_operand:V4SI 3 "s_register_operand" "w") > - (match_operand:HI 4 "vpr_register_operand" "Up")] > + (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")] > VRMLALDAVHAXQ_P_S)) > ] > "TARGET_HAVE_MVE" > @@ -6602,7 +6602,7 @@ (define_insn "mve_vrmlsldavhaq_p_sv4si" > (unspec:DI [(match_operand:DI 1 "s_register_operand" "0") > (match_operand:V4SI 2 "s_register_operand" "w") > (match_operand:V4SI 3 "s_register_operand" "w") > - (match_operand:HI 4 "vpr_register_operand" "Up")] > + (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")] > VRMLSLDAVHAQ_P_S)) > ] > "TARGET_HAVE_MVE" > @@ -6619,7 +6619,7 @@ (define_insn "mve_vrmlsldavhaxq_p_sv4si" > (unspec:DI [(match_operand:DI 1 "s_register_operand" "0") > (match_operand:V4SI 2 "s_register_operand" "w") > (match_operand:V4SI 3 "s_register_operand" "w") > - (match_operand:HI 4 "vpr_register_operand" "Up")] > + (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")] > VRMLSLDAVHAXQ_P_S)) > ] > "TARGET_HAVE_MVE" > @@ -7540,7 +7540,7 @@ (define_insn "mve_vldrhq_<supf><mode>" > (define_insn "mve_vldrhq_z_fv8hf" > [(set (match_operand:V8HF 0 "s_register_operand" "=w") > (unspec:V8HF [(match_operand:V8HI 1 "mve_memory_operand" "Ux") > - (match_operand:HI 2 "vpr_register_operand" "Up")] > + (match_operand:<MVE_VPRED> 2 "vpr_register_operand" "Up")] > VLDRHQ_F)) > ] > "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" > @@ -8315,7 +8315,7 @@ (define_insn "mve_vstrwq_fv4sf" > (define_insn "mve_vstrwq_p_fv4sf" > [(set (match_operand:V4SI 0 "memory_operand" "=Ux") > (unspec:V4SI [(match_operand:V4SF 1 "s_register_operand" "w") > - (match_operand:HI 2 "vpr_register_operand" "Up")] > + (match_operand:<MVE_VPRED> 2 "vpr_register_operand" "Up")] > VSTRWQ_F)) > ] > "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" > @@ -9856,7 +9856,7 @@ (define_insn "mve_vadciq_m_<supf>v4si" > (unspec:V4SI [(match_operand:V4SI 1 "s_register_operand" "0") > (match_operand:V4SI 2 "s_register_operand" "w") > (match_operand:V4SI 3 "s_register_operand" "w") > - (match_operand:HI 4 "vpr_register_operand" "Up")] > + (match_operand:V4BI 4 "vpr_register_operand" "Up")] > VADCIQ_M)) > (set (reg:SI VFPCC_REGNUM) > (unspec:SI [(const_int 0)] > @@ -9892,7 +9892,7 @@ (define_insn "mve_vadcq_m_<supf>v4si" > (unspec:V4SI [(match_operand:V4SI 1 "s_register_operand" "0") > (match_operand:V4SI 2 "s_register_operand" "w") > (match_operand:V4SI 3 "s_register_operand" "w") > - (match_operand:HI 4 "vpr_register_operand" "Up")] > + (match_operand:V4BI 4 "vpr_register_operand" "Up")] > VADCQ_M)) > (set (reg:SI VFPCC_REGNUM) > (unspec:SI [(reg:SI VFPCC_REGNUM)] > @@ -9929,7 +9929,7 @@ (define_insn "mve_vsbciq_m_<supf>v4si" > (unspec:V4SI [(match_operand:V4SI 1 "s_register_operand" "w") > (match_operand:V4SI 2 "s_register_operand" "w") > (match_operand:V4SI 3 "s_register_operand" "w") > - (match_operand:HI 4 "vpr_register_operand" "Up")] > + (match_operand:V4BI 4 "vpr_register_operand" "Up")] > VSBCIQ_M)) > (set (reg:SI VFPCC_REGNUM) > (unspec:SI [(const_int 0)] > @@ -9965,7 +9965,7 @@ (define_insn "mve_vsbcq_m_<supf>v4si" > (unspec:V4SI [(match_operand:V4SI 1 "s_register_operand" "w") > (match_operand:V4SI 2 "s_register_operand" "w") > (match_operand:V4SI 3 "s_register_operand" "w") > - (match_operand:HI 4 "vpr_register_operand" "Up")] > + (match_operand:V4BI 4 "vpr_register_operand" "Up")] > VSBCQ_M)) > (set (reg:SI VFPCC_REGNUM) > (unspec:SI [(reg:SI VFPCC_REGNUM)] > @@ -10469,7 +10469,7 @@ (define_insn "arm_vcx1q<a>_p_v16qi" > (unspec:V16QI [(match_operand:SI 1 "const_int_coproc_operand" "i") > (match_operand:V16QI 2 "register_operand" "0") > (match_operand:SI 3 "const_int_mve_cde1_operand" "i") > - (match_operand:HI 4 "vpr_register_operand" "Up")] > + (match_operand:V16BI 4 "vpr_register_operand" "Up")] > CDE_VCX))] > "TARGET_CDE && TARGET_HAVE_MVE" > "vpst\;vcx1<a>t\\tp%c1, %q0, #%c3" > @@ -10483,7 +10483,7 @@ (define_insn "arm_vcx2q<a>_p_v16qi" > (match_operand:V16QI 2 "register_operand" "0") > (match_operand:V16QI 3 "register_operand" "t") > (match_operand:SI 4 "const_int_mve_cde2_operand" "i") > - (match_operand:HI 5 "vpr_register_operand" "Up")] > + (match_operand:V16BI 5 "vpr_register_operand" "Up")] > CDE_VCX))] > "TARGET_CDE && TARGET_HAVE_MVE" > "vpst\;vcx2<a>t\\tp%c1, %q0, %q3, #%c4" > @@ -10498,7 +10498,7 @@ (define_insn "arm_vcx3q<a>_p_v16qi" > (match_operand:V16QI 3 "register_operand" "t") > (match_operand:V16QI 4 "register_operand" "t") > (match_operand:SI 5 "const_int_mve_cde3_operand" "i") > - (match_operand:HI 6 "vpr_register_operand" "Up")] > + (match_operand:V16BI 6 "vpr_register_operand" "Up")] > CDE_VCX))] > "TARGET_CDE && TARGET_HAVE_MVE" > "vpst\;vcx3<a>t\\tp%c1, %q0, %q3, %q4, #%c5" > diff --git a/gcc/testsuite/gcc.target/arm/acle/cde-mve-full-assembly.c b/gcc/testsuite/gcc.target/arm/acle/cde-mve-full-assembly.c > index 501cc84da10..77ea2866ad2 100644 > --- a/gcc/testsuite/gcc.target/arm/acle/cde-mve-full-assembly.c > +++ b/gcc/testsuite/gcc.target/arm/acle/cde-mve-full-assembly.c > @@ -567,80 +567,80 @@ > contain back references). */ > /* > ** test_cde_vcx1q_mfloat16x8_tintint: > -** (?:vldr\.64 d0, \.L[0-9]*\n\tvldr\.64 d1, \.L[0-9]*\+8|vmsr P0, r2 @ movhi) > -** (?:vldr\.64 d0, \.L[0-9]*\n\tvldr\.64 d1, \.L[0-9]*\+8|vmsr P0, r2 @ movhi) > +** (?:vldr\.64 d0, \.L[0-9]*\n\tvldr\.64 d1, \.L[0-9]*\+8|vmsr P0, r2) > +** (?:vldr\.64 d0, \.L[0-9]*\n\tvldr\.64 d1, \.L[0-9]*\+8|vmsr P0, r2) > ** vpst > ** vcx1t p0, q0, #32 > ** bx lr > */ > /* > ** test_cde_vcx1q_mfloat32x4_tintint: > -** (?:vldr\.64 d0, \.L[0-9]*\n\tvldr\.64 d1, \.L[0-9]*\+8|vmsr P0, r2 @ movhi) > -** (?:vldr\.64 d0, \.L[0-9]*\n\tvldr\.64 d1, \.L[0-9]*\+8|vmsr P0, r2 @ movhi) > +** (?:vldr\.64 d0, \.L[0-9]*\n\tvldr\.64 d1, \.L[0-9]*\+8|vmsr P0, r2) > +** (?:vldr\.64 d0, \.L[0-9]*\n\tvldr\.64 d1, \.L[0-9]*\+8|vmsr P0, r2) > ** vpst > ** vcx1t p0, q0, #32 > ** bx lr > */ > /* > ** test_cde_vcx1q_muint8x16_tintint: > -** (?:vldr\.64 d0, \.L[0-9]*\n\tvldr\.64 d1, \.L[0-9]*\+8|vmsr P0, r2 @ movhi) > -** (?:vldr\.64 d0, \.L[0-9]*\n\tvldr\.64 d1, \.L[0-9]*\+8|vmsr P0, r2 @ movhi) > +** (?:vldr\.64 d0, \.L[0-9]*\n\tvldr\.64 d1, \.L[0-9]*\+8|vmsr P0, r2) > +** (?:vldr\.64 d0, \.L[0-9]*\n\tvldr\.64 d1, \.L[0-9]*\+8|vmsr P0, r2) > ** vpst > ** vcx1t p0, q0, #32 > ** bx lr > */ > /* > ** test_cde_vcx1q_muint16x8_tintint: > -** (?:vldr\.64 d0, \.L[0-9]*\n\tvldr\.64 d1, \.L[0-9]*\+8|vmsr P0, r2 @ movhi) > -** (?:vldr\.64 d0, \.L[0-9]*\n\tvldr\.64 d1, \.L[0-9]*\+8|vmsr P0, r2 @ movhi) > +** (?:vldr\.64 d0, \.L[0-9]*\n\tvldr\.64 d1, \.L[0-9]*\+8|vmsr P0, r2) > +** (?:vldr\.64 d0, \.L[0-9]*\n\tvldr\.64 d1, \.L[0-9]*\+8|vmsr P0, r2) > ** vpst > ** vcx1t p0, q0, #32 > ** bx lr > */ > /* > ** test_cde_vcx1q_muint32x4_tintint: > -** (?:vldr\.64 d0, \.L[0-9]*\n\tvldr\.64 d1, \.L[0-9]*\+8|vmsr P0, r2 @ movhi) > -** (?:vldr\.64 d0, \.L[0-9]*\n\tvldr\.64 d1, \.L[0-9]*\+8|vmsr P0, r2 @ movhi) > +** (?:vldr\.64 d0, \.L[0-9]*\n\tvldr\.64 d1, \.L[0-9]*\+8|vmsr P0, r2) > +** (?:vldr\.64 d0, \.L[0-9]*\n\tvldr\.64 d1, \.L[0-9]*\+8|vmsr P0, r2) > ** vpst > ** vcx1t p0, q0, #32 > ** bx lr > */ > /* > ** test_cde_vcx1q_muint64x2_tintint: > -** (?:vldr\.64 d0, \.L[0-9]*\n\tvldr\.64 d1, \.L[0-9]*\+8|vmsr P0, r2 @ movhi) > -** (?:vldr\.64 d0, \.L[0-9]*\n\tvldr\.64 d1, \.L[0-9]*\+8|vmsr P0, r2 @ movhi) > +** (?:vldr\.64 d0, \.L[0-9]*\n\tvldr\.64 d1, \.L[0-9]*\+8|vmsr P0, r2) > +** (?:vldr\.64 d0, \.L[0-9]*\n\tvldr\.64 d1, \.L[0-9]*\+8|vmsr P0, r2) > ** vpst > ** vcx1t p0, q0, #32 > ** bx lr > */ > /* > ** test_cde_vcx1q_mint8x16_tintint: > -** (?:vldr\.64 d0, \.L[0-9]*\n\tvldr\.64 d1, \.L[0-9]*\+8|vmsr P0, r2 @ movhi) > -** (?:vldr\.64 d0, \.L[0-9]*\n\tvldr\.64 d1, \.L[0-9]*\+8|vmsr P0, r2 @ movhi) > +** (?:vldr\.64 d0, \.L[0-9]*\n\tvldr\.64 d1, \.L[0-9]*\+8|vmsr P0, r2) > +** (?:vldr\.64 d0, \.L[0-9]*\n\tvldr\.64 d1, \.L[0-9]*\+8|vmsr P0, r2) > ** vpst > ** vcx1t p0, q0, #32 > ** bx lr > */ > /* > ** test_cde_vcx1q_mint16x8_tintint: > -** (?:vldr\.64 d0, \.L[0-9]*\n\tvldr\.64 d1, \.L[0-9]*\+8|vmsr P0, r2 @ movhi) > -** (?:vldr\.64 d0, \.L[0-9]*\n\tvldr\.64 d1, \.L[0-9]*\+8|vmsr P0, r2 @ movhi) > +** (?:vldr\.64 d0, \.L[0-9]*\n\tvldr\.64 d1, \.L[0-9]*\+8|vmsr P0, r2) > +** (?:vldr\.64 d0, \.L[0-9]*\n\tvldr\.64 d1, \.L[0-9]*\+8|vmsr P0, r2) > ** vpst > ** vcx1t p0, q0, #32 > ** bx lr > */ > /* > ** test_cde_vcx1q_mint32x4_tintint: > -** (?:vldr\.64 d0, \.L[0-9]*\n\tvldr\.64 d1, \.L[0-9]*\+8|vmsr P0, r2 @ movhi) > -** (?:vldr\.64 d0, \.L[0-9]*\n\tvldr\.64 d1, \.L[0-9]*\+8|vmsr P0, r2 @ movhi) > +** (?:vldr\.64 d0, \.L[0-9]*\n\tvldr\.64 d1, \.L[0-9]*\+8|vmsr P0, r2) > +** (?:vldr\.64 d0, \.L[0-9]*\n\tvldr\.64 d1, \.L[0-9]*\+8|vmsr P0, r2) > ** vpst > ** vcx1t p0, q0, #32 > ** bx lr > */ > /* > ** test_cde_vcx1q_mint64x2_tintint: > -** (?:vldr\.64 d0, \.L[0-9]*\n\tvldr\.64 d1, \.L[0-9]*\+8|vmsr P0, r2 @ movhi) > -** (?:vldr\.64 d0, \.L[0-9]*\n\tvldr\.64 d1, \.L[0-9]*\+8|vmsr P0, r2 @ movhi) > +** (?:vldr\.64 d0, \.L[0-9]*\n\tvldr\.64 d1, \.L[0-9]*\+8|vmsr P0, r2) > +** (?:vldr\.64 d0, \.L[0-9]*\n\tvldr\.64 d1, \.L[0-9]*\+8|vmsr P0, r2) > ** vpst > ** vcx1t p0, q0, #32 > ** bx lr > @@ -649,80 +649,80 @@ > > /* > ** test_cde_vcx1qa_mfloat16x8_tintint: > -** (?:vldr\.64 d0, \.L[0-9]*\n\tvldr\.64 d1, \.L[0-9]*\+8|vmsr P0, r2 @ movhi) > -** (?:vldr\.64 d0, \.L[0-9]*\n\tvldr\.64 d1, \.L[0-9]*\+8|vmsr P0, r2 @ movhi) > +** (?:vldr\.64 d0, \.L[0-9]*\n\tvldr\.64 d1, \.L[0-9]*\+8|vmsr P0, r2) > +** (?:vldr\.64 d0, \.L[0-9]*\n\tvldr\.64 d1, \.L[0-9]*\+8|vmsr P0, r2) > ** vpst > ** vcx1at p0, q0, #32 > ** bx lr > */ > /* > ** test_cde_vcx1qa_mfloat32x4_tintint: > -** (?:vldr\.64 d0, \.L[0-9]*\n\tvldr\.64 d1, \.L[0-9]*\+8|vmsr P0, r2 @ movhi) > -** (?:vldr\.64 d0, \.L[0-9]*\n\tvldr\.64 d1, \.L[0-9]*\+8|vmsr P0, r2 @ movhi) > +** (?:vldr\.64 d0, \.L[0-9]*\n\tvldr\.64 d1, \.L[0-9]*\+8|vmsr P0, r2) > +** (?:vldr\.64 d0, \.L[0-9]*\n\tvldr\.64 d1, \.L[0-9]*\+8|vmsr P0, r2) > ** vpst > ** vcx1at p0, q0, #32 > ** bx lr > */ > /* > ** test_cde_vcx1qa_muint8x16_tintint: > -** (?:vldr\.64 d0, \.L[0-9]*\n\tvldr\.64 d1, \.L[0-9]*\+8|vmsr P0, r2 @ movhi) > -** (?:vldr\.64 d0, \.L[0-9]*\n\tvldr\.64 d1, \.L[0-9]*\+8|vmsr P0, r2 @ movhi) > +** (?:vldr\.64 d0, \.L[0-9]*\n\tvldr\.64 d1, \.L[0-9]*\+8|vmsr P0, r2) > +** (?:vldr\.64 d0, \.L[0-9]*\n\tvldr\.64 d1, \.L[0-9]*\+8|vmsr P0, r2) > ** vpst > ** vcx1at p0, q0, #32 > ** bx lr > */ > /* > ** test_cde_vcx1qa_muint16x8_tintint: > -** (?:vldr\.64 d0, \.L[0-9]*\n\tvldr\.64 d1, \.L[0-9]*\+8|vmsr P0, r2 @ movhi) > -** (?:vldr\.64 d0, \.L[0-9]*\n\tvldr\.64 d1, \.L[0-9]*\+8|vmsr P0, r2 @ movhi) > +** (?:vldr\.64 d0, \.L[0-9]*\n\tvldr\.64 d1, \.L[0-9]*\+8|vmsr P0, r2) > +** (?:vldr\.64 d0, \.L[0-9]*\n\tvldr\.64 d1, \.L[0-9]*\+8|vmsr P0, r2) > ** vpst > ** vcx1at p0, q0, #32 > ** bx lr > */ > /* > ** test_cde_vcx1qa_muint32x4_tintint: > -** (?:vldr\.64 d0, \.L[0-9]*\n\tvldr\.64 d1, \.L[0-9]*\+8|vmsr P0, r2 @ movhi) > -** (?:vldr\.64 d0, \.L[0-9]*\n\tvldr\.64 d1, \.L[0-9]*\+8|vmsr P0, r2 @ movhi) > +** (?:vldr\.64 d0, \.L[0-9]*\n\tvldr\.64 d1, \.L[0-9]*\+8|vmsr P0, r2) > +** (?:vldr\.64 d0, \.L[0-9]*\n\tvldr\.64 d1, \.L[0-9]*\+8|vmsr P0, r2) > ** vpst > ** vcx1at p0, q0, #32 > ** bx lr > */ > /* > ** test_cde_vcx1qa_muint64x2_tintint: > -** (?:vldr\.64 d0, \.L[0-9]*\n\tvldr\.64 d1, \.L[0-9]*\+8|vmsr P0, r2 @ movhi) > -** (?:vldr\.64 d0, \.L[0-9]*\n\tvldr\.64 d1, \.L[0-9]*\+8|vmsr P0, r2 @ movhi) > +** (?:vldr\.64 d0, \.L[0-9]*\n\tvldr\.64 d1, \.L[0-9]*\+8|vmsr P0, r2) > +** (?:vldr\.64 d0, \.L[0-9]*\n\tvldr\.64 d1, \.L[0-9]*\+8|vmsr P0, r2) > ** vpst > ** vcx1at p0, q0, #32 > ** bx lr > */ > /* > ** test_cde_vcx1qa_mint8x16_tintint: > -** (?:vldr\.64 d0, \.L[0-9]*\n\tvldr\.64 d1, \.L[0-9]*\+8|vmsr P0, r2 @ movhi) > -** (?:vldr\.64 d0, \.L[0-9]*\n\tvldr\.64 d1, \.L[0-9]*\+8|vmsr P0, r2 @ movhi) > +** (?:vldr\.64 d0, \.L[0-9]*\n\tvldr\.64 d1, \.L[0-9]*\+8|vmsr P0, r2) > +** (?:vldr\.64 d0, \.L[0-9]*\n\tvldr\.64 d1, \.L[0-9]*\+8|vmsr P0, r2) > ** vpst > ** vcx1at p0, q0, #32 > ** bx lr > */ > /* > ** test_cde_vcx1qa_mint16x8_tintint: > -** (?:vldr\.64 d0, \.L[0-9]*\n\tvldr\.64 d1, \.L[0-9]*\+8|vmsr P0, r2 @ movhi) > -** (?:vldr\.64 d0, \.L[0-9]*\n\tvldr\.64 d1, \.L[0-9]*\+8|vmsr P0, r2 @ movhi) > +** (?:vldr\.64 d0, \.L[0-9]*\n\tvldr\.64 d1, \.L[0-9]*\+8|vmsr P0, r2) > +** (?:vldr\.64 d0, \.L[0-9]*\n\tvldr\.64 d1, \.L[0-9]*\+8|vmsr P0, r2) > ** vpst > ** vcx1at p0, q0, #32 > ** bx lr > */ > /* > ** test_cde_vcx1qa_mint32x4_tintint: > -** (?:vldr\.64 d0, \.L[0-9]*\n\tvldr\.64 d1, \.L[0-9]*\+8|vmsr P0, r2 @ movhi) > -** (?:vldr\.64 d0, \.L[0-9]*\n\tvldr\.64 d1, \.L[0-9]*\+8|vmsr P0, r2 @ movhi) > +** (?:vldr\.64 d0, \.L[0-9]*\n\tvldr\.64 d1, \.L[0-9]*\+8|vmsr P0, r2) > +** (?:vldr\.64 d0, \.L[0-9]*\n\tvldr\.64 d1, \.L[0-9]*\+8|vmsr P0, r2) > ** vpst > ** vcx1at p0, q0, #32 > ** bx lr > */ > /* > ** test_cde_vcx1qa_mint64x2_tintint: > -** (?:vldr\.64 d0, \.L[0-9]*\n\tvldr\.64 d1, \.L[0-9]*\+8|vmsr P0, r2 @ movhi) > -** (?:vldr\.64 d0, \.L[0-9]*\n\tvldr\.64 d1, \.L[0-9]*\+8|vmsr P0, r2 @ movhi) > +** (?:vldr\.64 d0, \.L[0-9]*\n\tvldr\.64 d1, \.L[0-9]*\+8|vmsr P0, r2) > +** (?:vldr\.64 d0, \.L[0-9]*\n\tvldr\.64 d1, \.L[0-9]*\+8|vmsr P0, r2) > ** vpst > ** vcx1at p0, q0, #32 > ** bx lr > @@ -731,8 +731,8 @@ > > /* > ** test_cde_vcx2q_mfloat16x8_tuint16x8_tint: > -** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r1 @ movhi) > -** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r1 @ movhi) > +** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r1) > +** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r1) > ** vpst > ** vcx2t p0, (q[0-7]), q0, #32 > ** vmov q0, \1([[:space:]]+@ [^\n]*)? > @@ -740,8 +740,8 @@ > */ > /* > ** test_cde_vcx2q_mfloat16x8_tfloat32x4_tint: > -** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r1 @ movhi) > -** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r1 @ movhi) > +** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r1) > +** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r1) > ** vpst > ** vcx2t p0, (q[0-7]), q0, #32 > ** vmov q0, \1([[:space:]]+@ [^\n]*)? > @@ -749,8 +749,8 @@ > */ > /* > ** test_cde_vcx2q_mfloat32x4_tuint8x16_tint: > -** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r1 @ movhi) > -** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r1 @ movhi) > +** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r1) > +** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r1) > ** vpst > ** vcx2t p0, (q[0-7]), q0, #32 > ** vmov q0, \1([[:space:]]+@ [^\n]*)? > @@ -758,8 +758,8 @@ > */ > /* > ** test_cde_vcx2q_mint64x2_tuint8x16_tint: > -** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r1 @ movhi) > -** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r1 @ movhi) > +** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r1) > +** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r1) > ** vpst > ** vcx2t p0, (q[0-7]), q0, #32 > ** vmov q0, \1([[:space:]]+@ [^\n]*)? > @@ -767,8 +767,8 @@ > */ > /* > ** test_cde_vcx2q_mint8x16_tuint8x16_tint: > -** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r1 @ movhi) > -** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r1 @ movhi) > +** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r1) > +** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r1) > ** vpst > ** vcx2t p0, (q[0-7]), q0, #32 > ** vmov q0, \1([[:space:]]+@ [^\n]*)? > @@ -776,8 +776,8 @@ > */ > /* > ** test_cde_vcx2q_muint16x8_tuint8x16_tint: > -** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r1 @ movhi) > -** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r1 @ movhi) > +** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r1) > +** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r1) > ** vpst > ** vcx2t p0, (q[0-7]), q0, #32 > ** vmov q0, \1([[:space:]]+@ [^\n]*)? > @@ -785,8 +785,8 @@ > */ > /* > ** test_cde_vcx2q_muint8x16_tint64x2_tint: > -** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r1 @ movhi) > -** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r1 @ movhi) > +** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r1) > +** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r1) > ** vpst > ** vcx2t p0, (q[0-7]), q0, #32 > ** vmov q0, \1([[:space:]]+@ [^\n]*)? > @@ -794,8 +794,8 @@ > */ > /* > ** test_cde_vcx2q_muint8x16_tint8x16_tint: > -** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r1 @ movhi) > -** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r1 @ movhi) > +** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r1) > +** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r1) > ** vpst > ** vcx2t p0, (q[0-7]), q0, #32 > ** vmov q0, \1([[:space:]]+@ [^\n]*)? > @@ -803,8 +803,8 @@ > */ > /* > ** test_cde_vcx2q_muint8x16_tuint16x8_tint: > -** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r1 @ movhi) > -** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r1 @ movhi) > +** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r1) > +** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r1) > ** vpst > ** vcx2t p0, (q[0-7]), q0, #32 > ** vmov q0, \1([[:space:]]+@ [^\n]*)? > @@ -812,8 +812,8 @@ > */ > /* > ** test_cde_vcx2q_muint8x16_tuint8x16_tint: > -** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r1 @ movhi) > -** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r1 @ movhi) > +** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r1) > +** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r1) > ** vpst > ** vcx2t p0, (q[0-7]), q0, #32 > ** vmov q0, \1([[:space:]]+@ [^\n]*)? > @@ -823,8 +823,8 @@ > > /* > ** test_cde_vcx2qa_mfloat16x8_tuint16x8_tint: > -** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r1 @ movhi) > -** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r1 @ movhi) > +** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r1) > +** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r1) > ** vpst > ** vcx2at p0, (q[0-7]), q0, #32 > ** vmov q0, \1([[:space:]]+@ [^\n]*)? > @@ -832,8 +832,8 @@ > */ > /* > ** test_cde_vcx2qa_mfloat16x8_tfloat32x4_tint: > -** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r1 @ movhi) > -** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r1 @ movhi) > +** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r1) > +** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r1) > ** vpst > ** vcx2at p0, (q[0-7]), q0, #32 > ** vmov q0, \1([[:space:]]+@ [^\n]*)? > @@ -841,8 +841,8 @@ > */ > /* > ** test_cde_vcx2qa_mfloat32x4_tuint8x16_tint: > -** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r1 @ movhi) > -** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r1 @ movhi) > +** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r1) > +** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r1) > ** vpst > ** vcx2at p0, (q[0-7]), q0, #32 > ** vmov q0, \1([[:space:]]+@ [^\n]*)? > @@ -850,8 +850,8 @@ > */ > /* > ** test_cde_vcx2qa_mint64x2_tuint8x16_tint: > -** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r1 @ movhi) > -** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r1 @ movhi) > +** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r1) > +** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r1) > ** vpst > ** vcx2at p0, (q[0-7]), q0, #32 > ** vmov q0, \1([[:space:]]+@ [^\n]*)? > @@ -859,8 +859,8 @@ > */ > /* > ** test_cde_vcx2qa_mint8x16_tuint8x16_tint: > -** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r1 @ movhi) > -** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r1 @ movhi) > +** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r1) > +** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r1) > ** vpst > ** vcx2at p0, (q[0-7]), q0, #32 > ** vmov q0, \1([[:space:]]+@ [^\n]*)? > @@ -868,8 +868,8 @@ > */ > /* > ** test_cde_vcx2qa_muint16x8_tuint8x16_tint: > -** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r1 @ movhi) > -** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r1 @ movhi) > +** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r1) > +** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r1) > ** vpst > ** vcx2at p0, (q[0-7]), q0, #32 > ** vmov q0, \1([[:space:]]+@ [^\n]*)? > @@ -877,8 +877,8 @@ > */ > /* > ** test_cde_vcx2qa_muint8x16_tint64x2_tint: > -** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r1 @ movhi) > -** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r1 @ movhi) > +** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r1) > +** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r1) > ** vpst > ** vcx2at p0, (q[0-7]), q0, #32 > ** vmov q0, \1([[:space:]]+@ [^\n]*)? > @@ -886,8 +886,8 @@ > */ > /* > ** test_cde_vcx2qa_muint8x16_tint8x16_tint: > -** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r1 @ movhi) > -** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r1 @ movhi) > +** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r1) > +** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r1) > ** vpst > ** vcx2at p0, (q[0-7]), q0, #32 > ** vmov q0, \1([[:space:]]+@ [^\n]*)? > @@ -895,8 +895,8 @@ > */ > /* > ** test_cde_vcx2qa_muint8x16_tuint16x8_tint: > -** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r1 @ movhi) > -** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r1 @ movhi) > +** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r1) > +** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r1) > ** vpst > ** vcx2at p0, (q[0-7]), q0, #32 > ** vmov q0, \1([[:space:]]+@ [^\n]*)? > @@ -904,8 +904,8 @@ > */ > /* > ** test_cde_vcx2qa_muint8x16_tuint8x16_tint: > -** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r1 @ movhi) > -** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r1 @ movhi) > +** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r1) > +** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r1) > ** vpst > ** vcx2at p0, (q[0-7]), q0, #32 > ** vmov q0, \1([[:space:]]+@ [^\n]*)? > @@ -915,8 +915,8 @@ > > /* > ** test_cde_vcx3q_muint8x16_tuint8x16_tuint8x16_t: > -** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r0 @ movhi) > -** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r0 @ movhi) > +** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r0) > +** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r0) > ** vpst > ** vcx3t p0, (q[0-7]), q0, q1, #15 > ** vmov q0, \1([[:space:]]+@ [^\n]*)? > @@ -924,8 +924,8 @@ > */ > /* > ** test_cde_vcx3q_mfloat16x8_tfloat16x8_tfloat16x8_t: > -** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r0 @ movhi) > -** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r0 @ movhi) > +** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r0) > +** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r0) > ** vpst > ** vcx3t p0, (q[0-7]), q0, q1, #15 > ** vmov q0, \1([[:space:]]+@ [^\n]*)? > @@ -933,8 +933,8 @@ > */ > /* > ** test_cde_vcx3q_mfloat32x4_tuint64x2_tfloat16x8_t: > -** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r0 @ movhi) > -** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r0 @ movhi) > +** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r0) > +** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r0) > ** vpst > ** vcx3t p0, (q[0-7]), q0, q1, #15 > ** vmov q0, \1([[:space:]]+@ [^\n]*)? > @@ -942,8 +942,8 @@ > */ > /* > ** test_cde_vcx3q_muint16x8_tuint8x16_tuint8x16_t: > -** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r0 @ movhi) > -** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r0 @ movhi) > +** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r0) > +** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r0) > ** vpst > ** vcx3t p0, (q[0-7]), q0, q1, #15 > ** vmov q0, \1([[:space:]]+@ [^\n]*)? > @@ -951,8 +951,8 @@ > */ > /* > ** test_cde_vcx3q_muint8x16_tuint16x8_tuint8x16_t: > -** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r0 @ movhi) > -** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r0 @ movhi) > +** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r0) > +** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r0) > ** vpst > ** vcx3t p0, (q[0-7]), q0, q1, #15 > ** vmov q0, \1([[:space:]]+@ [^\n]*)? > @@ -960,8 +960,8 @@ > */ > /* > ** test_cde_vcx3q_muint8x16_tuint8x16_tuint16x8_t: > -** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r0 @ movhi) > -** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r0 @ movhi) > +** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r0) > +** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r0) > ** vpst > ** vcx3t p0, (q[0-7]), q0, q1, #15 > ** vmov q0, \1([[:space:]]+@ [^\n]*)? > @@ -969,8 +969,8 @@ > */ > /* > ** test_cde_vcx3q_mint8x16_tuint8x16_tuint8x16_t: > -** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r0 @ movhi) > -** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r0 @ movhi) > +** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r0) > +** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r0) > ** vpst > ** vcx3t p0, (q[0-7]), q0, q1, #15 > ** vmov q0, \1([[:space:]]+@ [^\n]*)? > @@ -978,8 +978,8 @@ > */ > /* > ** test_cde_vcx3q_muint8x16_tint8x16_tuint8x16_t: > -** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r0 @ movhi) > -** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r0 @ movhi) > +** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r0) > +** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r0) > ** vpst > ** vcx3t p0, (q[0-7]), q0, q1, #15 > ** vmov q0, \1([[:space:]]+@ [^\n]*)? > @@ -987,8 +987,8 @@ > */ > /* > ** test_cde_vcx3q_muint8x16_tuint8x16_tint8x16_t: > -** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r0 @ movhi) > -** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r0 @ movhi) > +** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r0) > +** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r0) > ** vpst > ** vcx3t p0, (q[0-7]), q0, q1, #15 > ** vmov q0, \1([[:space:]]+@ [^\n]*)? > @@ -996,8 +996,8 @@ > */ > /* > ** test_cde_vcx3q_mint64x2_tuint8x16_tuint8x16_t: > -** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r0 @ movhi) > -** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r0 @ movhi) > +** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r0) > +** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r0) > ** vpst > ** vcx3t p0, (q[0-7]), q0, q1, #15 > ** vmov q0, \1([[:space:]]+@ [^\n]*)? > @@ -1005,8 +1005,8 @@ > */ > /* > ** test_cde_vcx3q_muint8x16_tint64x2_tuint8x16_t: > -** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r0 @ movhi) > -** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r0 @ movhi) > +** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r0) > +** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r0) > ** vpst > ** vcx3t p0, (q[0-7]), q0, q1, #15 > ** vmov q0, \1([[:space:]]+@ [^\n]*)? > @@ -1014,8 +1014,8 @@ > */ > /* > ** test_cde_vcx3q_muint8x16_tuint8x16_tint64x2_t: > -** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r0 @ movhi) > -** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r0 @ movhi) > +** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r0) > +** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r0) > ** vpst > ** vcx3t p0, (q[0-7]), q0, q1, #15 > ** vmov q0, \1([[:space:]]+@ [^\n]*)? > @@ -1023,8 +1023,8 @@ > */ > /* > ** test_cde_vcx3q_muint8x16_tint64x2_tint64x2_t: > -** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r0 @ movhi) > -** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r0 @ movhi) > +** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r0) > +** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r0) > ** vpst > ** vcx3t p0, (q[0-7]), q0, q1, #15 > ** vmov q0, \1([[:space:]]+@ [^\n]*)? > @@ -1034,8 +1034,8 @@ > > /* > ** test_cde_vcx3qa_muint8x16_tuint8x16_tuint8x16_t: > -** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r0 @ movhi) > -** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r0 @ movhi) > +** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r0) > +** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r0) > ** vpst > ** vcx3at p0, (q[0-7]), q0, q1, #15 > ** vmov q0, \1([[:space:]]+@ [^\n]*)? > @@ -1043,8 +1043,8 @@ > */ > /* > ** test_cde_vcx3qa_mfloat16x8_tfloat16x8_tfloat16x8_t: > -** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r0 @ movhi) > -** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r0 @ movhi) > +** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r0) > +** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r0) > ** vpst > ** vcx3at p0, (q[0-7]), q0, q1, #15 > ** vmov q0, \1([[:space:]]+@ [^\n]*)? > @@ -1052,8 +1052,8 @@ > */ > /* > ** test_cde_vcx3qa_mfloat32x4_tuint64x2_tfloat16x8_t: > -** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r0 @ movhi) > -** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r0 @ movhi) > +** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r0) > +** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r0) > ** vpst > ** vcx3at p0, (q[0-7]), q0, q1, #15 > ** vmov q0, \1([[:space:]]+@ [^\n]*)? > @@ -1061,8 +1061,8 @@ > */ > /* > ** test_cde_vcx3qa_muint16x8_tuint8x16_tuint8x16_t: > -** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r0 @ movhi) > -** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r0 @ movhi) > +** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r0) > +** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r0) > ** vpst > ** vcx3at p0, (q[0-7]), q0, q1, #15 > ** vmov q0, \1([[:space:]]+@ [^\n]*)? > @@ -1070,8 +1070,8 @@ > */ > /* > ** test_cde_vcx3qa_muint8x16_tuint16x8_tuint8x16_t: > -** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r0 @ movhi) > -** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r0 @ movhi) > +** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r0) > +** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r0) > ** vpst > ** vcx3at p0, (q[0-7]), q0, q1, #15 > ** vmov q0, \1([[:space:]]+@ [^\n]*)? > @@ -1079,8 +1079,8 @@ > */ > /* > ** test_cde_vcx3qa_muint8x16_tuint8x16_tuint16x8_t: > -** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r0 @ movhi) > -** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r0 @ movhi) > +** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r0) > +** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r0) > ** vpst > ** vcx3at p0, (q[0-7]), q0, q1, #15 > ** vmov q0, \1([[:space:]]+@ [^\n]*)? > @@ -1088,8 +1088,8 @@ > */ > /* > ** test_cde_vcx3qa_mint8x16_tuint8x16_tuint8x16_t: > -** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r0 @ movhi) > -** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r0 @ movhi) > +** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r0) > +** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r0) > ** vpst > ** vcx3at p0, (q[0-7]), q0, q1, #15 > ** vmov q0, \1([[:space:]]+@ [^\n]*)? > @@ -1097,8 +1097,8 @@ > */ > /* > ** test_cde_vcx3qa_muint8x16_tint8x16_tuint8x16_t: > -** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r0 @ movhi) > -** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r0 @ movhi) > +** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r0) > +** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r0) > ** vpst > ** vcx3at p0, (q[0-7]), q0, q1, #15 > ** vmov q0, \1([[:space:]]+@ [^\n]*)? > @@ -1106,8 +1106,8 @@ > */ > /* > ** test_cde_vcx3qa_muint8x16_tuint8x16_tint8x16_t: > -** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r0 @ movhi) > -** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r0 @ movhi) > +** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r0) > +** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r0) > ** vpst > ** vcx3at p0, (q[0-7]), q0, q1, #15 > ** vmov q0, \1([[:space:]]+@ [^\n]*)? > @@ -1115,8 +1115,8 @@ > */ > /* > ** test_cde_vcx3qa_mint64x2_tuint8x16_tuint8x16_t: > -** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r0 @ movhi) > -** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r0 @ movhi) > +** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r0) > +** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r0) > ** vpst > ** vcx3at p0, (q[0-7]), q0, q1, #15 > ** vmov q0, \1([[:space:]]+@ [^\n]*)? > @@ -1124,8 +1124,8 @@ > */ > /* > ** test_cde_vcx3qa_muint8x16_tint64x2_tuint8x16_t: > -** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r0 @ movhi) > -** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r0 @ movhi) > +** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r0) > +** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r0) > ** vpst > ** vcx3at p0, (q[0-7]), q0, q1, #15 > ** vmov q0, \1([[:space:]]+@ [^\n]*)? > @@ -1133,8 +1133,8 @@ > */ > /* > ** test_cde_vcx3qa_muint8x16_tuint8x16_tint64x2_t: > -** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r0 @ movhi) > -** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r0 @ movhi) > +** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r0) > +** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r0) > ** vpst > ** vcx3at p0, (q[0-7]), q0, q1, #15 > ** vmov q0, \1([[:space:]]+@ [^\n]*)? > @@ -1142,8 +1142,8 @@ > */ > /* > ** test_cde_vcx3qa_muint8x16_tint64x2_tint64x2_t: > -** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r0 @ movhi) > -** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r0 @ movhi) > +** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r0) > +** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r0) > ** vpst > ** vcx3at p0, (q[0-7]), q0, q1, #15 > ** vmov q0, \1([[:space:]]+@ [^\n]*)? ^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH 10/13] arm: Convert remaining MVE vcmp builtins to predicate qualifiers 2021-09-07 9:20 [PATCH 10/13] arm: Convert remaining MVE vcmp builtins to predicate qualifiers Christophe Lyon ` (2 preceding siblings ...) 2021-09-07 9:21 ` [PATCH 13/13] arm: Convert more MVE/CDE " Christophe Lyon @ 2021-10-11 14:10 ` Richard Sandiford 3 siblings, 0 replies; 9+ messages in thread From: Richard Sandiford @ 2021-10-11 14:10 UTC (permalink / raw) To: Christophe Lyon via Gcc-patches Christophe Lyon via Gcc-patches <gcc-patches@gcc.gnu.org> writes: > This is mostly a mechanical change, only tested by the intrinsics > expansion tests. > > 2021-09-02 Christophe Lyon <christophe.lyon@foss.st.com> > > gcc/ > PR target/100757 > PR target/101325 > * config/arm/arm-builtins.c (BINOP_UNONE_NONE_NONE_QUALIFIERS): > Delete. > (TERNOP_UNONE_NONE_NONE_UNONE_QUALIFIERS): Change to ... > (TERNOP_PRED_NONE_NONE_PRED_QUALIFIERS): ... this. > (TERNOP_PRED_UNONE_UNONE_PRED_QUALIFIERS): New. > * config/arm/arm_mve_builtins.def (vcmp*q_n_, vcmp*q_m_f): Use new > predicated qualifiers. > * config/arm/mve.md (mve_vcmp<mve_cmp_op>q_n_<mode>) > (mve_vcmp*q_m_f<mode>): Use MVE_VPRED instead of HI. OK, thanks. Richard > > diff --git a/gcc/config/arm/arm-builtins.c b/gcc/config/arm/arm-builtins.c > index 6e3638869f1..b3455d87d4f 100644 > --- a/gcc/config/arm/arm-builtins.c > +++ b/gcc/config/arm/arm-builtins.c > @@ -487,12 +487,6 @@ arm_binop_none_none_unone_qualifiers[SIMD_MAX_BUILTIN_ARGS] > #define BINOP_NONE_NONE_UNONE_QUALIFIERS \ > (arm_binop_none_none_unone_qualifiers) > > -static enum arm_type_qualifiers > -arm_binop_unone_none_none_qualifiers[SIMD_MAX_BUILTIN_ARGS] > - = { qualifier_unsigned, qualifier_none, qualifier_none }; > -#define BINOP_UNONE_NONE_NONE_QUALIFIERS \ > - (arm_binop_unone_none_none_qualifiers) > - > static enum arm_type_qualifiers > arm_binop_pred_none_none_qualifiers[SIMD_MAX_BUILTIN_ARGS] > = { qualifier_predicate, qualifier_none, qualifier_none }; > @@ -553,10 +547,10 @@ arm_ternop_unone_unone_imm_unone_qualifiers[SIMD_MAX_BUILTIN_ARGS] > (arm_ternop_unone_unone_imm_unone_qualifiers) > > static enum arm_type_qualifiers > -arm_ternop_unone_none_none_unone_qualifiers[SIMD_MAX_BUILTIN_ARGS] > - = { qualifier_unsigned, qualifier_none, qualifier_none, qualifier_unsigned }; > -#define TERNOP_UNONE_NONE_NONE_UNONE_QUALIFIERS \ > - (arm_ternop_unone_none_none_unone_qualifiers) > +arm_ternop_pred_none_none_pred_qualifiers[SIMD_MAX_BUILTIN_ARGS] > + = { qualifier_predicate, qualifier_none, qualifier_none, qualifier_predicate }; > +#define TERNOP_PRED_NONE_NONE_PRED_QUALIFIERS \ > + (arm_ternop_pred_none_none_pred_qualifiers) > > static enum arm_type_qualifiers > arm_ternop_none_none_none_imm_qualifiers[SIMD_MAX_BUILTIN_ARGS] > @@ -602,6 +596,13 @@ arm_ternop_unone_unone_unone_pred_qualifiers[SIMD_MAX_BUILTIN_ARGS] > #define TERNOP_UNONE_UNONE_UNONE_PRED_QUALIFIERS \ > (arm_ternop_unone_unone_unone_pred_qualifiers) > > +static enum arm_type_qualifiers > +arm_ternop_pred_unone_unone_pred_qualifiers[SIMD_MAX_BUILTIN_ARGS] > + = { qualifier_predicate, qualifier_unsigned, qualifier_unsigned, > + qualifier_predicate }; > +#define TERNOP_PRED_UNONE_UNONE_PRED_QUALIFIERS \ > + (arm_ternop_pred_unone_unone_pred_qualifiers) > + > static enum arm_type_qualifiers > arm_ternop_none_none_none_none_qualifiers[SIMD_MAX_BUILTIN_ARGS] > = { qualifier_none, qualifier_none, qualifier_none, qualifier_none }; > diff --git a/gcc/config/arm/arm_mve_builtins.def b/gcc/config/arm/arm_mve_builtins.def > index 58a05e61bd9..91ed2073918 100644 > --- a/gcc/config/arm/arm_mve_builtins.def > +++ b/gcc/config/arm/arm_mve_builtins.def > @@ -118,9 +118,9 @@ VAR3 (BINOP_UNONE_UNONE_UNONE, vhaddq_u, v16qi, v8hi, v4si) > VAR3 (BINOP_UNONE_UNONE_UNONE, vhaddq_n_u, v16qi, v8hi, v4si) > VAR3 (BINOP_UNONE_UNONE_UNONE, veorq_u, v16qi, v8hi, v4si) > VAR3 (BINOP_PRED_UNONE_UNONE, vcmphiq_, v16qi, v8hi, v4si) > -VAR3 (BINOP_UNONE_UNONE_UNONE, vcmphiq_n_, v16qi, v8hi, v4si) > +VAR3 (BINOP_PRED_UNONE_UNONE, vcmphiq_n_, v16qi, v8hi, v4si) > VAR3 (BINOP_PRED_UNONE_UNONE, vcmpcsq_, v16qi, v8hi, v4si) > -VAR3 (BINOP_UNONE_UNONE_UNONE, vcmpcsq_n_, v16qi, v8hi, v4si) > +VAR3 (BINOP_PRED_UNONE_UNONE, vcmpcsq_n_, v16qi, v8hi, v4si) > VAR3 (BINOP_UNONE_UNONE_UNONE, vbicq_u, v16qi, v8hi, v4si) > VAR3 (BINOP_UNONE_UNONE_UNONE, vandq_u, v16qi, v8hi, v4si) > VAR3 (BINOP_UNONE_UNONE_UNONE, vaddvq_p_u, v16qi, v8hi, v4si) > @@ -142,17 +142,17 @@ VAR3 (BINOP_UNONE_UNONE_NONE, vbrsrq_n_u, v16qi, v8hi, v4si) > VAR3 (BINOP_UNONE_UNONE_IMM, vshlq_n_u, v16qi, v8hi, v4si) > VAR3 (BINOP_UNONE_UNONE_IMM, vrshrq_n_u, v16qi, v8hi, v4si) > VAR3 (BINOP_UNONE_UNONE_IMM, vqshlq_n_u, v16qi, v8hi, v4si) > -VAR3 (BINOP_UNONE_NONE_NONE, vcmpneq_n_, v16qi, v8hi, v4si) > +VAR3 (BINOP_PRED_NONE_NONE, vcmpneq_n_, v16qi, v8hi, v4si) > VAR3 (BINOP_PRED_NONE_NONE, vcmpltq_, v16qi, v8hi, v4si) > -VAR3 (BINOP_UNONE_NONE_NONE, vcmpltq_n_, v16qi, v8hi, v4si) > +VAR3 (BINOP_PRED_NONE_NONE, vcmpltq_n_, v16qi, v8hi, v4si) > VAR3 (BINOP_PRED_NONE_NONE, vcmpleq_, v16qi, v8hi, v4si) > -VAR3 (BINOP_UNONE_NONE_NONE, vcmpleq_n_, v16qi, v8hi, v4si) > +VAR3 (BINOP_PRED_NONE_NONE, vcmpleq_n_, v16qi, v8hi, v4si) > VAR3 (BINOP_PRED_NONE_NONE, vcmpgtq_, v16qi, v8hi, v4si) > -VAR3 (BINOP_UNONE_NONE_NONE, vcmpgtq_n_, v16qi, v8hi, v4si) > +VAR3 (BINOP_PRED_NONE_NONE, vcmpgtq_n_, v16qi, v8hi, v4si) > VAR3 (BINOP_PRED_NONE_NONE, vcmpgeq_, v16qi, v8hi, v4si) > -VAR3 (BINOP_UNONE_NONE_NONE, vcmpgeq_n_, v16qi, v8hi, v4si) > +VAR3 (BINOP_PRED_NONE_NONE, vcmpgeq_n_, v16qi, v8hi, v4si) > VAR3 (BINOP_PRED_NONE_NONE, vcmpeqq_, v16qi, v8hi, v4si) > -VAR3 (BINOP_UNONE_NONE_NONE, vcmpeqq_n_, v16qi, v8hi, v4si) > +VAR3 (BINOP_PRED_NONE_NONE, vcmpeqq_n_, v16qi, v8hi, v4si) > VAR3 (BINOP_UNONE_NONE_IMM, vqshluq_n_s, v16qi, v8hi, v4si) > VAR3 (BINOP_NONE_NONE_UNONE, vaddvq_p_s, v16qi, v8hi, v4si) > VAR3 (BINOP_NONE_NONE_NONE, vsubq_s, v16qi, v8hi, v4si) > @@ -218,17 +218,17 @@ VAR2 (BINOP_UNONE_UNONE_IMM, vshlltq_n_u, v16qi, v8hi) > VAR2 (BINOP_UNONE_UNONE_IMM, vshllbq_n_u, v16qi, v8hi) > VAR2 (BINOP_UNONE_UNONE_IMM, vorrq_n_u, v8hi, v4si) > VAR2 (BINOP_UNONE_UNONE_IMM, vbicq_n_u, v8hi, v4si) > -VAR2 (BINOP_UNONE_NONE_NONE, vcmpneq_n_f, v8hf, v4sf) > +VAR2 (BINOP_PRED_NONE_NONE, vcmpneq_n_f, v8hf, v4sf) > VAR2 (BINOP_PRED_NONE_NONE, vcmpneq_f, v8hf, v4sf) > -VAR2 (BINOP_UNONE_NONE_NONE, vcmpltq_n_f, v8hf, v4sf) > +VAR2 (BINOP_PRED_NONE_NONE, vcmpltq_n_f, v8hf, v4sf) > VAR2 (BINOP_PRED_NONE_NONE, vcmpltq_f, v8hf, v4sf) > -VAR2 (BINOP_UNONE_NONE_NONE, vcmpleq_n_f, v8hf, v4sf) > +VAR2 (BINOP_PRED_NONE_NONE, vcmpleq_n_f, v8hf, v4sf) > VAR2 (BINOP_PRED_NONE_NONE, vcmpleq_f, v8hf, v4sf) > -VAR2 (BINOP_UNONE_NONE_NONE, vcmpgtq_n_f, v8hf, v4sf) > +VAR2 (BINOP_PRED_NONE_NONE, vcmpgtq_n_f, v8hf, v4sf) > VAR2 (BINOP_PRED_NONE_NONE, vcmpgtq_f, v8hf, v4sf) > -VAR2 (BINOP_UNONE_NONE_NONE, vcmpgeq_n_f, v8hf, v4sf) > +VAR2 (BINOP_PRED_NONE_NONE, vcmpgeq_n_f, v8hf, v4sf) > VAR2 (BINOP_PRED_NONE_NONE, vcmpgeq_f, v8hf, v4sf) > -VAR2 (BINOP_UNONE_NONE_NONE, vcmpeqq_n_f, v8hf, v4sf) > +VAR2 (BINOP_PRED_NONE_NONE, vcmpeqq_n_f, v8hf, v4sf) > VAR2 (BINOP_PRED_NONE_NONE, vcmpeqq_f, v8hf, v4sf) > VAR2 (BINOP_NONE_NONE_NONE, vsubq_f, v8hf, v4sf) > VAR2 (BINOP_NONE_NONE_NONE, vqmovntq_s, v8hi, v4si) > @@ -285,7 +285,7 @@ VAR1 (TERNOP_NONE_NONE_NONE_NONE, vrmlaldavhaq_s, v4si) > VAR1 (TERNOP_UNONE_UNONE_UNONE_UNONE, vrmlaldavhaq_u, v4si) > VAR2 (TERNOP_NONE_NONE_UNONE_UNONE, vcvtq_m_to_f_u, v8hf, v4sf) > VAR2 (TERNOP_NONE_NONE_NONE_UNONE, vcvtq_m_to_f_s, v8hf, v4sf) > -VAR2 (TERNOP_UNONE_NONE_NONE_UNONE, vcmpeqq_m_f, v8hf, v4sf) > +VAR2 (TERNOP_PRED_NONE_NONE_PRED, vcmpeqq_m_f, v8hf, v4sf) > VAR3 (TERNOP_UNONE_NONE_UNONE_IMM, vshlcq_carry_s, v16qi, v8hi, v4si) > VAR3 (TERNOP_UNONE_UNONE_UNONE_IMM, vshlcq_carry_u, v16qi, v8hi, v4si) > VAR2 (TERNOP_UNONE_UNONE_NONE_IMM, vqrshrunbq_n_s, v8hi, v4si) > @@ -306,14 +306,14 @@ VAR3 (TERNOP_UNONE_UNONE_UNONE_UNONE, vmladavaq_u, v16qi, v8hi, v4si) > VAR3 (TERNOP_UNONE_UNONE_UNONE_UNONE, vminvq_p_u, v16qi, v8hi, v4si) > VAR3 (TERNOP_UNONE_UNONE_UNONE_UNONE, vmaxvq_p_u, v16qi, v8hi, v4si) > VAR3 (TERNOP_UNONE_UNONE_UNONE_UNONE, vdupq_m_n_u, v16qi, v8hi, v4si) > -VAR3 (TERNOP_UNONE_UNONE_UNONE_UNONE, vcmpneq_m_u, v16qi, v8hi, v4si) > -VAR3 (TERNOP_UNONE_UNONE_UNONE_UNONE, vcmpneq_m_n_u, v16qi, v8hi, v4si) > -VAR3 (TERNOP_UNONE_UNONE_UNONE_UNONE, vcmphiq_m_u, v16qi, v8hi, v4si) > -VAR3 (TERNOP_UNONE_UNONE_UNONE_UNONE, vcmphiq_m_n_u, v16qi, v8hi, v4si) > -VAR3 (TERNOP_UNONE_UNONE_UNONE_UNONE, vcmpeqq_m_u, v16qi, v8hi, v4si) > -VAR3 (TERNOP_UNONE_UNONE_UNONE_UNONE, vcmpeqq_m_n_u, v16qi, v8hi, v4si) > -VAR3 (TERNOP_UNONE_UNONE_UNONE_UNONE, vcmpcsq_m_u, v16qi, v8hi, v4si) > -VAR3 (TERNOP_UNONE_UNONE_UNONE_UNONE, vcmpcsq_m_n_u, v16qi, v8hi, v4si) > +VAR3 (TERNOP_PRED_UNONE_UNONE_PRED, vcmpneq_m_u, v16qi, v8hi, v4si) > +VAR3 (TERNOP_PRED_UNONE_UNONE_PRED, vcmpneq_m_n_u, v16qi, v8hi, v4si) > +VAR3 (TERNOP_PRED_UNONE_UNONE_PRED, vcmphiq_m_u, v16qi, v8hi, v4si) > +VAR3 (TERNOP_PRED_UNONE_UNONE_PRED, vcmphiq_m_n_u, v16qi, v8hi, v4si) > +VAR3 (TERNOP_PRED_UNONE_UNONE_PRED, vcmpeqq_m_u, v16qi, v8hi, v4si) > +VAR3 (TERNOP_PRED_UNONE_UNONE_PRED, vcmpeqq_m_n_u, v16qi, v8hi, v4si) > +VAR3 (TERNOP_PRED_UNONE_UNONE_PRED, vcmpcsq_m_u, v16qi, v8hi, v4si) > +VAR3 (TERNOP_PRED_UNONE_UNONE_PRED, vcmpcsq_m_n_u, v16qi, v8hi, v4si) > VAR3 (TERNOP_UNONE_UNONE_UNONE_UNONE, vclzq_m_u, v16qi, v8hi, v4si) > VAR3 (TERNOP_UNONE_UNONE_UNONE_UNONE, vaddvaq_p_u, v16qi, v8hi, v4si) > VAR3 (TERNOP_UNONE_UNONE_UNONE_IMM, vsriq_n_u, v16qi, v8hi, v4si) > @@ -326,18 +326,18 @@ VAR3 (TERNOP_UNONE_UNONE_NONE_UNONE, vminavq_p_s, v16qi, v8hi, v4si) > VAR3 (TERNOP_UNONE_UNONE_NONE_UNONE, vminaq_m_s, v16qi, v8hi, v4si) > VAR3 (TERNOP_UNONE_UNONE_NONE_UNONE, vmaxavq_p_s, v16qi, v8hi, v4si) > VAR3 (TERNOP_UNONE_UNONE_NONE_UNONE, vmaxaq_m_s, v16qi, v8hi, v4si) > -VAR3 (TERNOP_UNONE_NONE_NONE_UNONE, vcmpneq_m_s, v16qi, v8hi, v4si) > -VAR3 (TERNOP_UNONE_NONE_NONE_UNONE, vcmpneq_m_n_s, v16qi, v8hi, v4si) > -VAR3 (TERNOP_UNONE_NONE_NONE_UNONE, vcmpltq_m_s, v16qi, v8hi, v4si) > -VAR3 (TERNOP_UNONE_NONE_NONE_UNONE, vcmpltq_m_n_s, v16qi, v8hi, v4si) > -VAR3 (TERNOP_UNONE_NONE_NONE_UNONE, vcmpleq_m_s, v16qi, v8hi, v4si) > -VAR3 (TERNOP_UNONE_NONE_NONE_UNONE, vcmpleq_m_n_s, v16qi, v8hi, v4si) > -VAR3 (TERNOP_UNONE_NONE_NONE_UNONE, vcmpgtq_m_s, v16qi, v8hi, v4si) > -VAR3 (TERNOP_UNONE_NONE_NONE_UNONE, vcmpgtq_m_n_s, v16qi, v8hi, v4si) > -VAR3 (TERNOP_UNONE_NONE_NONE_UNONE, vcmpgeq_m_s, v16qi, v8hi, v4si) > -VAR3 (TERNOP_UNONE_NONE_NONE_UNONE, vcmpgeq_m_n_s, v16qi, v8hi, v4si) > -VAR3 (TERNOP_UNONE_NONE_NONE_UNONE, vcmpeqq_m_s, v16qi, v8hi, v4si) > -VAR3 (TERNOP_UNONE_NONE_NONE_UNONE, vcmpeqq_m_n_s, v16qi, v8hi, v4si) > +VAR3 (TERNOP_PRED_NONE_NONE_PRED, vcmpneq_m_s, v16qi, v8hi, v4si) > +VAR3 (TERNOP_PRED_NONE_NONE_PRED, vcmpneq_m_n_s, v16qi, v8hi, v4si) > +VAR3 (TERNOP_PRED_NONE_NONE_PRED, vcmpltq_m_s, v16qi, v8hi, v4si) > +VAR3 (TERNOP_PRED_NONE_NONE_PRED, vcmpltq_m_n_s, v16qi, v8hi, v4si) > +VAR3 (TERNOP_PRED_NONE_NONE_PRED, vcmpleq_m_s, v16qi, v8hi, v4si) > +VAR3 (TERNOP_PRED_NONE_NONE_PRED, vcmpleq_m_n_s, v16qi, v8hi, v4si) > +VAR3 (TERNOP_PRED_NONE_NONE_PRED, vcmpgtq_m_s, v16qi, v8hi, v4si) > +VAR3 (TERNOP_PRED_NONE_NONE_PRED, vcmpgtq_m_n_s, v16qi, v8hi, v4si) > +VAR3 (TERNOP_PRED_NONE_NONE_PRED, vcmpgeq_m_s, v16qi, v8hi, v4si) > +VAR3 (TERNOP_PRED_NONE_NONE_PRED, vcmpgeq_m_n_s, v16qi, v8hi, v4si) > +VAR3 (TERNOP_PRED_NONE_NONE_PRED, vcmpeqq_m_s, v16qi, v8hi, v4si) > +VAR3 (TERNOP_PRED_NONE_NONE_PRED, vcmpeqq_m_n_s, v16qi, v8hi, v4si) > VAR3 (TERNOP_NONE_NONE_NONE_UNONE, vshlq_m_r_s, v16qi, v8hi, v4si) > VAR3 (TERNOP_NONE_NONE_NONE_UNONE, vrshlq_m_n_s, v16qi, v8hi, v4si) > VAR3 (TERNOP_NONE_NONE_NONE_UNONE, vrev64q_m_s, v16qi, v8hi, v4si) > @@ -405,17 +405,17 @@ VAR2 (TERNOP_UNONE_UNONE_NONE_IMM, vqshrunbq_n_s, v8hi, v4si) > VAR2 (TERNOP_UNONE_UNONE_NONE_IMM, vqrshruntq_n_s, v8hi, v4si) > VAR2 (TERNOP_UNONE_UNONE_IMM_UNONE, vorrq_m_n_u, v8hi, v4si) > VAR2 (TERNOP_UNONE_UNONE_IMM_UNONE, vmvnq_m_n_u, v8hi, v4si) > -VAR2 (TERNOP_UNONE_NONE_NONE_UNONE, vcmpneq_m_n_f, v8hf, v4sf) > -VAR2 (TERNOP_UNONE_NONE_NONE_UNONE, vcmpneq_m_f, v8hf, v4sf) > -VAR2 (TERNOP_UNONE_NONE_NONE_UNONE, vcmpltq_m_n_f, v8hf, v4sf) > -VAR2 (TERNOP_UNONE_NONE_NONE_UNONE, vcmpltq_m_f, v8hf, v4sf) > -VAR2 (TERNOP_UNONE_NONE_NONE_UNONE, vcmpleq_m_n_f, v8hf, v4sf) > -VAR2 (TERNOP_UNONE_NONE_NONE_UNONE, vcmpleq_m_f, v8hf, v4sf) > -VAR2 (TERNOP_UNONE_NONE_NONE_UNONE, vcmpgtq_m_n_f, v8hf, v4sf) > -VAR2 (TERNOP_UNONE_NONE_NONE_UNONE, vcmpgtq_m_f, v8hf, v4sf) > -VAR2 (TERNOP_UNONE_NONE_NONE_UNONE, vcmpgeq_m_n_f, v8hf, v4sf) > -VAR2 (TERNOP_UNONE_NONE_NONE_UNONE, vcmpgeq_m_f, v8hf, v4sf) > -VAR2 (TERNOP_UNONE_NONE_NONE_UNONE, vcmpeqq_m_n_f, v8hf, v4sf) > +VAR2 (TERNOP_PRED_NONE_NONE_PRED, vcmpneq_m_n_f, v8hf, v4sf) > +VAR2 (TERNOP_PRED_NONE_NONE_PRED, vcmpneq_m_f, v8hf, v4sf) > +VAR2 (TERNOP_PRED_NONE_NONE_PRED, vcmpltq_m_n_f, v8hf, v4sf) > +VAR2 (TERNOP_PRED_NONE_NONE_PRED, vcmpltq_m_f, v8hf, v4sf) > +VAR2 (TERNOP_PRED_NONE_NONE_PRED, vcmpleq_m_n_f, v8hf, v4sf) > +VAR2 (TERNOP_PRED_NONE_NONE_PRED, vcmpleq_m_f, v8hf, v4sf) > +VAR2 (TERNOP_PRED_NONE_NONE_PRED, vcmpgtq_m_n_f, v8hf, v4sf) > +VAR2 (TERNOP_PRED_NONE_NONE_PRED, vcmpgtq_m_f, v8hf, v4sf) > +VAR2 (TERNOP_PRED_NONE_NONE_PRED, vcmpgeq_m_n_f, v8hf, v4sf) > +VAR2 (TERNOP_PRED_NONE_NONE_PRED, vcmpgeq_m_f, v8hf, v4sf) > +VAR2 (TERNOP_PRED_NONE_NONE_PRED, vcmpeqq_m_n_f, v8hf, v4sf) > VAR2 (TERNOP_NONE_NONE_NONE_UNONE, vrndxq_m_f, v8hf, v4sf) > VAR2 (TERNOP_NONE_NONE_NONE_UNONE, vrndq_m_f, v8hf, v4sf) > VAR2 (TERNOP_NONE_NONE_NONE_UNONE, vrndpq_m_f, v8hf, v4sf) > diff --git a/gcc/config/arm/mve.md b/gcc/config/arm/mve.md > index d663c698cfb..4867aa79687 100644 > --- a/gcc/config/arm/mve.md > +++ b/gcc/config/arm/mve.md > @@ -853,8 +853,8 @@ (define_insn "@mve_vcmp<mve_cmp_op>q_<mode>" > ;; > (define_insn "mve_vcmp<mve_cmp_op>q_n_<mode>" > [ > - (set (match_operand:HI 0 "vpr_register_operand" "=Up") > - (MVE_COMPARISONS:HI (match_operand:MVE_2 1 "s_register_operand" "w") > + (set (match_operand:<MVE_VPRED> 0 "vpr_register_operand" "=Up") > + (MVE_COMPARISONS:<MVE_VPRED> (match_operand:MVE_2 1 "s_register_operand" "w") > (match_operand:<V_elem> 2 "s_register_operand" "r"))) > ] > "TARGET_HAVE_MVE" > @@ -1943,8 +1943,8 @@ (define_insn "@mve_vcmp<mve_cmp_op>q_f<mode>" > ;; > (define_insn "@mve_vcmp<mve_cmp_op>q_n_f<mode>" > [ > - (set (match_operand:HI 0 "vpr_register_operand" "=Up") > - (MVE_FP_COMPARISONS:HI (match_operand:MVE_0 1 "s_register_operand" "w") > + (set (match_operand:<MVE_VPRED> 0 "vpr_register_operand" "=Up") > + (MVE_FP_COMPARISONS:<MVE_VPRED> (match_operand:MVE_0 1 "s_register_operand" "w") > (match_operand:<V_elem> 2 "s_register_operand" "r"))) > ] > "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" > @@ -2593,10 +2593,10 @@ (define_insn "mve_vbicq_m_n_<supf><mode>" > ;; > (define_insn "mve_vcmpeqq_m_f<mode>" > [ > - (set (match_operand:HI 0 "vpr_register_operand" "=Up") > - (unspec:HI [(match_operand:MVE_0 1 "s_register_operand" "w") > + (set (match_operand:<MVE_VPRED> 0 "vpr_register_operand" "=Up") > + (unspec:<MVE_VPRED> [(match_operand:MVE_0 1 "s_register_operand" "w") > (match_operand:MVE_0 2 "s_register_operand" "w") > - (match_operand:HI 3 "vpr_register_operand" "Up")] > + (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")] > VCMPEQQ_M_F)) > ] > "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" > @@ -2809,10 +2809,10 @@ (define_insn "mve_vclzq_m_<supf><mode>" > ;; > (define_insn "mve_vcmpcsq_m_n_u<mode>" > [ > - (set (match_operand:HI 0 "vpr_register_operand" "=Up") > - (unspec:HI [(match_operand:MVE_2 1 "s_register_operand" "w") > + (set (match_operand:<MVE_VPRED> 0 "vpr_register_operand" "=Up") > + (unspec:<MVE_VPRED> [(match_operand:MVE_2 1 "s_register_operand" "w") > (match_operand:<V_elem> 2 "s_register_operand" "r") > - (match_operand:HI 3 "vpr_register_operand" "Up")] > + (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")] > VCMPCSQ_M_N_U)) > ] > "TARGET_HAVE_MVE" > @@ -2825,10 +2825,10 @@ (define_insn "mve_vcmpcsq_m_n_u<mode>" > ;; > (define_insn "mve_vcmpcsq_m_u<mode>" > [ > - (set (match_operand:HI 0 "vpr_register_operand" "=Up") > - (unspec:HI [(match_operand:MVE_2 1 "s_register_operand" "w") > + (set (match_operand:<MVE_VPRED> 0 "vpr_register_operand" "=Up") > + (unspec:<MVE_VPRED> [(match_operand:MVE_2 1 "s_register_operand" "w") > (match_operand:MVE_2 2 "s_register_operand" "w") > - (match_operand:HI 3 "vpr_register_operand" "Up")] > + (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")] > VCMPCSQ_M_U)) > ] > "TARGET_HAVE_MVE" > @@ -2841,10 +2841,10 @@ (define_insn "mve_vcmpcsq_m_u<mode>" > ;; > (define_insn "mve_vcmpeqq_m_n_<supf><mode>" > [ > - (set (match_operand:HI 0 "vpr_register_operand" "=Up") > - (unspec:HI [(match_operand:MVE_2 1 "s_register_operand" "w") > + (set (match_operand:<MVE_VPRED> 0 "vpr_register_operand" "=Up") > + (unspec:<MVE_VPRED> [(match_operand:MVE_2 1 "s_register_operand" "w") > (match_operand:<V_elem> 2 "s_register_operand" "r") > - (match_operand:HI 3 "vpr_register_operand" "Up")] > + (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")] > VCMPEQQ_M_N)) > ] > "TARGET_HAVE_MVE" > @@ -2857,10 +2857,10 @@ (define_insn "mve_vcmpeqq_m_n_<supf><mode>" > ;; > (define_insn "mve_vcmpeqq_m_<supf><mode>" > [ > - (set (match_operand:HI 0 "vpr_register_operand" "=Up") > - (unspec:HI [(match_operand:MVE_2 1 "s_register_operand" "w") > + (set (match_operand:<MVE_VPRED> 0 "vpr_register_operand" "=Up") > + (unspec:<MVE_VPRED> [(match_operand:MVE_2 1 "s_register_operand" "w") > (match_operand:MVE_2 2 "s_register_operand" "w") > - (match_operand:HI 3 "vpr_register_operand" "Up")] > + (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")] > VCMPEQQ_M)) > ] > "TARGET_HAVE_MVE" > @@ -2873,10 +2873,10 @@ (define_insn "mve_vcmpeqq_m_<supf><mode>" > ;; > (define_insn "mve_vcmpgeq_m_n_s<mode>" > [ > - (set (match_operand:HI 0 "vpr_register_operand" "=Up") > - (unspec:HI [(match_operand:MVE_2 1 "s_register_operand" "w") > + (set (match_operand:<MVE_VPRED> 0 "vpr_register_operand" "=Up") > + (unspec:<MVE_VPRED> [(match_operand:MVE_2 1 "s_register_operand" "w") > (match_operand:<V_elem> 2 "s_register_operand" "r") > - (match_operand:HI 3 "vpr_register_operand" "Up")] > + (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")] > VCMPGEQ_M_N_S)) > ] > "TARGET_HAVE_MVE" > @@ -2889,10 +2889,10 @@ (define_insn "mve_vcmpgeq_m_n_s<mode>" > ;; > (define_insn "mve_vcmpgeq_m_s<mode>" > [ > - (set (match_operand:HI 0 "vpr_register_operand" "=Up") > - (unspec:HI [(match_operand:MVE_2 1 "s_register_operand" "w") > + (set (match_operand:<MVE_VPRED> 0 "vpr_register_operand" "=Up") > + (unspec:<MVE_VPRED> [(match_operand:MVE_2 1 "s_register_operand" "w") > (match_operand:MVE_2 2 "s_register_operand" "w") > - (match_operand:HI 3 "vpr_register_operand" "Up")] > + (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")] > VCMPGEQ_M_S)) > ] > "TARGET_HAVE_MVE" > @@ -2905,10 +2905,10 @@ (define_insn "mve_vcmpgeq_m_s<mode>" > ;; > (define_insn "mve_vcmpgtq_m_n_s<mode>" > [ > - (set (match_operand:HI 0 "vpr_register_operand" "=Up") > - (unspec:HI [(match_operand:MVE_2 1 "s_register_operand" "w") > + (set (match_operand:<MVE_VPRED> 0 "vpr_register_operand" "=Up") > + (unspec:<MVE_VPRED> [(match_operand:MVE_2 1 "s_register_operand" "w") > (match_operand:<V_elem> 2 "s_register_operand" "r") > - (match_operand:HI 3 "vpr_register_operand" "Up")] > + (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")] > VCMPGTQ_M_N_S)) > ] > "TARGET_HAVE_MVE" > @@ -2921,10 +2921,10 @@ (define_insn "mve_vcmpgtq_m_n_s<mode>" > ;; > (define_insn "mve_vcmpgtq_m_s<mode>" > [ > - (set (match_operand:HI 0 "vpr_register_operand" "=Up") > - (unspec:HI [(match_operand:MVE_2 1 "s_register_operand" "w") > + (set (match_operand:<MVE_VPRED> 0 "vpr_register_operand" "=Up") > + (unspec:<MVE_VPRED> [(match_operand:MVE_2 1 "s_register_operand" "w") > (match_operand:MVE_2 2 "s_register_operand" "w") > - (match_operand:HI 3 "vpr_register_operand" "Up")] > + (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")] > VCMPGTQ_M_S)) > ] > "TARGET_HAVE_MVE" > @@ -2937,10 +2937,10 @@ (define_insn "mve_vcmpgtq_m_s<mode>" > ;; > (define_insn "mve_vcmphiq_m_n_u<mode>" > [ > - (set (match_operand:HI 0 "vpr_register_operand" "=Up") > - (unspec:HI [(match_operand:MVE_2 1 "s_register_operand" "w") > + (set (match_operand:<MVE_VPRED> 0 "vpr_register_operand" "=Up") > + (unspec:<MVE_VPRED> [(match_operand:MVE_2 1 "s_register_operand" "w") > (match_operand:<V_elem> 2 "s_register_operand" "r") > - (match_operand:HI 3 "vpr_register_operand" "Up")] > + (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")] > VCMPHIQ_M_N_U)) > ] > "TARGET_HAVE_MVE" > @@ -2953,10 +2953,10 @@ (define_insn "mve_vcmphiq_m_n_u<mode>" > ;; > (define_insn "mve_vcmphiq_m_u<mode>" > [ > - (set (match_operand:HI 0 "vpr_register_operand" "=Up") > - (unspec:HI [(match_operand:MVE_2 1 "s_register_operand" "w") > + (set (match_operand:<MVE_VPRED> 0 "vpr_register_operand" "=Up") > + (unspec:<MVE_VPRED> [(match_operand:MVE_2 1 "s_register_operand" "w") > (match_operand:MVE_2 2 "s_register_operand" "w") > - (match_operand:HI 3 "vpr_register_operand" "Up")] > + (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")] > VCMPHIQ_M_U)) > ] > "TARGET_HAVE_MVE" > @@ -2969,10 +2969,10 @@ (define_insn "mve_vcmphiq_m_u<mode>" > ;; > (define_insn "mve_vcmpleq_m_n_s<mode>" > [ > - (set (match_operand:HI 0 "vpr_register_operand" "=Up") > - (unspec:HI [(match_operand:MVE_2 1 "s_register_operand" "w") > + (set (match_operand:<MVE_VPRED> 0 "vpr_register_operand" "=Up") > + (unspec:<MVE_VPRED> [(match_operand:MVE_2 1 "s_register_operand" "w") > (match_operand:<V_elem> 2 "s_register_operand" "r") > - (match_operand:HI 3 "vpr_register_operand" "Up")] > + (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")] > VCMPLEQ_M_N_S)) > ] > "TARGET_HAVE_MVE" > @@ -2985,10 +2985,10 @@ (define_insn "mve_vcmpleq_m_n_s<mode>" > ;; > (define_insn "mve_vcmpleq_m_s<mode>" > [ > - (set (match_operand:HI 0 "vpr_register_operand" "=Up") > - (unspec:HI [(match_operand:MVE_2 1 "s_register_operand" "w") > + (set (match_operand:<MVE_VPRED> 0 "vpr_register_operand" "=Up") > + (unspec:<MVE_VPRED> [(match_operand:MVE_2 1 "s_register_operand" "w") > (match_operand:MVE_2 2 "s_register_operand" "w") > - (match_operand:HI 3 "vpr_register_operand" "Up")] > + (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")] > VCMPLEQ_M_S)) > ] > "TARGET_HAVE_MVE" > @@ -3001,10 +3001,10 @@ (define_insn "mve_vcmpleq_m_s<mode>" > ;; > (define_insn "mve_vcmpltq_m_n_s<mode>" > [ > - (set (match_operand:HI 0 "vpr_register_operand" "=Up") > - (unspec:HI [(match_operand:MVE_2 1 "s_register_operand" "w") > + (set (match_operand:<MVE_VPRED> 0 "vpr_register_operand" "=Up") > + (unspec:<MVE_VPRED> [(match_operand:MVE_2 1 "s_register_operand" "w") > (match_operand:<V_elem> 2 "s_register_operand" "r") > - (match_operand:HI 3 "vpr_register_operand" "Up")] > + (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")] > VCMPLTQ_M_N_S)) > ] > "TARGET_HAVE_MVE" > @@ -3017,10 +3017,10 @@ (define_insn "mve_vcmpltq_m_n_s<mode>" > ;; > (define_insn "mve_vcmpltq_m_s<mode>" > [ > - (set (match_operand:HI 0 "vpr_register_operand" "=Up") > - (unspec:HI [(match_operand:MVE_2 1 "s_register_operand" "w") > + (set (match_operand:<MVE_VPRED> 0 "vpr_register_operand" "=Up") > + (unspec:<MVE_VPRED> [(match_operand:MVE_2 1 "s_register_operand" "w") > (match_operand:MVE_2 2 "s_register_operand" "w") > - (match_operand:HI 3 "vpr_register_operand" "Up")] > + (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")] > VCMPLTQ_M_S)) > ] > "TARGET_HAVE_MVE" > @@ -3033,10 +3033,10 @@ (define_insn "mve_vcmpltq_m_s<mode>" > ;; > (define_insn "mve_vcmpneq_m_n_<supf><mode>" > [ > - (set (match_operand:HI 0 "vpr_register_operand" "=Up") > - (unspec:HI [(match_operand:MVE_2 1 "s_register_operand" "w") > + (set (match_operand:<MVE_VPRED> 0 "vpr_register_operand" "=Up") > + (unspec:<MVE_VPRED> [(match_operand:MVE_2 1 "s_register_operand" "w") > (match_operand:<V_elem> 2 "s_register_operand" "r") > - (match_operand:HI 3 "vpr_register_operand" "Up")] > + (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")] > VCMPNEQ_M_N)) > ] > "TARGET_HAVE_MVE" > @@ -3049,10 +3049,10 @@ (define_insn "mve_vcmpneq_m_n_<supf><mode>" > ;; > (define_insn "mve_vcmpneq_m_<supf><mode>" > [ > - (set (match_operand:HI 0 "vpr_register_operand" "=Up") > - (unspec:HI [(match_operand:MVE_2 1 "s_register_operand" "w") > + (set (match_operand:<MVE_VPRED> 0 "vpr_register_operand" "=Up") > + (unspec:<MVE_VPRED> [(match_operand:MVE_2 1 "s_register_operand" "w") > (match_operand:MVE_2 2 "s_register_operand" "w") > - (match_operand:HI 3 "vpr_register_operand" "Up")] > + (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")] > VCMPNEQ_M)) > ] > "TARGET_HAVE_MVE" > @@ -3782,10 +3782,10 @@ (define_insn "mve_vcmlaq<mve_rot><mode>" > ;; > (define_insn "mve_vcmpeqq_m_n_f<mode>" > [ > - (set (match_operand:HI 0 "vpr_register_operand" "=Up") > - (unspec:HI [(match_operand:MVE_0 1 "s_register_operand" "w") > + (set (match_operand:<MVE_VPRED> 0 "vpr_register_operand" "=Up") > + (unspec:<MVE_VPRED> [(match_operand:MVE_0 1 "s_register_operand" "w") > (match_operand:<V_elem> 2 "s_register_operand" "r") > - (match_operand:HI 3 "vpr_register_operand" "Up")] > + (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")] > VCMPEQQ_M_N_F)) > ] > "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" > @@ -3798,10 +3798,10 @@ (define_insn "mve_vcmpeqq_m_n_f<mode>" > ;; > (define_insn "mve_vcmpgeq_m_f<mode>" > [ > - (set (match_operand:HI 0 "vpr_register_operand" "=Up") > - (unspec:HI [(match_operand:MVE_0 1 "s_register_operand" "w") > + (set (match_operand:<MVE_VPRED> 0 "vpr_register_operand" "=Up") > + (unspec:<MVE_VPRED> [(match_operand:MVE_0 1 "s_register_operand" "w") > (match_operand:MVE_0 2 "s_register_operand" "w") > - (match_operand:HI 3 "vpr_register_operand" "Up")] > + (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")] > VCMPGEQ_M_F)) > ] > "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" > @@ -3814,10 +3814,10 @@ (define_insn "mve_vcmpgeq_m_f<mode>" > ;; > (define_insn "mve_vcmpgeq_m_n_f<mode>" > [ > - (set (match_operand:HI 0 "vpr_register_operand" "=Up") > - (unspec:HI [(match_operand:MVE_0 1 "s_register_operand" "w") > + (set (match_operand:<MVE_VPRED> 0 "vpr_register_operand" "=Up") > + (unspec:<MVE_VPRED> [(match_operand:MVE_0 1 "s_register_operand" "w") > (match_operand:<V_elem> 2 "s_register_operand" "r") > - (match_operand:HI 3 "vpr_register_operand" "Up")] > + (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")] > VCMPGEQ_M_N_F)) > ] > "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" > @@ -3830,10 +3830,10 @@ (define_insn "mve_vcmpgeq_m_n_f<mode>" > ;; > (define_insn "mve_vcmpgtq_m_f<mode>" > [ > - (set (match_operand:HI 0 "vpr_register_operand" "=Up") > - (unspec:HI [(match_operand:MVE_0 1 "s_register_operand" "w") > + (set (match_operand:<MVE_VPRED> 0 "vpr_register_operand" "=Up") > + (unspec:<MVE_VPRED> [(match_operand:MVE_0 1 "s_register_operand" "w") > (match_operand:MVE_0 2 "s_register_operand" "w") > - (match_operand:HI 3 "vpr_register_operand" "Up")] > + (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")] > VCMPGTQ_M_F)) > ] > "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" > @@ -3846,10 +3846,10 @@ (define_insn "mve_vcmpgtq_m_f<mode>" > ;; > (define_insn "mve_vcmpgtq_m_n_f<mode>" > [ > - (set (match_operand:HI 0 "vpr_register_operand" "=Up") > - (unspec:HI [(match_operand:MVE_0 1 "s_register_operand" "w") > + (set (match_operand:<MVE_VPRED> 0 "vpr_register_operand" "=Up") > + (unspec:<MVE_VPRED> [(match_operand:MVE_0 1 "s_register_operand" "w") > (match_operand:<V_elem> 2 "s_register_operand" "r") > - (match_operand:HI 3 "vpr_register_operand" "Up")] > + (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")] > VCMPGTQ_M_N_F)) > ] > "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" > @@ -3862,10 +3862,10 @@ (define_insn "mve_vcmpgtq_m_n_f<mode>" > ;; > (define_insn "mve_vcmpleq_m_f<mode>" > [ > - (set (match_operand:HI 0 "vpr_register_operand" "=Up") > - (unspec:HI [(match_operand:MVE_0 1 "s_register_operand" "w") > + (set (match_operand:<MVE_VPRED> 0 "vpr_register_operand" "=Up") > + (unspec:<MVE_VPRED> [(match_operand:MVE_0 1 "s_register_operand" "w") > (match_operand:MVE_0 2 "s_register_operand" "w") > - (match_operand:HI 3 "vpr_register_operand" "Up")] > + (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")] > VCMPLEQ_M_F)) > ] > "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" > @@ -3878,10 +3878,10 @@ (define_insn "mve_vcmpleq_m_f<mode>" > ;; > (define_insn "mve_vcmpleq_m_n_f<mode>" > [ > - (set (match_operand:HI 0 "vpr_register_operand" "=Up") > - (unspec:HI [(match_operand:MVE_0 1 "s_register_operand" "w") > + (set (match_operand:<MVE_VPRED> 0 "vpr_register_operand" "=Up") > + (unspec:<MVE_VPRED> [(match_operand:MVE_0 1 "s_register_operand" "w") > (match_operand:<V_elem> 2 "s_register_operand" "r") > - (match_operand:HI 3 "vpr_register_operand" "Up")] > + (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")] > VCMPLEQ_M_N_F)) > ] > "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" > @@ -3894,10 +3894,10 @@ (define_insn "mve_vcmpleq_m_n_f<mode>" > ;; > (define_insn "mve_vcmpltq_m_f<mode>" > [ > - (set (match_operand:HI 0 "vpr_register_operand" "=Up") > - (unspec:HI [(match_operand:MVE_0 1 "s_register_operand" "w") > + (set (match_operand:<MVE_VPRED> 0 "vpr_register_operand" "=Up") > + (unspec:<MVE_VPRED> [(match_operand:MVE_0 1 "s_register_operand" "w") > (match_operand:MVE_0 2 "s_register_operand" "w") > - (match_operand:HI 3 "vpr_register_operand" "Up")] > + (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")] > VCMPLTQ_M_F)) > ] > "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" > @@ -3910,10 +3910,10 @@ (define_insn "mve_vcmpltq_m_f<mode>" > ;; > (define_insn "mve_vcmpltq_m_n_f<mode>" > [ > - (set (match_operand:HI 0 "vpr_register_operand" "=Up") > - (unspec:HI [(match_operand:MVE_0 1 "s_register_operand" "w") > + (set (match_operand:<MVE_VPRED> 0 "vpr_register_operand" "=Up") > + (unspec:<MVE_VPRED> [(match_operand:MVE_0 1 "s_register_operand" "w") > (match_operand:<V_elem> 2 "s_register_operand" "r") > - (match_operand:HI 3 "vpr_register_operand" "Up")] > + (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")] > VCMPLTQ_M_N_F)) > ] > "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" > @@ -3926,10 +3926,10 @@ (define_insn "mve_vcmpltq_m_n_f<mode>" > ;; > (define_insn "mve_vcmpneq_m_f<mode>" > [ > - (set (match_operand:HI 0 "vpr_register_operand" "=Up") > - (unspec:HI [(match_operand:MVE_0 1 "s_register_operand" "w") > + (set (match_operand:<MVE_VPRED> 0 "vpr_register_operand" "=Up") > + (unspec:<MVE_VPRED> [(match_operand:MVE_0 1 "s_register_operand" "w") > (match_operand:MVE_0 2 "s_register_operand" "w") > - (match_operand:HI 3 "vpr_register_operand" "Up")] > + (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")] > VCMPNEQ_M_F)) > ] > "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" > @@ -3942,10 +3942,10 @@ (define_insn "mve_vcmpneq_m_f<mode>" > ;; > (define_insn "mve_vcmpneq_m_n_f<mode>" > [ > - (set (match_operand:HI 0 "vpr_register_operand" "=Up") > - (unspec:HI [(match_operand:MVE_0 1 "s_register_operand" "w") > + (set (match_operand:<MVE_VPRED> 0 "vpr_register_operand" "=Up") > + (unspec:<MVE_VPRED> [(match_operand:MVE_0 1 "s_register_operand" "w") > (match_operand:<V_elem> 2 "s_register_operand" "r") > - (match_operand:HI 3 "vpr_register_operand" "Up")] > + (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")] > VCMPNEQ_M_N_F)) > ] > "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" ^ permalink raw reply [flat|nested] 9+ messages in thread
end of thread, other threads:[~2021-10-11 15:03 UTC | newest] Thread overview: 9+ messages (download: mbox.gz / follow: Atom feed) -- links below jump to the message on this page -- 2021-09-07 9:20 [PATCH 10/13] arm: Convert remaining MVE vcmp builtins to predicate qualifiers Christophe Lyon 2021-09-07 9:20 ` [PATCH 11/13] arm: Convert more MVE " Christophe Lyon 2021-10-11 14:17 ` Richard Sandiford 2021-09-07 9:20 ` [PATCH 12/13] arm: Convert more load/store " Christophe Lyon 2021-10-11 14:19 ` Richard Sandiford 2021-10-11 15:03 ` Richard Sandiford 2021-09-07 9:21 ` [PATCH 13/13] arm: Convert more MVE/CDE " Christophe Lyon 2021-10-11 14:21 ` Richard Sandiford 2021-10-11 14:10 ` [PATCH 10/13] arm: Convert remaining MVE vcmp " Richard Sandiford
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