From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 25725 invoked by alias); 16 Jan 2020 10:06:01 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Received: (qmail 25705 invoked by uid 89); 16 Jan 2020 10:06:00 -0000 Authentication-Results: sourceware.org; auth=none X-Spam-SWARE-Status: No, score=-17.5 required=5.0 tests=AWL,BAYES_00,GIT_PATCH_0,GIT_PATCH_1,GIT_PATCH_2,GIT_PATCH_3,RCVD_IN_DNSWL_NONE,SPF_PASS autolearn=ham version=3.3.1 spammy= X-HELO: foss.arm.com Received: from foss.arm.com (HELO foss.arm.com) (217.140.110.172) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Thu, 16 Jan 2020 10:05:50 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id C623431B for ; Thu, 16 Jan 2020 02:05:48 -0800 (PST) Received: from localhost (e121540-lin.manchester.arm.com [10.32.98.126]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 6F67B3F534 for ; Thu, 16 Jan 2020 02:05:48 -0800 (PST) From: Richard Sandiford To: gcc-patches@gcc.gnu.org Mail-Followup-To: gcc-patches@gcc.gnu.org, richard.sandiford@arm.com Subject: [committed] aarch64: Fix BE SVE mode punning involving floats Date: Thu, 16 Jan 2020 11:11:00 -0000 Message-ID: User-Agent: Gnus/5.13 (Gnus v5.13) Emacs/26.1 (gnu/linux) MIME-Version: 1.0 Content-Type: text/plain X-IsSubscribed: yes X-SW-Source: 2020-01/txt/msg00947.txt.bz2 The patterns used by aarch64_split_sve_subreg_move only support integer modes, so if the widest mode is a float, we should get its integer equivalent. Fixes gcc.target/aarch64/sel_3.c for big-endian targets. Tested on aarch64-linux-gnu and aarch64_be-none-elf. Richard 2020-01-16 Richard Sandiford gcc/ * config/aarch64/aarch64.c (aarch64_split_sve_subreg_move): Apply aarch64_sve_int_mode to each mode. --- gcc/config/aarch64/aarch64.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/gcc/config/aarch64/aarch64.c b/gcc/config/aarch64/aarch64.c index ac89cc1f9c9..600a238c1f4 100644 --- a/gcc/config/aarch64/aarch64.c +++ b/gcc/config/aarch64/aarch64.c @@ -4827,8 +4827,8 @@ aarch64_split_sve_subreg_move (rtx dest, rtx ptrue, rtx src) /* Decide which REV operation we need. The mode with wider elements determines the mode of the operands and the mode with the narrower elements determines the reverse width. */ - machine_mode mode_with_wider_elts = GET_MODE (dest); - machine_mode mode_with_narrower_elts = GET_MODE (src); + machine_mode mode_with_wider_elts = aarch64_sve_int_mode (GET_MODE (dest)); + machine_mode mode_with_narrower_elts = aarch64_sve_int_mode (GET_MODE (src)); if (GET_MODE_UNIT_SIZE (mode_with_wider_elts) < GET_MODE_UNIT_SIZE (mode_with_narrower_elts)) std::swap (mode_with_wider_elts, mode_with_narrower_elts);