From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 117576 invoked by alias); 7 Jun 2019 17:17:44 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Received: (qmail 117566 invoked by uid 89); 7 Jun 2019 17:17:44 -0000 Authentication-Results: sourceware.org; auth=none X-Spam-SWARE-Status: No, score=-15.2 required=5.0 tests=AWL,BAYES_00,GIT_PATCH_0,GIT_PATCH_1,GIT_PATCH_2,GIT_PATCH_3,SPF_PASS autolearn=ham version=3.3.1 spammy= X-HELO: foss.arm.com Received: from foss.arm.com (HELO foss.arm.com) (217.140.110.172) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Fri, 07 Jun 2019 17:17:43 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 719092B; Fri, 7 Jun 2019 10:17:41 -0700 (PDT) Received: from localhost (e121540-lin.manchester.arm.com [10.32.98.39]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id A826D3F718; Fri, 7 Jun 2019 10:17:40 -0700 (PDT) From: Richard Sandiford To: Prathamesh Kulkarni Mail-Followup-To: Prathamesh Kulkarni ,Szabolcs Nagy , gcc Patches , nd , richard.sandiford@arm.com Cc: Szabolcs Nagy , gcc Patches , nd Subject: Re: [AArch64] [SVE] PR88837 - Poor vector construction code in VL-specific mode References: <1e630d13-8020-546d-646c-1810a8413e5e@arm.com> Date: Fri, 07 Jun 2019 17:17:00 -0000 In-Reply-To: (Prathamesh Kulkarni's message of "Fri, 7 Jun 2019 21:59:02 +0530") Message-ID: User-Agent: Gnus/5.13 (Gnus v5.13) Emacs/26.1 (gnu/linux) MIME-Version: 1.0 Content-Type: text/plain X-SW-Source: 2019-06/txt/msg00462.txt.bz2 Prathamesh Kulkarni writes: > 2019-06-07 Prathamesh Kulkarni > > * gcc.target/aarch64/sve/init_1.c: Remove options > -O2 -fno-schedule-insns and instead pass -O. > Update assembly in comments. > * gcc.target/aarch64/sve/init_2.c: Likewise. > * gcc.target/aarch64/sve/init_3.c: Likewise. > * gcc.target/aarch64/sve/init_4.c: Likewise. > * gcc.target/aarch64/sve/init_5.c: Likewise and additionally > adjust dg-scan. > * gcc.target/aarch64/sve/init_6.c: Likewise. > * gcc.target/aarch64/sve/init_7.c: Likewise. > * gcc.target/aarch64/sve/init_8.c: Likewise. > * gcc.target/aarch64/sve/init_9.c: Likewise. > * gcc.target/aarch64/sve/init_10.c: Likewise. > * gcc.target/aarch64/sve/init_11.c: Likewise. > * gcc.target/aarch64/sve/init_12.c: Likewise. > > diff --git a/gcc/testsuite/gcc.target/aarch64/sve/init_1.c b/gcc/testsuite/gcc.target/aarch64/sve/init_1.c > index 5c14b603f46..4f18088f3b0 100644 > --- a/gcc/testsuite/gcc.target/aarch64/sve/init_1.c > +++ b/gcc/testsuite/gcc.target/aarch64/sve/init_1.c > @@ -1,5 +1,5 @@ > /* { dg-do assemble { target aarch64_asm_sve_ok } } */ > -/* { dg-options "-O2 -fno-schedule-insns -msve-vector-bits=256 --save-temps" } */ > +/* { dg-options "-O -msve-vector-bits=256 --save-temps" } */ > > /* Case 1.1: Trailing constants with stepped sequence. */ > > @@ -17,10 +17,10 @@ vnx4si foo(int a, int b) > foo: > .LFB0: > .cfi_startproc > - ptrue p0.s, vl8 > index z0.s, #1, #1 > insr z0.s, w1 > insr z0.s, w0 > + ptrue p0.s, vl8 > ret > */ Let's drop the ptrues as well, since they only exist to feed the st1ws and are rightly not part of the matched code. (Same for all tests that have a ptrue at the end.) OK with that change, thanks. Richard