From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by sourceware.org (Postfix) with ESMTP id F35B43861813 for ; Fri, 17 Nov 2023 17:25:47 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org F35B43861813 Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=arm.com ARC-Filter: OpenARC Filter v1.0.0 sourceware.org F35B43861813 Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1700241950; cv=none; b=nSrHtv+H9sNlTME3EN46NkAKWpEUHGOLQbPxPgrNAViwBR1WfVtX0Uk4NVPytIw67taCjKllMJwjD2IYOSKdCeK1JLwDjdu40Wk8C+Er/Qy7Xt46GwE/itQNzNyOpurKnRtKjGcr/B4EoEfXCq6PIQy97VZ6vE+YAVUi8pCvkwM= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1700241950; c=relaxed/simple; bh=Aewh7qgvUDyA6QZJchWgAWmU8Nm0FAHXtdrAcng1VLg=; h=From:To:Subject:Date:Message-ID:MIME-Version; b=xC+a0rKXstDw6ugLhlnfVMUNIb6MKEBk8V9xdqOAjNGNBKaTn4EYuGTr3ov9h5uxAMOUFCapjzusudlOn7MRE2khXRA7UqW1n3vvV0kz8kgpEHDTN0YLLVHpG3om5oetZSbR0nk1AkFjgKiKkwk3kHosIVDE39Q4r7nuwMM/ONo= ARC-Authentication-Results: i=1; server2.sourceware.org Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 8B22B1477 for ; Fri, 17 Nov 2023 09:26:33 -0800 (PST) Received: from localhost (e121540-lin.manchester.arm.com [10.32.110.72]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 260BB3F73F for ; Fri, 17 Nov 2023 09:25:47 -0800 (PST) From: Richard Sandiford To: gcc-patches@gcc.gnu.org Mail-Followup-To: gcc-patches@gcc.gnu.org, richard.sandiford@arm.com Subject: [PATCH 08/21] aarch64: Add +sme References: Date: Fri, 17 Nov 2023 17:25:45 +0000 In-Reply-To: (Richard Sandiford's message of "Fri, 17 Nov 2023 17:23:28 +0000") Message-ID: User-Agent: Gnus/5.13 (Gnus v5.13) Emacs/26.3 (gnu/linux) MIME-Version: 1.0 Content-Type: text/plain X-Spam-Status: No, score=-22.9 required=5.0 tests=BAYES_00,GIT_PATCH_0,KAM_DMARC_NONE,KAM_DMARC_STATUS,KAM_LAZY_DOMAIN_SECURITY,KAM_SHORT,SPF_HELO_NONE,SPF_NONE,TXREP,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: This patch adds the +sme ISA feature and requires it to be present when compiling arm_streaming code. (arm_streaming_compatible code does not necessarily assume the presence of SME. It just has to work when SME is present and streaming mode is enabled.) gcc/ * doc/invoke.texi: Document SME. * doc/sourcebuild.texi: Document aarch64_sve. * config/aarch64/aarch64-option-extensions.def (sme): Define. * config/aarch64/aarch64.h (AARCH64_ISA_SME): New macro. (TARGET_SME): Likewise. * config/aarch64/aarch64.cc (aarch64_override_options_internal): Ensure that SME is present when compiling streaming code. gcc/testsuite/ * lib/target-supports.exp (check_effective_target_aarch64_sme): New target test. * gcc.target/aarch64/sme/aarch64-sme.exp: Force SME to be enabled if it isn't by default. * g++.target/aarch64/sme/aarch64-sme.exp: Likewise. * gcc.target/aarch64/sme/streaming_mode_3.c: New test. --- .../aarch64/aarch64-option-extensions.def | 2 + gcc/config/aarch64/aarch64.cc | 33 ++++++++++ gcc/config/aarch64/aarch64.h | 5 ++ gcc/doc/invoke.texi | 2 + gcc/doc/sourcebuild.texi | 2 + .../g++.target/aarch64/sme/aarch64-sme.exp | 10 ++- .../gcc.target/aarch64/sme/aarch64-sme.exp | 10 ++- .../gcc.target/aarch64/sme/streaming_mode_3.c | 63 +++++++++++++++++++ .../gcc.target/aarch64/sme/streaming_mode_4.c | 22 +++++++ gcc/testsuite/lib/target-supports.exp | 12 ++++ 10 files changed, 157 insertions(+), 4 deletions(-) create mode 100644 gcc/testsuite/gcc.target/aarch64/sme/streaming_mode_3.c create mode 100644 gcc/testsuite/gcc.target/aarch64/sme/streaming_mode_4.c diff --git a/gcc/config/aarch64/aarch64-option-extensions.def b/gcc/config/aarch64/aarch64-option-extensions.def index 825f3bf7758..fb9ff1b66b2 100644 --- a/gcc/config/aarch64/aarch64-option-extensions.def +++ b/gcc/config/aarch64/aarch64-option-extensions.def @@ -151,4 +151,6 @@ AARCH64_OPT_EXTENSION("mops", MOPS, (), (), (), "") AARCH64_OPT_EXTENSION("cssc", CSSC, (), (), (), "cssc") +AARCH64_OPT_EXTENSION("sme", SME, (BF16, SVE2), (), (), "sme") + #undef AARCH64_OPT_EXTENSION diff --git a/gcc/config/aarch64/aarch64.cc b/gcc/config/aarch64/aarch64.cc index 1a4ef2a4396..fcaea87c737 100644 --- a/gcc/config/aarch64/aarch64.cc +++ b/gcc/config/aarch64/aarch64.cc @@ -11737,6 +11737,23 @@ aarch64_fixed_condition_code_regs (unsigned int *p1, unsigned int *p2) return true; } +/* Implement TARGET_START_CALL_ARGS. */ + +static void +aarch64_start_call_args (cumulative_args_t ca_v) +{ + CUMULATIVE_ARGS *ca = get_cumulative_args (ca_v); + + if (!TARGET_SME && (ca->isa_mode & AARCH64_FL_SM_ON)) + { + error ("calling a streaming function requires the ISA extension %qs", + "sme"); + inform (input_location, "you can enable %qs using the command-line" + " option %<-march%>, or by using the %" + " attribute or pragma", "sme"); + } +} + /* This function is used by the call expanders of the machine description. RESULT is the register in which the result is returned. It's NULL for "call" and "sibcall". @@ -18541,6 +18558,19 @@ aarch64_override_options_internal (struct gcc_options *opts) && !fixed_regs[R18_REGNUM]) error ("%<-fsanitize=shadow-call-stack%> requires %<-ffixed-x18%>"); + if ((opts->x_aarch64_isa_flags & AARCH64_FL_SM_ON) + && !(opts->x_aarch64_isa_flags & AARCH64_FL_SME)) + { + error ("streaming functions require the ISA extension %qs", "sme"); + inform (input_location, "you can enable %qs using the command-line" + " option %<-march%>, or by using the %" + " attribute or pragma", "sme"); + opts->x_target_flags &= ~MASK_GENERAL_REGS_ONLY; + auto new_flags = (opts->x_aarch64_asm_isa_flags + | feature_deps::SME ().enable); + aarch64_set_asm_isa_flags (opts, new_flags); + } + initialize_aarch64_code_model (opts); initialize_aarch64_tls_size (opts); aarch64_tpidr_register = opts->x_aarch64_tpidr_reg; @@ -28607,6 +28637,9 @@ aarch64_run_selftests (void) #undef TARGET_FUNCTION_VALUE_REGNO_P #define TARGET_FUNCTION_VALUE_REGNO_P aarch64_function_value_regno_p +#undef TARGET_START_CALL_ARGS +#define TARGET_START_CALL_ARGS aarch64_start_call_args + #undef TARGET_GIMPLE_FOLD_BUILTIN #define TARGET_GIMPLE_FOLD_BUILTIN aarch64_gimple_fold_builtin diff --git a/gcc/config/aarch64/aarch64.h b/gcc/config/aarch64/aarch64.h index 4c7d9409fbc..ded640e8c7b 100644 --- a/gcc/config/aarch64/aarch64.h +++ b/gcc/config/aarch64/aarch64.h @@ -214,6 +214,7 @@ constexpr auto AARCH64_FL_DEFAULT_ISA_MODE = AARCH64_FL_SM_OFF; #define AARCH64_ISA_SVE2_BITPERM (aarch64_isa_flags & AARCH64_FL_SVE2_BITPERM) #define AARCH64_ISA_SVE2_SHA3 (aarch64_isa_flags & AARCH64_FL_SVE2_SHA3) #define AARCH64_ISA_SVE2_SM4 (aarch64_isa_flags & AARCH64_FL_SVE2_SM4) +#define AARCH64_ISA_SME (aarch64_isa_flags & AARCH64_FL_SME) #define AARCH64_ISA_V8_3A (aarch64_isa_flags & AARCH64_FL_V8_3A) #define AARCH64_ISA_DOTPROD (aarch64_isa_flags & AARCH64_FL_DOTPROD) #define AARCH64_ISA_AES (aarch64_isa_flags & AARCH64_FL_AES) @@ -293,6 +294,10 @@ constexpr auto AARCH64_FL_DEFAULT_ISA_MODE = AARCH64_FL_SM_OFF; /* SVE2 SM4 instructions, enabled through +sve2-sm4. */ #define TARGET_SVE2_SM4 (AARCH64_ISA_SVE2_SM4) +/* SME instructions, enabled through +sme. Note that this does not + imply anything about the state of PSTATE.SM. */ +#define TARGET_SME (AARCH64_ISA_SME) + /* ARMv8.3-A features. */ #define TARGET_ARMV8_3 (AARCH64_ISA_V8_3A) diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi index ba99a701f3e..31a3f7c567d 100644 --- a/gcc/doc/invoke.texi +++ b/gcc/doc/invoke.texi @@ -21059,6 +21059,8 @@ Enable the Flag Manipulation instructions Extension. Enable the Pointer Authentication Extension. @item cssc Enable the Common Short Sequence Compression instructions. +@item sme +Enable the Scalable Matrix Extension. @end table diff --git a/gcc/doc/sourcebuild.texi b/gcc/doc/sourcebuild.texi index eaa75f00f5c..448f5e08578 100644 --- a/gcc/doc/sourcebuild.texi +++ b/gcc/doc/sourcebuild.texi @@ -2316,6 +2316,8 @@ AArch64 target which generates instruction sequences for big endian. @item aarch64_small_fpic Binutils installed on test system supports relocation types required by -fpic for AArch64 small memory model. +@item aarch64_sme +AArch64 target that generates instructions for SME. @item aarch64_sve_hw AArch64 target that is able to generate and execute SVE code (regardless of whether it does so by default). diff --git a/gcc/testsuite/g++.target/aarch64/sme/aarch64-sme.exp b/gcc/testsuite/g++.target/aarch64/sme/aarch64-sme.exp index 72fcd0bd982..1c3e69cde12 100644 --- a/gcc/testsuite/g++.target/aarch64/sme/aarch64-sme.exp +++ b/gcc/testsuite/g++.target/aarch64/sme/aarch64-sme.exp @@ -30,10 +30,16 @@ load_lib g++-dg.exp # Initialize `dg'. dg-init -aarch64-with-arch-dg-options "" { +if { [check_effective_target_aarch64_sme] } { + set sme_flags "" +} else { + set sme_flags "-march=armv9-a+sme" +} + +aarch64-with-arch-dg-options $sme_flags { # Main loop. dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/*.\[cCS\]]] \ - "" "" + "" $sme_flags } # All done. diff --git a/gcc/testsuite/gcc.target/aarch64/sme/aarch64-sme.exp b/gcc/testsuite/gcc.target/aarch64/sme/aarch64-sme.exp index c990e59247a..011310e8061 100644 --- a/gcc/testsuite/gcc.target/aarch64/sme/aarch64-sme.exp +++ b/gcc/testsuite/gcc.target/aarch64/sme/aarch64-sme.exp @@ -30,10 +30,16 @@ load_lib gcc-dg.exp # Initialize `dg'. dg-init -aarch64-with-arch-dg-options "" { +if { [check_effective_target_aarch64_sme] } { + set sme_flags "" +} else { + set sme_flags "-march=armv9-a+sme" +} + +aarch64-with-arch-dg-options $sme_flags { # Main loop. dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/*.\[cCS\]]] \ - "" "" + "" $sme_flags } # All done. diff --git a/gcc/testsuite/gcc.target/aarch64/sme/streaming_mode_3.c b/gcc/testsuite/gcc.target/aarch64/sme/streaming_mode_3.c new file mode 100644 index 00000000000..45ec92321b2 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sme/streaming_mode_3.c @@ -0,0 +1,63 @@ +// { dg-options "" } + +#pragma GCC target "+nosme" + +void sc_a () [[arm::streaming_compatible]] {} +void s_a () [[arm::streaming]] {} // { dg-error "streaming functions require the ISA extension 'sme'" } +void ns_a () {} + +void sc_b () [[arm::streaming_compatible]] {} +void ns_b () {} +void s_b () [[arm::streaming]] {} // { dg-error "streaming functions require the ISA extension 'sme'" } + +void sc_c () [[arm::streaming_compatible]] {} +void sc_d () [[arm::streaming_compatible]] {} + +void s_c () [[arm::streaming]] {} // { dg-error "streaming functions require the ISA extension 'sme'" } +void s_d () [[arm::streaming]] {} // { dg-error "streaming functions require the ISA extension 'sme'" } + +void ns_c () {} +void ns_d () {} + +void sc_e () [[arm::streaming_compatible]]; +void s_e () [[arm::streaming]]; +void ns_e (); + +#pragma GCC target "+sme" + +void sc_f () [[arm::streaming_compatible]] {} +void s_f () [[arm::streaming]] {} +void ns_f () {} + +void sc_g () [[arm::streaming_compatible]] {} +void ns_g () {} +void s_g () [[arm::streaming]] {} + +void sc_h () [[arm::streaming_compatible]] {} +void sc_i () [[arm::streaming_compatible]] {} + +void s_h () [[arm::streaming]] {} +void s_i () [[arm::streaming]] {} + +void ns_h () {} +void ns_i () {} + +void sc_j () [[arm::streaming_compatible]]; +void s_j () [[arm::streaming]]; +void ns_j (); + +#pragma GCC target "+sme" + +void sc_k () [[arm::streaming_compatible]] {} + +#pragma GCC target "+nosme" +#pragma GCC target "+sme" + +void s_k () [[arm::streaming]] {} + +#pragma GCC target "+nosme" +#pragma GCC target "+sme" + +void ns_k () {} + +#pragma GCC target "+nosme" diff --git a/gcc/testsuite/gcc.target/aarch64/sme/streaming_mode_4.c b/gcc/testsuite/gcc.target/aarch64/sme/streaming_mode_4.c new file mode 100644 index 00000000000..50e92f2e18a --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sme/streaming_mode_4.c @@ -0,0 +1,22 @@ +// { dg-options "-mgeneral-regs-only" } + +void sc_a () [[arm::streaming_compatible]] {} +void s_a () [[arm::streaming]] {} // { dg-error "streaming functions require the ISA extension 'sme'" } +void ns_a () {} + +void sc_b () [[arm::streaming_compatible]] {} +void ns_b () {} +void s_b () [[arm::streaming]] {} // { dg-error "streaming functions require the ISA extension 'sme'" } + +void sc_c () [[arm::streaming_compatible]] {} +void sc_d () [[arm::streaming_compatible]] {} + +void s_c () [[arm::streaming]] {} // { dg-error "streaming functions require the ISA extension 'sme'" } +void s_d () [[arm::streaming]] {} // { dg-error "streaming functions require the ISA extension 'sme'" } + +void ns_c () {} +void ns_d () {} + +void sc_e () [[arm::streaming_compatible]]; +void s_e () [[arm::streaming]]; +void ns_e (); diff --git a/gcc/testsuite/lib/target-supports.exp b/gcc/testsuite/lib/target-supports.exp index 1a7bea96c1e..a78a210b79f 100644 --- a/gcc/testsuite/lib/target-supports.exp +++ b/gcc/testsuite/lib/target-supports.exp @@ -4413,6 +4413,18 @@ proc aarch64_sve_bits { } { }] } +# Return 1 if this is an AArch64 target that generates instructions for SME. +proc check_effective_target_aarch64_sme { } { + if { ![istarget aarch64*-*-*] } { + return 0 + } + return [check_no_compiler_messages aarch64_sme assembly { + #if !defined (__ARM_FEATURE_SME) + #error FOO + #endif + }] +} + # Return 1 if this is a compiler supporting ARC atomic operations proc check_effective_target_arc_atomic { } { return [check_no_compiler_messages arc_atomic assembly { -- 2.25.1