From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by sourceware.org (Postfix) with ESMTP id 41F3438A816D for ; Tue, 15 Nov 2022 18:05:16 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 41F3438A816D Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 48A1213D5; Tue, 15 Nov 2022 10:05:22 -0800 (PST) Received: from localhost (e121540-lin.manchester.arm.com [10.32.98.62]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 491CA3F587; Tue, 15 Nov 2022 10:05:15 -0800 (PST) From: Richard Sandiford To: "Andre Vieira \(lists\)" Mail-Followup-To: "Andre Vieira \(lists\)" ,"gcc-patches\@gcc.gnu.org" , Kyrylo Tkachov , Richard Earnshaw , richard.sandiford@arm.com Cc: "gcc-patches\@gcc.gnu.org" , Kyrylo Tkachov , Richard Earnshaw Subject: Re: [PATCH 2/2] aarch64: Add support for widening LDAPR instructions References: <0f0f4ffc-daa9-7b4d-334b-3941596a86cf@arm.com> Date: Tue, 15 Nov 2022 18:05:14 +0000 In-Reply-To: <0f0f4ffc-daa9-7b4d-334b-3941596a86cf@arm.com> (Andre Vieira's message of "Mon, 14 Nov 2022 14:10:11 +0000") Message-ID: User-Agent: Gnus/5.13 (Gnus v5.13) Emacs/26.3 (gnu/linux) MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable X-Spam-Status: No, score=-39.2 required=5.0 tests=BAYES_00,BODY_8BITS,GIT_PATCH_0,KAM_DMARC_NONE,KAM_DMARC_STATUS,KAM_LAZY_DOMAIN_SECURITY,KAM_SHORT,SPF_HELO_NONE,SPF_NONE,TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: "Andre Vieira (lists)" writes: > Updated version of the patch to account for the testsuite changes in the= =20 > first patch. > > On 10/11/2022 11:20, Andre Vieira (lists) via Gcc-patches wrote: >> Hi, >> >> This patch adds support for the widening LDAPR instructions. >> >> Bootstrapped and regression tested on aarch64-none-linux-gnu. >> >> OK for trunk? >> >> 2022-11-09=C2=A0 Andre Vieira=C2=A0 >> =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 Kyryl= o Tkachov=C2=A0 >> >> gcc/ChangeLog: >> >> =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 * config/aarch64/atomics.md=20 >> (*aarch64_atomic_load_rcpc_zext): New pattern. >> =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 (*aarch64_atomic_load_rcpc_zext): Likewise. >> >> gcc/testsuite/ChangeLog: >> >> =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 * gcc.target/aarch64/ldapr-ex= t.c: New test. > > diff --git a/gcc/config/aarch64/atomics.md b/gcc/config/aarch64/atomics.md > index dc5f52ee8a4b349c0d8466a16196f83604893cbb..9670bef7d8cb2b32c5146536d= 806a7e8bdffb2e3 100644 > --- a/gcc/config/aarch64/atomics.md > +++ b/gcc/config/aarch64/atomics.md > @@ -704,6 +704,28 @@ > } > ) >=20=20 > +(define_insn "*aarch64_atomic_load_rcpc_zext" > + [(set (match_operand:GPI 0 "register_operand" "=3Dr") > + (zero_extend:GPI > + (unspec_volatile:ALLX > + [(match_operand:ALLX 1 "aarch64_sync_memory_operand" "Q") > + (match_operand:SI 2 "const_int_operand")] ;; model > + UNSPECV_LDAP)))] > + "TARGET_RCPC" > + "ldapr\t%0, %1" It would be good to add: > to the condition, so that we don't provide bogus SI->SI and DI->DI extensions. (They shouldn't be generated, but it's better not to provide them anyway.) Thanks, Richard > +) > + > +(define_insn "*aarch64_atomic_load_rcpc_sext" > + [(set (match_operand:GPI 0 "register_operand" "=3Dr") > + (sign_extend:GPI > + (unspec_volatile:ALLX > + [(match_operand:ALLX 1 "aarch64_sync_memory_operand" "Q") > + (match_operand:SI 2 "const_int_operand")] ;; model > + UNSPECV_LDAP)))] > + "TARGET_RCPC" > + "ldaprs\t%0, %1" > +) > + > (define_insn "atomic_store" > [(set (match_operand:ALLI 0 "aarch64_rcpc_memory_operand" "=3DQ,Ust") > (unspec_volatile:ALLI > diff --git a/gcc/testsuite/gcc.target/aarch64/ldapr-ext.c b/gcc/testsuite= /gcc.target/aarch64/ldapr-ext.c > new file mode 100644 > index 0000000000000000000000000000000000000000..aed27e06235b1d266decf1174= 5dacf94cc59e76d > --- /dev/null > +++ b/gcc/testsuite/gcc.target/aarch64/ldapr-ext.c > @@ -0,0 +1,94 @@ > +/* { dg-do compile } */ > +/* { dg-options "-O2 -std=3Dc99" } */ > +/* { dg-final { check-function-bodies "**" "" "" } } */ > +#include > + > +#pragma GCC target "+rcpc" > + > +atomic_ullong u64; > +atomic_llong s64; > +atomic_uint u32; > +atomic_int s32; > +atomic_ushort u16; > +atomic_short s16; > +atomic_uchar u8; > +atomic_schar s8; > + > +#define TEST(name, ldsize, rettype) \ > +rettype \ > +test_##name (void) \ > +{ \ > + return atomic_load_explicit (&ldsize, memory_order_acquire); \ > +} > + > +/* > +**test_u8_u64: > +**... > +** ldaprb x0, \[x[0-9]+\] > +** ret > +*/ > + > +TEST(u8_u64, u8, unsigned long long) > + > +/* > +**test_s8_s64: > +**... > +** ldaprsb x0, \[x[0-9]+\] > +** ret > +*/ > + > +TEST(s8_s64, s8, long long) > + > +/* > +**test_u16_u64: > +**... > +** ldaprh x0, \[x[0-9]+\] > +** ret > +*/ > + > +TEST(u16_u64, u16, unsigned long long) > + > +/* > +**test_s16_s64: > +**... > +** ldaprsh x0, \[x[0-9]+\] > +** ret > +*/ > + > +TEST(s16_s64, s16, long long) > + > +/* > +**test_u8_u32: > +**... > +** ldaprb w0, \[x[0-9]+\] > +** ret > +*/ > + > +TEST(u8_u32, u8, unsigned) > + > +/* > +**test_s8_s32: > +**... > +** ldaprsb w0, \[x[0-9]+\] > +** ret > +*/ > + > +TEST(s8_s32, s8, int) > + > +/* > +**test_u16_u32: > +**... > +** ldaprh w0, \[x[0-9]+\] > +** ret > +*/ > + > +TEST(u16_u32, u16, unsigned) > + > +/* > +**test_s16_s32: > +**... > +** ldaprsh w0, \[x[0-9]+\] > +** ret > +*/ > + > +TEST(s16_s32, s16, int)