From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by sourceware.org (Postfix) with ESMTP id DC4933858C52 for ; Fri, 23 Sep 2022 09:42:59 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org DC4933858C52 Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 073FB139F; Fri, 23 Sep 2022 02:43:06 -0700 (PDT) Received: from localhost (e121540-lin.manchester.arm.com [10.32.98.62]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 80DCE3F73D; Fri, 23 Sep 2022 02:42:58 -0700 (PDT) From: Richard Sandiford To: Tamar Christina Mail-Followup-To: Tamar Christina ,gcc-patches@gcc.gnu.org, nd@arm.com, Richard.Earnshaw@arm.com, Marcus.Shawcroft@arm.com, Kyrylo.Tkachov@arm.com, richard.sandiford@arm.com Cc: gcc-patches@gcc.gnu.org, nd@arm.com, Richard.Earnshaw@arm.com, Marcus.Shawcroft@arm.com, Kyrylo.Tkachov@arm.com Subject: Re: [PATCH 2/2]AArch64 Extend tbz pattern to allow SI to SI extensions. References: Date: Fri, 23 Sep 2022 10:42:57 +0100 In-Reply-To: (Tamar Christina's message of "Fri, 23 Sep 2022 10:25:26 +0100") Message-ID: User-Agent: Gnus/5.13 (Gnus v5.13) Emacs/26.3 (gnu/linux) MIME-Version: 1.0 Content-Type: text/plain X-Spam-Status: No, score=-47.3 required=5.0 tests=BAYES_00,GIT_PATCH_0,KAM_DMARC_NONE,KAM_DMARC_STATUS,KAM_LAZY_DOMAIN_SECURITY,KAM_LOTSOFHASH,KAM_SHORT,SPF_HELO_NONE,SPF_NONE,TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: Tamar Christina writes: > Hi All, > > This adds additional recognition of & 1 into the tbz/tbnz pattern. > > Concretely with the mid-end changes this changes > > void g1(bool x) > { > if (__builtin_expect (x, 0)) > h (); > } > > from > > tst w0, 255 > bne .L7 > > to > > tbnz w0, #0, .L5 > > This pattern occurs ~120,000 times in SPECCPU 20127, basically on > every boolean comparison. > > Bootstrapped Regtested on aarch64-none-linux-gnu and no issues. > > Ok for master? > > Thanks, > Tamar > > gcc/ChangeLog: > > * config/aarch64/aarch64.md (*tb1): Renamed this ... > (*tb1): ... To this. > * config/aarch64/iterators.md (GPI2): New. > > gcc/testsuite/ChangeLog: > > * gcc.target/aarch64/tbz_1.c: New test. > > --- inline copy of patch -- > diff --git a/gcc/config/aarch64/aarch64.md b/gcc/config/aarch64/aarch64.md > index 6aa1fb4be003f2027d63ac69fd314c2bbc876258..3faa03f453c94665d9d82225f180d8afdcd0b5fe 100644 > --- a/gcc/config/aarch64/aarch64.md > +++ b/gcc/config/aarch64/aarch64.md > @@ -943,31 +943,33 @@ (define_insn "*cb1" > (const_int 1)))] > ) > > -(define_insn "*tb1" > +(define_insn "*tb1" > [(set (pc) (if_then_else > - (EQL (zero_extract:DI (match_operand:GPI 0 "register_operand" "r") > - (const_int 1) > - (match_operand 1 > - "aarch64_simd_shift_imm_" "n")) > + (EQL (zero_extract:GPI2 > + (match_operand:GPI 0 "register_operand" "r") > + (const_int 1) > + (match_operand 1 "aarch64_simd_shift_imm_" "n")) > (const_int 0)) > (label_ref (match_operand 2 "" "")) > (pc))) > (clobber (reg:CC CC_REGNUM))] > - "!aarch64_track_speculation" > + "!aarch64_track_speculation > + && known_ge (GET_MODE_SIZE (mode), > + GET_MODE_SIZE (mode))" Is this check necessary? The extraction evaluates to 0 or 1, so it shouldn't matter whether it is interpreted as DI or SI. OK without the check if you agree. Thanks, Richard > { > if (get_attr_length (insn) == 8) > { > if (get_attr_far_branch (insn) == 1) > return aarch64_gen_far_branch (operands, 2, "Ltb", > - "\\t%0, %1, "); > + "\\t%0, %1, "); > else > { > operands[1] = GEN_INT (HOST_WIDE_INT_1U << UINTVAL (operands[1])); > - return "tst\t%0, %1\;\t%l2"; > + return "tst\t%0, %1\;\t%l2"; > } > } > else > - return "\t%0, %1, %l2"; > + return "\t%0, %1, %l2"; > } > [(set_attr "type" "branch") > (set (attr "length") > diff --git a/gcc/config/aarch64/iterators.md b/gcc/config/aarch64/iterators.md > index 89ca66fd291b60a28979785706ecc5345ea86744..f6b2e7a83c63cab73947b6bd61b499b4b57d14ac 100644 > --- a/gcc/config/aarch64/iterators.md > +++ b/gcc/config/aarch64/iterators.md > @@ -28,6 +28,8 @@ (define_mode_iterator CCFP_CCFPE [CCFP CCFPE]) > > ;; Iterator for General Purpose Integer registers (32- and 64-bit modes) > (define_mode_iterator GPI [SI DI]) > +;; Copy of the above iterator > +(define_mode_iterator GPI2 [SI DI]) > > ;; Iterator for HI, SI, DI, some instructions can only work on these modes. > (define_mode_iterator GPI_I16 [(HI "AARCH64_ISA_F16") SI DI]) > diff --git a/gcc/testsuite/gcc.target/aarch64/tbz_1.c b/gcc/testsuite/gcc.target/aarch64/tbz_1.c > new file mode 100644 > index 0000000000000000000000000000000000000000..6a75eb4e7aedbfa3ae329358c6ee4d675704a074 > --- /dev/null > +++ b/gcc/testsuite/gcc.target/aarch64/tbz_1.c > @@ -0,0 +1,32 @@ > +/* { dg-do compile } */ > +/* { dg-additional-options "-O2 -std=c99 -fno-unwind-tables -fno-asynchronous-unwind-tables" } */ > +/* { dg-final { check-function-bodies "**" "" "" { target { le } } } } */ > + > +#include // Type your code here, or load an example. > + > +void h(void); > + > +/* > +** g1: > +** tbnz w[0-9], #?0, .L([0-9]+) > +** ret > +** ... > +*/ > +void g1(bool x) > +{ > + if (__builtin_expect (x, 0)) > + h (); > +} > + > +/* > +** g2: > +** tbz w[0-9]+, #?0, .L([0-9]+) > +** b h > +** ... > +*/ > +void g2(bool x) > +{ > + if (__builtin_expect (x, 1)) > + h (); > +} > +