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Rozycki" , richard.sandiford@arm.com Cc: gcc-patches@gcc.gnu.org, Jakub Jelinek , Matthew Fortune , "Maciej W. Rozycki" Subject: Re: PING^5: [PATCH] mips: Fix up mips_atomic_assign_expand_fenv [PR94780] References: <84b8b6a1019dd2a6eb84daf6cc21358d8781f5b7.camel@mengyan1223.wang> <41b4eb8970718ada95ecf6b6de9dd3a515db6cff.camel@mengyan1223.wang> Date: Fri, 30 Jul 2021 09:11:38 +0100 In-Reply-To: <41b4eb8970718ada95ecf6b6de9dd3a515db6cff.camel@mengyan1223.wang> (Xi Ruoyao's message of "Fri, 30 Jul 2021 12:56:31 +0800") Message-ID: User-Agent: Gnus/5.13 (Gnus v5.13) Emacs/26.3 (gnu/linux) Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: LO4P123CA0466.GBRP123.PROD.OUTLOOK.COM (2603:10a6:600:1aa::21) To DBAPR08MB5589.eurprd08.prod.outlook.com (2603:10a6:10:1a2::23) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 Received: from localhost (217.140.106.32) by LO4P123CA0466.GBRP123.PROD.OUTLOOK.COM (2603:10a6:600:1aa::21) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4373.18 via Frontend Transport; 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CTRY:IE; LANG:en; SCL:1; SRV:; IPV:CAL; SFV:NSPM; H:64aa7808-outbound-1.mta.getcheckrecipient.com; PTR:ec2-63-35-35-123.eu-west-1.compute.amazonaws.com; CAT:NONE; SFS:(4636009)(346002)(396003)(39850400004)(136003)(376002)(46966006)(36840700001)(6486002)(83380400001)(336012)(82740400003)(107886003)(450100002)(54906003)(4326008)(8936002)(356005)(6862004)(70206006)(2616005)(8676002)(316002)(81166007)(956004)(186003)(36860700001)(6496006)(26005)(70586007)(86362001)(82310400003)(5660300002)(2906002)(47076005)(36756003)(478600001)(44832011)(81973001); DIR:OUT; SFP:1101; X-OriginatorOrg: arm.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 30 Jul 2021 08:11:48.7780 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 4d879ba9-df60-4c1e-2563-08d95331ae1e X-MS-Exchange-CrossTenant-Id: f34e5979-57d9-4aaa-ad4d-b122a662184d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=f34e5979-57d9-4aaa-ad4d-b122a662184d; Ip=[63.35.35.123]; Helo=[64aa7808-outbound-1.mta.getcheckrecipient.com] X-MS-Exchange-CrossTenant-AuthSource: VE1EUR03FT011.eop-EUR03.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: VI1PR0801MB1920 X-Spam-Status: No, score=-11.4 required=5.0 tests=BAYES_00, BODY_8BITS, DKIM_SIGNED, DKIM_VALID, GIT_PATCH_0, MSGID_FROM_MTA_HEADER, RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H2, SPF_HELO_PASS, SPF_PASS, TXREP, UNPARSEABLE_RELAY autolearn=ham autolearn_force=no version=3.4.4 X-Spam-Checker-Version: SpamAssassin 3.4.4 (2020-01-24) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 30 Jul 2021 08:11:53 -0000 Xi Ruoyao writes: > Ping again. > > On Wed, 2021-06-23 at 11:11 +0800, Xi Ruoyao wrote: >> Commit message shamelessly copied from 1777beb6b129 by jakub: >>=20 >> This function, because it is sometimes called even outside of function >> bodies, uses create_tmp_var_raw rather than create_tmp_var.=C2=A0 But in >> order >> for that to work, when first referenced, the VAR_DECLs need to appear >> in a >> TARGET_EXPR so that during gimplification the var gets the right >> DECL_CONTEXT and is added to local decls. >>=20 >> Bootstrapped & regtested on mips64el-linux-gnu.=C2=A0 Ok for trunk and >> backport >> to 11, 10, and 9? OK for all, thanks. Similar comments to the previous message about the appropriateness of me reviewing the patch, but like you say, this is doing for MIPS what we've already had to do for other targets. Richard >>=20 >> gcc/ >>=20 >> =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0* config/mips/mips.c (mi= ps_atomic_assign_expand_fenv): Use >> =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 TARGET_EXPR inste= ad of MODIFY_EXPR. >> --- >> =C2=A0gcc/config/mips/mips.c | 12 ++++++------ >> =C2=A01 file changed, 6 insertions(+), 6 deletions(-) >>=20 >> diff --git a/gcc/config/mips/mips.c b/gcc/config/mips/mips.c >> index 8f043399a8e..89d1be6cea6 100644 >> --- a/gcc/config/mips/mips.c >> +++ b/gcc/config/mips/mips.c >> @@ -22439,12 +22439,12 @@ mips_atomic_assign_expand_fenv (tree *hold, >> tree *clear, tree *update) >> =C2=A0=C2=A0 tree get_fcsr =3D mips_builtin_decls[MIPS_GET_FCSR]; >> =C2=A0=C2=A0 tree set_fcsr =3D mips_builtin_decls[MIPS_SET_FCSR]; >> =C2=A0=C2=A0 tree get_fcsr_hold_call =3D build_call_expr (get_fcsr, 0); >> -=C2=A0 tree hold_assign_orig =3D build2 (MODIFY_EXPR, MIPS_ATYPE_USI, >> -=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0= =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 fcsr_orig_var, get_fcsr_ho= ld_call); >> +=C2=A0 tree hold_assign_orig =3D build4 (TARGET_EXPR, MIPS_ATYPE_USI, >> +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0= =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 fcsr_orig_var, get_fcsr_ho= ld_call, >> NULL, NULL); >> =C2=A0=C2=A0 tree hold_mod_val =3D build2 (BIT_AND_EXPR, MIPS_ATYPE_USI, >> fcsr_orig_var, >> =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0= =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0=C2=A0=C2=A0=C2=A0=C2=A0 build_int_cst (MIPS_ATYPE_USI, >> 0xfffff003)); >> -=C2=A0 tree hold_assign_mod =3D build2 (MODIFY_EXPR, MIPS_ATYPE_USI, >> -=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0= =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 fcsr_mod_var, hold_mod_val); >> +=C2=A0 tree hold_assign_mod =3D build4 (TARGET_EXPR, MIPS_ATYPE_USI, >> +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0= =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 fcsr_mod_var, hold_mod_val, NULL= , >> NULL); >> =C2=A0=C2=A0 tree set_fcsr_hold_call =3D build_call_expr (set_fcsr, 1, >> fcsr_mod_var); >> =C2=A0=C2=A0 tree hold_all =3D build2 (COMPOUND_EXPR, MIPS_ATYPE_USI, >> =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0= =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0 hold_assign_orig, hold_assign_mod); >> @@ -22454,8 +22454,8 @@ mips_atomic_assign_expand_fenv (tree *hold, >> tree *clear, tree *update) >> =C2=A0=C2=A0 *clear =3D build_call_expr (set_fcsr, 1, fcsr_mod_var); >> =C2=A0 >> =C2=A0=C2=A0 tree get_fcsr_update_call =3D build_call_expr (get_fcsr, 0)= ; >> -=C2=A0 *update =3D build2 (MODIFY_EXPR, MIPS_ATYPE_USI, >> -=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 exceptions_var, get_fcsr_update_cal= l); >> +=C2=A0 *update =3D build4 (TARGET_EXPR, MIPS_ATYPE_USI, >> +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 exceptions_var, get_fcsr_update_cal= l, NULL, NULL); >> =C2=A0=C2=A0 tree set_fcsr_update_call =3D build_call_expr (set_fcsr, 1, >> fcsr_orig_var); >> =C2=A0=C2=A0 *update =3D build2 (COMPOUND_EXPR, void_type_node, *update, >> =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0= =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 set_fcsr_update_call);