* [PATCH 5/6] arm: Add testsuite checks for asm-flag
2019-11-08 10:54 [PATCH 0/6] Implement asm flag outputs for arm + aarch64 Richard Henderson
2019-11-08 10:54 ` [PATCH 3/6] arm: Rename CC_NOOVmode to CC_NZmode Richard Henderson
2019-11-08 10:54 ` [PATCH 4/6] arm, aarch64: Add support for __GCC_ASM_FLAG_OUTPUTS__ Richard Henderson
@ 2019-11-08 10:54 ` Richard Henderson
2019-11-08 10:54 ` [PATCH 2/6] arm: Fix the "c" constraint Richard Henderson
` (3 subsequent siblings)
6 siblings, 0 replies; 11+ messages in thread
From: Richard Henderson @ 2019-11-08 10:54 UTC (permalink / raw)
To: gcc-patches
Cc: richard.earnshaw, james.greenhalgh, richard.sandiford,
marcus.shawcroft, kyrylo.tkachov
Inspired by the tests in gcc.target/i386. Testing code generation,
diagnostics, and execution.
* gcc.target/arm/asm-flag-1.c: New test.
* gcc.target/arm/asm-flag-3.c: New test.
* gcc.target/arm/asm-flag-5.c: New test.
* gcc.target/arm/asm-flag-6.c: New test.
---
gcc/testsuite/gcc.target/arm/asm-flag-1.c | 35 ++++++++++++++++++
gcc/testsuite/gcc.target/arm/asm-flag-3.c | 36 +++++++++++++++++++
gcc/testsuite/gcc.target/arm/asm-flag-5.c | 30 ++++++++++++++++
gcc/testsuite/gcc.target/arm/asm-flag-6.c | 43 +++++++++++++++++++++++
4 files changed, 144 insertions(+)
create mode 100644 gcc/testsuite/gcc.target/arm/asm-flag-1.c
create mode 100644 gcc/testsuite/gcc.target/arm/asm-flag-3.c
create mode 100644 gcc/testsuite/gcc.target/arm/asm-flag-5.c
create mode 100644 gcc/testsuite/gcc.target/arm/asm-flag-6.c
diff --git a/gcc/testsuite/gcc.target/arm/asm-flag-1.c b/gcc/testsuite/gcc.target/arm/asm-flag-1.c
new file mode 100644
index 00000000000..e1ce4120d98
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/asm-flag-1.c
@@ -0,0 +1,35 @@
+/* Test the valid @cc<cc> asm flag outputs. */
+/* { dg-do compile } */
+/* { dg-options "-O" } */
+
+#ifndef __GCC_ASM_FLAG_OUTPUTS__
+#error "missing preprocessor define"
+#endif
+
+void f(char *out)
+{
+ asm(""
+ : "=@ccne"(out[0]), "=@cceq"(out[1]),
+ "=@cccs"(out[2]), "=@cccc"(out[3]),
+ "=@ccmi"(out[4]), "=@ccpl"(out[5]),
+ "=@ccvs"(out[6]), "=@ccvc"(out[7]),
+ "=@cchi"(out[8]), "=@ccls"(out[9]),
+ "=@ccge"(out[10]), "=@cclt"(out[11]),
+ "=@ccgt"(out[12]), "=@ccle"(out[13]));
+}
+
+/* There will be at least one of each, probably two. */
+/* { dg-final { scan-assembler "movne" } } */
+/* { dg-final { scan-assembler "moveq" } } */
+/* { dg-final { scan-assembler "movcs" } } */
+/* { dg-final { scan-assembler "movcc" } } */
+/* { dg-final { scan-assembler "movmi" } } */
+/* { dg-final { scan-assembler "movpl" } } */
+/* { dg-final { scan-assembler "movvs" } } */
+/* { dg-final { scan-assembler "movvc" } } */
+/* { dg-final { scan-assembler "movhi" } } */
+/* { dg-final { scan-assembler "movls" } } */
+/* { dg-final { scan-assembler "movge" } } */
+/* { dg-final { scan-assembler "movls" } } */
+/* { dg-final { scan-assembler "movgt" } } */
+/* { dg-final { scan-assembler "movle" } } */
diff --git a/gcc/testsuite/gcc.target/arm/asm-flag-3.c b/gcc/testsuite/gcc.target/arm/asm-flag-3.c
new file mode 100644
index 00000000000..8b0bd8a00f9
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/asm-flag-3.c
@@ -0,0 +1,36 @@
+/* Test some of the valid @cc<cc> asm flag outputs. */
+/* { dg-do compile } */
+/* { dg-options "-O" } */
+
+#define DO(C) \
+void f##C(void) { char x; asm("" : "=@cc"#C(x)); if (!x) asm(""); asm(""); }
+
+DO(ne)
+DO(eq)
+DO(cs)
+DO(cc)
+DO(mi)
+DO(pl)
+DO(vs)
+DO(vc)
+DO(hi)
+DO(ls)
+DO(ge)
+DO(lt)
+DO(gt)
+DO(le)
+
+/* { dg-final { scan-assembler "bne" } } */
+/* { dg-final { scan-assembler "beq" } } */
+/* { dg-final { scan-assembler "bcs" } } */
+/* { dg-final { scan-assembler "bcc" } } */
+/* { dg-final { scan-assembler "bmi" } } */
+/* { dg-final { scan-assembler "bpl" } } */
+/* { dg-final { scan-assembler "bvs" } } */
+/* { dg-final { scan-assembler "bvc" } } */
+/* { dg-final { scan-assembler "bhi" } } */
+/* { dg-final { scan-assembler "bls" } } */
+/* { dg-final { scan-assembler "bge" } } */
+/* { dg-final { scan-assembler "blt" } } */
+/* { dg-final { scan-assembler "bgt" } } */
+/* { dg-final { scan-assembler "ble" } } */
diff --git a/gcc/testsuite/gcc.target/arm/asm-flag-5.c b/gcc/testsuite/gcc.target/arm/asm-flag-5.c
new file mode 100644
index 00000000000..4d4394e1478
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/asm-flag-5.c
@@ -0,0 +1,30 @@
+/* Test error conditions of asm flag outputs. */
+/* { dg-do compile } */
+/* { dg-options "" } */
+
+void f_B(void) { _Bool x; asm("" : "=@cccc"(x)); }
+void f_c(void) { char x; asm("" : "=@cccc"(x)); }
+void f_s(void) { short x; asm("" : "=@cccc"(x)); }
+void f_i(void) { int x; asm("" : "=@cccc"(x)); }
+void f_l(void) { long x; asm("" : "=@cccc"(x)); }
+void f_ll(void) { long long x; asm("" : "=@cccc"(x)); }
+
+void f_f(void)
+{
+ float x;
+ asm("" : "=@cccc"(x)); /* { dg-error invalid type } */
+}
+
+void f_d(void)
+{
+ double x;
+ asm("" : "=@cccc"(x)); /* { dg-error invalid type } */
+}
+
+struct S { int x[3]; };
+
+void f_S(void)
+{
+ struct S x;
+ asm("" : "=@cccc"(x)); /* { dg-error invalid type } */
+}
diff --git a/gcc/testsuite/gcc.target/arm/asm-flag-6.c b/gcc/testsuite/gcc.target/arm/asm-flag-6.c
new file mode 100644
index 00000000000..ef2e06afc37
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/asm-flag-6.c
@@ -0,0 +1,43 @@
+/* Executable testcase for 'output flags.' */
+/* { dg-do run } */
+
+int test_bits (long nzcv)
+{
+ long n, z, c, v;
+
+ __asm__ ("msr APSR_nzcvq, %[in]"
+ : "=@ccmi"(n), "=@cceq"(z), "=@cccs"(c), "=@ccvs"(v)
+ : [in] "r"(nzcv << 28));
+
+ return n * 8 + z * 4 + c * 2 + v == nzcv;
+}
+
+int test_cmp (long x, long y)
+{
+ long gt, lt, ge, le;
+
+ __asm__ ("cmp %[x], %[y]"
+ : "=@ccgt"(gt), "=@cclt"(lt), "=@ccge"(ge), "=@ccle"(le)
+ : [x] "r"(x), [y] "r"(y));
+
+ return (gt == (x > y)
+ && lt == (x < y)
+ && ge == (x >= y)
+ && le == (x <= y));
+}
+
+int main ()
+{
+ long i, j;
+
+ for (i = 0; i < 16; ++i)
+ if (!test_bits (i))
+ __builtin_abort ();
+
+ for (i = -1; i <= 1; ++i)
+ for (j = -1; j <= 1; ++j)
+ if (!test_cmp (i, j))
+ __builtin_abort ();
+
+ return 0;
+}
--
2.17.1
^ permalink raw reply [flat|nested] 11+ messages in thread
* [PATCH 1/6] aarch64: Add "c" constraint
2019-11-08 10:54 [PATCH 0/6] Implement asm flag outputs for arm + aarch64 Richard Henderson
` (4 preceding siblings ...)
2019-11-08 10:54 ` [PATCH 6/6] aarch64: Add testsuite checks for asm-flag Richard Henderson
@ 2019-11-08 10:54 ` Richard Henderson
2019-11-12 20:23 ` [PATCH 0/6] Implement asm flag outputs for arm + aarch64 Richard Sandiford
6 siblings, 0 replies; 11+ messages in thread
From: Richard Henderson @ 2019-11-08 10:54 UTC (permalink / raw)
To: gcc-patches
Cc: richard.earnshaw, james.greenhalgh, richard.sandiford,
marcus.shawcroft, kyrylo.tkachov
Mirror arm in letting "c" match the condition code register.
* config/aarch64/constraints.md (c): New constraint.
---
gcc/config/aarch64/constraints.md | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/gcc/config/aarch64/constraints.md b/gcc/config/aarch64/constraints.md
index d0c3dd5bc1f..b9e5d13e851 100644
--- a/gcc/config/aarch64/constraints.md
+++ b/gcc/config/aarch64/constraints.md
@@ -39,6 +39,10 @@
(define_register_constraint "y" "FP_LO8_REGS"
"Floating point and SIMD vector registers V0 - V7.")
+(define_constraint "c"
+ "@internal The condition code register."
+ (match_operand 0 "cc_register"))
+
(define_constraint "I"
"A constant that can be used with an ADD operation."
(and (match_code "const_int")
--
2.17.1
^ permalink raw reply [flat|nested] 11+ messages in thread
* [PATCH 3/6] arm: Rename CC_NOOVmode to CC_NZmode
2019-11-08 10:54 [PATCH 0/6] Implement asm flag outputs for arm + aarch64 Richard Henderson
@ 2019-11-08 10:54 ` Richard Henderson
2019-11-08 10:54 ` [PATCH 4/6] arm, aarch64: Add support for __GCC_ASM_FLAG_OUTPUTS__ Richard Henderson
` (5 subsequent siblings)
6 siblings, 0 replies; 11+ messages in thread
From: Richard Henderson @ 2019-11-08 10:54 UTC (permalink / raw)
To: gcc-patches
Cc: richard.earnshaw, james.greenhalgh, richard.sandiford,
marcus.shawcroft, kyrylo.tkachov
CC_NZmode is a more accurate description of what we require
from the mode, and matches up with the definition in aarch64.
Rename noov_comparison_operator to nz_comparison_operator
in order to match.
* config/arm/arm-modes.def (CC_NZ): Rename from CC_NOOV.
* config/arm/predicates.md (nz_comparison_operator): Rename
from noov_comparison_operator.
* config/arm/arm.c (arm_select_cc_mode): Use CC_NZmode name.
(arm_gen_dicompare_reg): Likewise.
(maybe_get_arm_condition_code): Likewise.
(thumb1_final_prescan_insn): Likewise.
(arm_emit_coreregs_64bit_shift): Likewise.
* config/arm/arm.md (addsi3_compare0): Likewise.
(*addsi3_compare0_scratch, subsi3_compare0): Likewise.
(*mulsi3_compare0, *mulsi3_compare0_v6): Likewise.
(*mulsi3_compare0_scratch, *mulsi3_compare0_scratch_v6): Likewise.
(*mulsi3addsi_compare0, *mulsi3addsi_compare0_v6): Likewise.
(*mulsi3addsi_compare0_scratch): Likewise.
(*mulsi3addsi_compare0_scratch_v6): Likewise.
(*andsi3_compare0, *andsi3_compare0_scratch): Likewise.
(*zeroextractsi_compare0_scratch): Likewise.
(*ne_zeroextractsi, *ne_zeroextractsi_shifted): Likewise.
(*ite_ne_zeroextractsi, *ite_ne_zeroextractsi_shifted): Likewise.
(andsi_not_shiftsi_si_scc_no_reuse): Likewise.
(andsi_not_shiftsi_si_scc): Likewise.
(*andsi_notsi_si_compare0, *andsi_notsi_si_compare0_scratch): Likewise.
(*iorsi3_compare0, *iorsi3_compare0_scratch): Likewise.
(*xorsi3_compare0, *xorsi3_compare0_scratch): Likewise.
(*shiftsi3_compare0, *shiftsi3_compare0_scratch): Likewise.
(*not_shiftsi_compare0, *not_shiftsi_compare0_scratch): Likewise.
(*notsi_compare0, *notsi_compare0_scratch): Likewise.
(return_addr_mask, *check_arch2): Likewise.
(*arith_shiftsi_compare0, *arith_shiftsi_compare0_scratch): Likewise.
(*sub_shiftsi_compare0, *sub_shiftsi_compare0_scratch): Likewise.
(compare_scc splitters): Likewise.
(movcond_addsi): Likewise.
* config/arm/thumb2.md (thumb2_addsi3_compare0): Likewise.
(*thumb2_addsi3_compare0_scratch): Likewise.
(*thumb2_mulsi_short_compare0): Likewise.
(*thumb2_mulsi_short_compare0_scratch): Likewise.
(compare peephole2s): Likewise.
* config/arm/thumb1.md (thumb1_cbz): Use CC_NZmode and
nz_comparison_operator names.
(cbranchsi4_insn): Likewise.
---
gcc/config/arm/arm.c | 12 +--
gcc/config/arm/arm-modes.def | 4 +-
gcc/config/arm/arm.md | 186 +++++++++++++++++------------------
gcc/config/arm/predicates.md | 2 +-
gcc/config/arm/thumb1.md | 8 +-
gcc/config/arm/thumb2.md | 34 +++----
6 files changed, 123 insertions(+), 123 deletions(-)
diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c
index eddd3ca93ed..b620322318b 100644
--- a/gcc/config/arm/arm.c
+++ b/gcc/config/arm/arm.c
@@ -15379,7 +15379,7 @@ arm_select_cc_mode (enum rtx_code op, rtx x, rtx y)
|| GET_CODE (x) == ASHIFT || GET_CODE (x) == ASHIFTRT
|| GET_CODE (x) == ROTATERT
|| (TARGET_32BIT && GET_CODE (x) == ZERO_EXTRACT)))
- return CC_NOOVmode;
+ return CC_NZmode;
/* A comparison of ~reg with a const is really a special
canoncialization of compare (~const, reg), which is a reverse
@@ -15495,11 +15495,11 @@ arm_gen_dicompare_reg (rtx_code code, rtx x, rtx y, rtx scratch)
}
rtx clobber = gen_rtx_CLOBBER (VOIDmode, scratch);
- cc_reg = gen_rtx_REG (CC_NOOVmode, CC_REGNUM);
+ cc_reg = gen_rtx_REG (CC_NZmode, CC_REGNUM);
rtx set
= gen_rtx_SET (cc_reg,
- gen_rtx_COMPARE (CC_NOOVmode,
+ gen_rtx_COMPARE (CC_NZmode,
gen_rtx_IOR (SImode, x_lo, x_hi),
const0_rtx));
emit_insn (gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, set,
@@ -23884,7 +23884,7 @@ maybe_get_arm_condition_code (rtx comparison)
return code;
return ARM_NV;
- case E_CC_NOOVmode:
+ case E_CC_NZmode:
switch (comp_code)
{
case NE: return ARM_NE;
@@ -25307,7 +25307,7 @@ thumb1_final_prescan_insn (rtx_insn *insn)
cfun->machine->thumb1_cc_insn = insn;
cfun->machine->thumb1_cc_op0 = SET_DEST (set);
cfun->machine->thumb1_cc_op1 = const0_rtx;
- cfun->machine->thumb1_cc_mode = CC_NOOVmode;
+ cfun->machine->thumb1_cc_mode = CC_NZmode;
if (INSN_CODE (insn) == CODE_FOR_thumb1_subsi3_insn)
{
rtx src1 = XEXP (SET_SRC (set), 1);
@@ -30484,7 +30484,7 @@ arm_emit_coreregs_64bit_shift (enum rtx_code code, rtx out, rtx in,
else
{
/* We have a shift-by-register. */
- rtx cc_reg = gen_rtx_REG (CC_NOOVmode, CC_REGNUM);
+ rtx cc_reg = gen_rtx_REG (CC_NZmode, CC_REGNUM);
/* This alternative requires the scratch registers. */
gcc_assert (scratch1 && REG_P (scratch1));
diff --git a/gcc/config/arm/arm-modes.def b/gcc/config/arm/arm-modes.def
index a6b520df32d..2ce53e0efba 100644
--- a/gcc/config/arm/arm-modes.def
+++ b/gcc/config/arm/arm-modes.def
@@ -29,7 +29,7 @@ ADJUST_FLOAT_FORMAT (HF, ((arm_fp16_format == ARM_FP16_FORMAT_ALTERNATIVE)
/* CCFPEmode should be used with floating inequalities,
CCFPmode should be used with floating equalities.
- CC_NOOVmode should be used with SImode integer equalities.
+ CC_NZmode should be used if only the N and Z bits are set correctly.
CC_Zmode should be used if only the Z flag is set correctly
CC_Cmode should be used if only the C flag is set correctly, after an
addition.
@@ -47,7 +47,7 @@ ADJUST_FLOAT_FORMAT (HF, ((arm_fp16_format == ARM_FP16_FORMAT_ALTERNATIVE)
against one of the other operands.
CCmode should be used otherwise. */
-CC_MODE (CC_NOOV);
+CC_MODE (CC_NZ);
CC_MODE (CC_Z);
CC_MODE (CC_NV);
CC_MODE (CC_SWP);
diff --git a/gcc/config/arm/arm.md b/gcc/config/arm/arm.md
index 4f035cbfddd..1e325b8924d 100644
--- a/gcc/config/arm/arm.md
+++ b/gcc/config/arm/arm.md
@@ -1062,8 +1062,8 @@
)
(define_insn "addsi3_compare0"
- [(set (reg:CC_NOOV CC_REGNUM)
- (compare:CC_NOOV
+ [(set (reg:CC_NZ CC_REGNUM)
+ (compare:CC_NZ
(plus:SI (match_operand:SI 1 "s_register_operand" "r, r,r")
(match_operand:SI 2 "arm_add_operand" "I,L,r"))
(const_int 0)))
@@ -1079,8 +1079,8 @@
)
(define_insn "*addsi3_compare0_scratch"
- [(set (reg:CC_NOOV CC_REGNUM)
- (compare:CC_NOOV
+ [(set (reg:CC_NZ CC_REGNUM)
+ (compare:CC_NZ
(plus:SI (match_operand:SI 0 "s_register_operand" "r, r, r")
(match_operand:SI 1 "arm_add_operand" "I,L, r"))
(const_int 0)))]
@@ -2001,8 +2001,8 @@
)
(define_insn "subsi3_compare0"
- [(set (reg:CC_NOOV CC_REGNUM)
- (compare:CC_NOOV
+ [(set (reg:CC_NZ CC_REGNUM)
+ (compare:CC_NZ
(minus:SI (match_operand:SI 1 "arm_rhs_operand" "r,r,I")
(match_operand:SI 2 "arm_rhs_operand" "I,r,r"))
(const_int 0)))
@@ -2240,8 +2240,8 @@
)
(define_insn "*mulsi3_compare0"
- [(set (reg:CC_NOOV CC_REGNUM)
- (compare:CC_NOOV (mult:SI
+ [(set (reg:CC_NZ CC_REGNUM)
+ (compare:CC_NZ (mult:SI
(match_operand:SI 2 "s_register_operand" "r,r")
(match_operand:SI 1 "s_register_operand" "%0,r"))
(const_int 0)))
@@ -2254,8 +2254,8 @@
)
(define_insn "*mulsi3_compare0_v6"
- [(set (reg:CC_NOOV CC_REGNUM)
- (compare:CC_NOOV (mult:SI
+ [(set (reg:CC_NZ CC_REGNUM)
+ (compare:CC_NZ (mult:SI
(match_operand:SI 2 "s_register_operand" "r")
(match_operand:SI 1 "s_register_operand" "r"))
(const_int 0)))
@@ -2268,8 +2268,8 @@
)
(define_insn "*mulsi_compare0_scratch"
- [(set (reg:CC_NOOV CC_REGNUM)
- (compare:CC_NOOV (mult:SI
+ [(set (reg:CC_NZ CC_REGNUM)
+ (compare:CC_NZ (mult:SI
(match_operand:SI 2 "s_register_operand" "r,r")
(match_operand:SI 1 "s_register_operand" "%0,r"))
(const_int 0)))
@@ -2281,8 +2281,8 @@
)
(define_insn "*mulsi_compare0_scratch_v6"
- [(set (reg:CC_NOOV CC_REGNUM)
- (compare:CC_NOOV (mult:SI
+ [(set (reg:CC_NZ CC_REGNUM)
+ (compare:CC_NZ (mult:SI
(match_operand:SI 2 "s_register_operand" "r")
(match_operand:SI 1 "s_register_operand" "r"))
(const_int 0)))
@@ -2294,8 +2294,8 @@
)
(define_insn "*mulsi3addsi_compare0"
- [(set (reg:CC_NOOV CC_REGNUM)
- (compare:CC_NOOV
+ [(set (reg:CC_NZ CC_REGNUM)
+ (compare:CC_NZ
(plus:SI (mult:SI
(match_operand:SI 2 "s_register_operand" "r,r,r,r")
(match_operand:SI 1 "s_register_operand" "%0,r,0,r"))
@@ -2311,8 +2311,8 @@
)
(define_insn "*mulsi3addsi_compare0_v6"
- [(set (reg:CC_NOOV CC_REGNUM)
- (compare:CC_NOOV
+ [(set (reg:CC_NZ CC_REGNUM)
+ (compare:CC_NZ
(plus:SI (mult:SI
(match_operand:SI 2 "s_register_operand" "r")
(match_operand:SI 1 "s_register_operand" "r"))
@@ -2328,8 +2328,8 @@
)
(define_insn "*mulsi3addsi_compare0_scratch"
- [(set (reg:CC_NOOV CC_REGNUM)
- (compare:CC_NOOV
+ [(set (reg:CC_NZ CC_REGNUM)
+ (compare:CC_NZ
(plus:SI (mult:SI
(match_operand:SI 2 "s_register_operand" "r,r,r,r")
(match_operand:SI 1 "s_register_operand" "%0,r,0,r"))
@@ -2343,8 +2343,8 @@
)
(define_insn "*mulsi3addsi_compare0_scratch_v6"
- [(set (reg:CC_NOOV CC_REGNUM)
- (compare:CC_NOOV
+ [(set (reg:CC_NZ CC_REGNUM)
+ (compare:CC_NZ
(plus:SI (mult:SI
(match_operand:SI 2 "s_register_operand" "r")
(match_operand:SI 1 "s_register_operand" "r"))
@@ -2834,8 +2834,8 @@
)
(define_insn "*andsi3_compare0"
- [(set (reg:CC_NOOV CC_REGNUM)
- (compare:CC_NOOV
+ [(set (reg:CC_NZ CC_REGNUM)
+ (compare:CC_NZ
(and:SI (match_operand:SI 1 "s_register_operand" "r,r,r")
(match_operand:SI 2 "arm_not_operand" "I,K,r"))
(const_int 0)))
@@ -2851,8 +2851,8 @@
)
(define_insn "*andsi3_compare0_scratch"
- [(set (reg:CC_NOOV CC_REGNUM)
- (compare:CC_NOOV
+ [(set (reg:CC_NZ CC_REGNUM)
+ (compare:CC_NZ
(and:SI (match_operand:SI 0 "s_register_operand" "r,r,r")
(match_operand:SI 1 "arm_not_operand" "I,K,r"))
(const_int 0)))
@@ -2867,8 +2867,8 @@
)
(define_insn "*zeroextractsi_compare0_scratch"
- [(set (reg:CC_NOOV CC_REGNUM)
- (compare:CC_NOOV (zero_extract:SI
+ [(set (reg:CC_NZ CC_REGNUM)
+ (compare:CC_NZ (zero_extract:SI
(match_operand:SI 0 "s_register_operand" "r")
(match_operand 1 "const_int_operand" "n")
(match_operand 2 "const_int_operand" "n"))
@@ -2908,12 +2908,12 @@
&& INTVAL (operands[2]) > 0
&& INTVAL (operands[2]) + (INTVAL (operands[3]) & 1) <= 8
&& INTVAL (operands[2]) + INTVAL (operands[3]) <= 32)"
- [(parallel [(set (reg:CC_NOOV CC_REGNUM)
- (compare:CC_NOOV (and:SI (match_dup 1) (match_dup 2))
+ [(parallel [(set (reg:CC_NZ CC_REGNUM)
+ (compare:CC_NZ (and:SI (match_dup 1) (match_dup 2))
(const_int 0)))
(set (match_dup 0) (and:SI (match_dup 1) (match_dup 2)))])
(set (match_dup 0)
- (if_then_else:SI (eq (reg:CC_NOOV CC_REGNUM) (const_int 0))
+ (if_then_else:SI (eq (reg:CC_NZ CC_REGNUM) (const_int 0))
(match_dup 0) (const_int 1)))]
"
operands[2] = GEN_INT (((1 << INTVAL (operands[2])) - 1)
@@ -2938,12 +2938,12 @@
"TARGET_ARM"
"#"
"TARGET_ARM"
- [(parallel [(set (reg:CC_NOOV CC_REGNUM)
- (compare:CC_NOOV (ashift:SI (match_dup 1) (match_dup 2))
+ [(parallel [(set (reg:CC_NZ CC_REGNUM)
+ (compare:CC_NZ (ashift:SI (match_dup 1) (match_dup 2))
(const_int 0)))
(set (match_dup 0) (ashift:SI (match_dup 1) (match_dup 2)))])
(set (match_dup 0)
- (if_then_else:SI (eq (reg:CC_NOOV CC_REGNUM) (const_int 0))
+ (if_then_else:SI (eq (reg:CC_NZ CC_REGNUM) (const_int 0))
(match_dup 0) (const_int 1)))]
"
operands[2] = GEN_INT (32 - INTVAL (operands[2]));
@@ -2976,12 +2976,12 @@
&& INTVAL (operands[2]) + (INTVAL (operands[3]) & 1) <= 8
&& INTVAL (operands[2]) + INTVAL (operands[3]) <= 32)
&& !reg_overlap_mentioned_p (operands[0], operands[4])"
- [(parallel [(set (reg:CC_NOOV CC_REGNUM)
- (compare:CC_NOOV (and:SI (match_dup 1) (match_dup 2))
+ [(parallel [(set (reg:CC_NZ CC_REGNUM)
+ (compare:CC_NZ (and:SI (match_dup 1) (match_dup 2))
(const_int 0)))
(set (match_dup 0) (and:SI (match_dup 1) (match_dup 2)))])
(set (match_dup 0)
- (if_then_else:SI (eq (reg:CC_NOOV CC_REGNUM) (const_int 0))
+ (if_then_else:SI (eq (reg:CC_NZ CC_REGNUM) (const_int 0))
(match_dup 0) (match_dup 4)))]
"
operands[2] = GEN_INT (((1 << INTVAL (operands[2])) - 1)
@@ -3005,12 +3005,12 @@
"TARGET_ARM && !reg_overlap_mentioned_p (operands[0], operands[3])"
"#"
"TARGET_ARM && !reg_overlap_mentioned_p (operands[0], operands[3])"
- [(parallel [(set (reg:CC_NOOV CC_REGNUM)
- (compare:CC_NOOV (ashift:SI (match_dup 1) (match_dup 2))
+ [(parallel [(set (reg:CC_NZ CC_REGNUM)
+ (compare:CC_NZ (ashift:SI (match_dup 1) (match_dup 2))
(const_int 0)))
(set (match_dup 0) (ashift:SI (match_dup 1) (match_dup 2)))])
(set (match_dup 0)
- (if_then_else:SI (eq (reg:CC_NOOV CC_REGNUM) (const_int 0))
+ (if_then_else:SI (eq (reg:CC_NZ CC_REGNUM) (const_int 0))
(match_dup 0) (match_dup 3)))]
"
operands[2] = GEN_INT (32 - INTVAL (operands[2]));
@@ -3328,8 +3328,8 @@
;; bics output. Pattern restricts Thumb2 shift operand as bics for Thumb2
;; does not support shift by register.
(define_insn "andsi_not_shiftsi_si_scc_no_reuse"
- [(set (reg:CC_NOOV CC_REGNUM)
- (compare:CC_NOOV
+ [(set (reg:CC_NZ CC_REGNUM)
+ (compare:CC_NZ
(and:SI (not:SI (match_operator:SI 0 "shift_operator"
[(match_operand:SI 1 "s_register_operand" "r,r")
(match_operand:SI 2 "shift_amount_operand" "M,r")]))
@@ -3348,8 +3348,8 @@
;; Same as andsi_not_shiftsi_si_scc_no_reuse, but the bics result is also
;; getting reused later.
(define_insn "andsi_not_shiftsi_si_scc"
- [(parallel [(set (reg:CC_NOOV CC_REGNUM)
- (compare:CC_NOOV
+ [(parallel [(set (reg:CC_NZ CC_REGNUM)
+ (compare:CC_NZ
(and:SI (not:SI (match_operator:SI 0 "shift_operator"
[(match_operand:SI 1 "s_register_operand" "r,r")
(match_operand:SI 2 "shift_amount_operand" "M,r")]))
@@ -3370,8 +3370,8 @@
)
(define_insn "*andsi_notsi_si_compare0"
- [(set (reg:CC_NOOV CC_REGNUM)
- (compare:CC_NOOV
+ [(set (reg:CC_NZ CC_REGNUM)
+ (compare:CC_NZ
(and:SI (not:SI (match_operand:SI 2 "s_register_operand" "r"))
(match_operand:SI 1 "s_register_operand" "r"))
(const_int 0)))
@@ -3384,8 +3384,8 @@
)
(define_insn "*andsi_notsi_si_compare0_scratch"
- [(set (reg:CC_NOOV CC_REGNUM)
- (compare:CC_NOOV
+ [(set (reg:CC_NZ CC_REGNUM)
+ (compare:CC_NZ
(and:SI (not:SI (match_operand:SI 2 "s_register_operand" "r"))
(match_operand:SI 1 "s_register_operand" "r"))
(const_int 0)))
@@ -3474,8 +3474,8 @@
)
(define_insn "*iorsi3_compare0"
- [(set (reg:CC_NOOV CC_REGNUM)
- (compare:CC_NOOV
+ [(set (reg:CC_NZ CC_REGNUM)
+ (compare:CC_NZ
(ior:SI (match_operand:SI 1 "s_register_operand" "%r,0,r")
(match_operand:SI 2 "arm_rhs_operand" "I,l,r"))
(const_int 0)))
@@ -3490,8 +3490,8 @@
)
(define_insn "*iorsi3_compare0_scratch"
- [(set (reg:CC_NOOV CC_REGNUM)
- (compare:CC_NOOV
+ [(set (reg:CC_NZ CC_REGNUM)
+ (compare:CC_NZ
(ior:SI (match_operand:SI 1 "s_register_operand" "%r,0,r")
(match_operand:SI 2 "arm_rhs_operand" "I,l,r"))
(const_int 0)))
@@ -3564,8 +3564,8 @@
)
(define_insn "*xorsi3_compare0"
- [(set (reg:CC_NOOV CC_REGNUM)
- (compare:CC_NOOV (xor:SI (match_operand:SI 1 "s_register_operand" "r,r")
+ [(set (reg:CC_NZ CC_REGNUM)
+ (compare:CC_NZ (xor:SI (match_operand:SI 1 "s_register_operand" "r,r")
(match_operand:SI 2 "arm_rhs_operand" "I,r"))
(const_int 0)))
(set (match_operand:SI 0 "s_register_operand" "=r,r")
@@ -3577,8 +3577,8 @@
)
(define_insn "*xorsi3_compare0_scratch"
- [(set (reg:CC_NOOV CC_REGNUM)
- (compare:CC_NOOV (xor:SI (match_operand:SI 0 "s_register_operand" "r,r")
+ [(set (reg:CC_NZ CC_REGNUM)
+ (compare:CC_NZ (xor:SI (match_operand:SI 0 "s_register_operand" "r,r")
(match_operand:SI 1 "arm_rhs_operand" "I,r"))
(const_int 0)))]
"TARGET_32BIT"
@@ -4227,8 +4227,8 @@
)
(define_insn "*shiftsi3_compare0"
- [(set (reg:CC_NOOV CC_REGNUM)
- (compare:CC_NOOV (match_operator:SI 3 "shift_operator"
+ [(set (reg:CC_NZ CC_REGNUM)
+ (compare:CC_NZ (match_operator:SI 3 "shift_operator"
[(match_operand:SI 1 "s_register_operand" "r,r")
(match_operand:SI 2 "arm_rhs_operand" "M,r")])
(const_int 0)))
@@ -4242,8 +4242,8 @@
)
(define_insn "*shiftsi3_compare0_scratch"
- [(set (reg:CC_NOOV CC_REGNUM)
- (compare:CC_NOOV (match_operator:SI 3 "shift_operator"
+ [(set (reg:CC_NZ CC_REGNUM)
+ (compare:CC_NZ (match_operator:SI 3 "shift_operator"
[(match_operand:SI 1 "s_register_operand" "r,r")
(match_operand:SI 2 "arm_rhs_operand" "M,r")])
(const_int 0)))
@@ -4268,8 +4268,8 @@
(set_attr "type" "mvn_shift,mvn_shift_reg")])
(define_insn "*not_shiftsi_compare0"
- [(set (reg:CC_NOOV CC_REGNUM)
- (compare:CC_NOOV
+ [(set (reg:CC_NZ CC_REGNUM)
+ (compare:CC_NZ
(not:SI (match_operator:SI 3 "shift_operator"
[(match_operand:SI 1 "s_register_operand" "r,r")
(match_operand:SI 2 "shift_amount_operand" "M,r")]))
@@ -4284,8 +4284,8 @@
(set_attr "type" "mvn_shift,mvn_shift_reg")])
(define_insn "*not_shiftsi_compare0_scratch"
- [(set (reg:CC_NOOV CC_REGNUM)
- (compare:CC_NOOV
+ [(set (reg:CC_NZ CC_REGNUM)
+ (compare:CC_NZ
(not:SI (match_operator:SI 3 "shift_operator"
[(match_operand:SI 1 "s_register_operand" "r,r")
(match_operand:SI 2 "shift_amount_operand" "M,r")]))
@@ -4875,8 +4875,8 @@
)
(define_insn "*notsi_compare0"
- [(set (reg:CC_NOOV CC_REGNUM)
- (compare:CC_NOOV (not:SI (match_operand:SI 1 "s_register_operand" "r"))
+ [(set (reg:CC_NZ CC_REGNUM)
+ (compare:CC_NZ (not:SI (match_operand:SI 1 "s_register_operand" "r"))
(const_int 0)))
(set (match_operand:SI 0 "s_register_operand" "=r")
(not:SI (match_dup 1)))]
@@ -4887,8 +4887,8 @@
)
(define_insn "*notsi_compare0_scratch"
- [(set (reg:CC_NOOV CC_REGNUM)
- (compare:CC_NOOV (not:SI (match_operand:SI 1 "s_register_operand" "r"))
+ [(set (reg:CC_NZ CC_REGNUM)
+ (compare:CC_NZ (not:SI (match_operand:SI 1 "s_register_operand" "r"))
(const_int 0)))
(clobber (match_scratch:SI 0 "=r"))]
"TARGET_32BIT"
@@ -8384,7 +8384,7 @@
(define_expand "return_addr_mask"
[(set (match_dup 1)
- (compare:CC_NOOV (unspec [(const_int 0)] UNSPEC_CHECK_ARCH)
+ (compare:CC_NZ (unspec [(const_int 0)] UNSPEC_CHECK_ARCH)
(const_int 0)))
(set (match_operand:SI 0 "s_register_operand")
(if_then_else:SI (eq (match_dup 1) (const_int 0))
@@ -8392,12 +8392,12 @@
(const_int 67108860)))] ; 0x03fffffc
"TARGET_ARM"
"
- operands[1] = gen_rtx_REG (CC_NOOVmode, CC_REGNUM);
+ operands[1] = gen_rtx_REG (CC_NZmode, CC_REGNUM);
")
(define_insn "*check_arch2"
- [(set (match_operand:CC_NOOV 0 "cc_register" "")
- (compare:CC_NOOV (unspec [(const_int 0)] UNSPEC_CHECK_ARCH)
+ [(set (match_operand:CC_NZ 0 "cc_register" "")
+ (compare:CC_NZ (unspec [(const_int 0)] UNSPEC_CHECK_ARCH)
(const_int 0)))]
"TARGET_ARM"
"teq\\t%|r0, %|r0\;teq\\t%|pc, %|pc"
@@ -8933,8 +8933,8 @@
"")
(define_insn "*arith_shiftsi_compare0"
- [(set (reg:CC_NOOV CC_REGNUM)
- (compare:CC_NOOV
+ [(set (reg:CC_NZ CC_REGNUM)
+ (compare:CC_NZ
(match_operator:SI 1 "shiftable_operator"
[(match_operator:SI 3 "shift_operator"
[(match_operand:SI 4 "s_register_operand" "r,r")
@@ -8952,8 +8952,8 @@
(set_attr "type" "alus_shift_imm,alus_shift_reg")])
(define_insn "*arith_shiftsi_compare0_scratch"
- [(set (reg:CC_NOOV CC_REGNUM)
- (compare:CC_NOOV
+ [(set (reg:CC_NZ CC_REGNUM)
+ (compare:CC_NZ
(match_operator:SI 1 "shiftable_operator"
[(match_operator:SI 3 "shift_operator"
[(match_operand:SI 4 "s_register_operand" "r,r")
@@ -8983,8 +8983,8 @@
(set_attr "type" "alus_shift_imm,alus_shift_reg")])
(define_insn "*sub_shiftsi_compare0"
- [(set (reg:CC_NOOV CC_REGNUM)
- (compare:CC_NOOV
+ [(set (reg:CC_NZ CC_REGNUM)
+ (compare:CC_NZ
(minus:SI (match_operand:SI 1 "s_register_operand" "r,r")
(match_operator:SI 2 "shift_operator"
[(match_operand:SI 3 "s_register_operand" "r,r")
@@ -9001,8 +9001,8 @@
(set_attr "type" "alus_shift_imm,alus_shift_reg")])
(define_insn "*sub_shiftsi_compare0_scratch"
- [(set (reg:CC_NOOV CC_REGNUM)
- (compare:CC_NOOV
+ [(set (reg:CC_NZ CC_REGNUM)
+ (compare:CC_NZ
(minus:SI (match_operand:SI 1 "s_register_operand" "r,r")
(match_operator:SI 2 "shift_operator"
[(match_operand:SI 3 "s_register_operand" "r,r")
@@ -9146,11 +9146,11 @@
(clobber (reg:CC CC_REGNUM))]
"TARGET_32BIT && reload_completed"
[(parallel
- [(set (reg:CC_NOOV CC_REGNUM)
- (compare:CC_NOOV (minus:SI (match_dup 1) (match_dup 2))
+ [(set (reg:CC_NZ CC_REGNUM)
+ (compare:CC_NZ (minus:SI (match_dup 1) (match_dup 2))
(const_int 0)))
(set (match_dup 0) (minus:SI (match_dup 1) (match_dup 2)))])
- (cond_exec (ne:CC_NOOV (reg:CC_NOOV CC_REGNUM) (const_int 0))
+ (cond_exec (ne:CC_NZ (reg:CC_NZ CC_REGNUM) (const_int 0))
(set (match_dup 0) (const_int 1)))])
(define_insn_and_split "*compare_scc"
@@ -9855,8 +9855,8 @@
)
(define_split
- [(set (reg:CC_NOOV CC_REGNUM)
- (compare:CC_NOOV (ior:SI
+ [(set (reg:CC_NZ CC_REGNUM)
+ (compare:CC_NZ (ior:SI
(and:SI (match_operand:SI 0 "s_register_operand" "")
(const_int 1))
(match_operator:SI 1 "arm_comparison_operator"
@@ -9868,14 +9868,14 @@
[(set (match_dup 4)
(ior:SI (match_op_dup 1 [(match_dup 2) (match_dup 3)])
(match_dup 0)))
- (set (reg:CC_NOOV CC_REGNUM)
- (compare:CC_NOOV (and:SI (match_dup 4) (const_int 1))
+ (set (reg:CC_NZ CC_REGNUM)
+ (compare:CC_NZ (and:SI (match_dup 4) (const_int 1))
(const_int 0)))]
"")
(define_split
- [(set (reg:CC_NOOV CC_REGNUM)
- (compare:CC_NOOV (ior:SI
+ [(set (reg:CC_NZ CC_REGNUM)
+ (compare:CC_NZ (ior:SI
(match_operator:SI 1 "arm_comparison_operator"
[(match_operand:SI 2 "s_register_operand" "")
(match_operand:SI 3 "arm_add_operand" "")])
@@ -9887,8 +9887,8 @@
[(set (match_dup 4)
(ior:SI (match_op_dup 1 [(match_dup 2) (match_dup 3)])
(match_dup 0)))
- (set (reg:CC_NOOV CC_REGNUM)
- (compare:CC_NOOV (and:SI (match_dup 4) (const_int 1))
+ (set (reg:CC_NZ CC_REGNUM)
+ (compare:CC_NZ (and:SI (match_dup 4) (const_int 1))
(const_int 0)))]
"")
;; ??? The conditional patterns above need checking for Thumb-2 usefulness
@@ -9977,8 +9977,8 @@
"TARGET_32BIT"
"#"
"&& reload_completed"
- [(set (reg:CC_NOOV CC_REGNUM)
- (compare:CC_NOOV
+ [(set (reg:CC_NZ CC_REGNUM)
+ (compare:CC_NZ
(plus:SI (match_dup 3)
(match_dup 4))
(const_int 0)))
diff --git a/gcc/config/arm/predicates.md b/gcc/config/arm/predicates.md
index 267c446c03e..da208b62724 100644
--- a/gcc/config/arm/predicates.md
+++ b/gcc/config/arm/predicates.md
@@ -422,7 +422,7 @@
(match_operand 0 "arm_vsel_comparison_operator"))
(match_operand 0 "expandable_comparison_operator")))
-(define_special_predicate "noov_comparison_operator"
+(define_special_predicate "nz_comparison_operator"
(match_code "lt,ge,eq,ne"))
(define_special_predicate "minmax_operator"
diff --git a/gcc/config/arm/thumb1.md b/gcc/config/arm/thumb1.md
index 5c70200bef3..9df793cc47c 100644
--- a/gcc/config/arm/thumb1.md
+++ b/gcc/config/arm/thumb1.md
@@ -1023,9 +1023,9 @@
if (!rtx_equal_p (cfun->machine->thumb1_cc_op0, operands[1])
|| !rtx_equal_p (cfun->machine->thumb1_cc_op1, operands[2]))
t = NULL_RTX;
- if (cfun->machine->thumb1_cc_mode == CC_NOOVmode)
+ if (cfun->machine->thumb1_cc_mode == CC_NZmode)
{
- if (!noov_comparison_operator (operands[0], VOIDmode))
+ if (!nz_comparison_operator (operands[0], VOIDmode))
t = NULL_RTX;
}
else if (cfun->machine->thumb1_cc_mode != CCmode)
@@ -1097,9 +1097,9 @@
if (!rtx_equal_p (cfun->machine->thumb1_cc_op0, operands[1])
|| !rtx_equal_p (cfun->machine->thumb1_cc_op1, operands[2]))
t = NULL_RTX;
- if (cfun->machine->thumb1_cc_mode == CC_NOOVmode)
+ if (cfun->machine->thumb1_cc_mode == CC_NZmode)
{
- if (!noov_comparison_operator (operands[0], VOIDmode))
+ if (!nz_comparison_operator (operands[0], VOIDmode))
t = NULL_RTX;
}
else if (cfun->machine->thumb1_cc_mode != CCmode)
diff --git a/gcc/config/arm/thumb2.md b/gcc/config/arm/thumb2.md
index 7fce50b045b..2558e404b88 100644
--- a/gcc/config/arm/thumb2.md
+++ b/gcc/config/arm/thumb2.md
@@ -1287,8 +1287,8 @@
)
(define_insn "thumb2_addsi3_compare0"
- [(set (reg:CC_NOOV CC_REGNUM)
- (compare:CC_NOOV
+ [(set (reg:CC_NZ CC_REGNUM)
+ (compare:CC_NZ
(plus:SI (match_operand:SI 1 "s_register_operand" "l, 0, r")
(match_operand:SI 2 "arm_add_operand" "lPt,Ps,rIL"))
(const_int 0)))
@@ -1321,8 +1321,8 @@
)
(define_insn "*thumb2_addsi3_compare0_scratch"
- [(set (reg:CC_NOOV CC_REGNUM)
- (compare:CC_NOOV
+ [(set (reg:CC_NZ CC_REGNUM)
+ (compare:CC_NZ
(plus:SI (match_operand:SI 0 "s_register_operand" "l, r")
(match_operand:SI 1 "arm_add_operand" "lPv,rIL"))
(const_int 0)))]
@@ -1359,8 +1359,8 @@
(set_attr "type" "muls")])
(define_insn "*thumb2_mulsi_short_compare0"
- [(set (reg:CC_NOOV CC_REGNUM)
- (compare:CC_NOOV
+ [(set (reg:CC_NZ CC_REGNUM)
+ (compare:CC_NZ
(mult:SI (match_operand:SI 1 "register_operand" "%0")
(match_operand:SI 2 "register_operand" "l"))
(const_int 0)))
@@ -1372,8 +1372,8 @@
(set_attr "type" "muls")])
(define_insn "*thumb2_mulsi_short_compare0_scratch"
- [(set (reg:CC_NOOV CC_REGNUM)
- (compare:CC_NOOV
+ [(set (reg:CC_NZ CC_REGNUM)
+ (compare:CC_NZ
(mult:SI (match_operand:SI 1 "register_operand" "%0")
(match_operand:SI 2 "register_operand" "l"))
(const_int 0)))
@@ -1477,15 +1477,15 @@
)
(define_peephole2
- [(set (match_operand:CC_NOOV 0 "cc_register" "")
- (compare:CC_NOOV (zero_extract:SI
+ [(set (match_operand:CC_NZ 0 "cc_register" "")
+ (compare:CC_NZ (zero_extract:SI
(match_operand:SI 1 "low_register_operand" "")
(const_int 1)
(match_operand:SI 2 "const_int_operand" ""))
(const_int 0)))
(match_scratch:SI 3 "l")
(set (pc)
- (if_then_else (match_operator:CC_NOOV 4 "equality_operator"
+ (if_then_else (match_operator:CC_NZ 4 "equality_operator"
[(match_dup 0) (const_int 0)])
(match_operand 5 "" "")
(match_operand 6 "" "")))]
@@ -1493,7 +1493,7 @@
&& (INTVAL (operands[2]) >= 0 && INTVAL (operands[2]) < 32)
&& peep2_reg_dead_p (2, operands[0])"
[(parallel [(set (match_dup 0)
- (compare:CC_NOOV (ashift:SI (match_dup 1) (match_dup 2))
+ (compare:CC_NZ (ashift:SI (match_dup 1) (match_dup 2))
(const_int 0)))
(clobber (match_dup 3))])
(set (pc)
@@ -1506,15 +1506,15 @@
")
(define_peephole2
- [(set (match_operand:CC_NOOV 0 "cc_register" "")
- (compare:CC_NOOV (zero_extract:SI
+ [(set (match_operand:CC_NZ 0 "cc_register" "")
+ (compare:CC_NZ (zero_extract:SI
(match_operand:SI 1 "low_register_operand" "")
(match_operand:SI 2 "const_int_operand" "")
(const_int 0))
(const_int 0)))
(match_scratch:SI 3 "l")
(set (pc)
- (if_then_else (match_operator:CC_NOOV 4 "equality_operator"
+ (if_then_else (match_operator:CC_NZ 4 "equality_operator"
[(match_dup 0) (const_int 0)])
(match_operand 5 "" "")
(match_operand 6 "" "")))]
@@ -1522,8 +1522,8 @@
&& (INTVAL (operands[2]) > 0 && INTVAL (operands[2]) < 32)
&& peep2_reg_dead_p (2, operands[0])"
[(parallel [(set (match_dup 0)
- (compare:CC_NOOV (ashift:SI (match_dup 1) (match_dup 2))
- (const_int 0)))
+ (compare:CC_NZ (ashift:SI (match_dup 1) (match_dup 2))
+ (const_int 0)))
(clobber (match_dup 3))])
(set (pc)
(if_then_else (match_op_dup 4 [(match_dup 0) (const_int 0)])
--
2.17.1
^ permalink raw reply [flat|nested] 11+ messages in thread
* [PATCH 6/6] aarch64: Add testsuite checks for asm-flag
2019-11-08 10:54 [PATCH 0/6] Implement asm flag outputs for arm + aarch64 Richard Henderson
` (3 preceding siblings ...)
2019-11-08 10:54 ` [PATCH 2/6] arm: Fix the "c" constraint Richard Henderson
@ 2019-11-08 10:54 ` Richard Henderson
2019-11-08 10:54 ` [PATCH 1/6] aarch64: Add "c" constraint Richard Henderson
2019-11-12 20:23 ` [PATCH 0/6] Implement asm flag outputs for arm + aarch64 Richard Sandiford
6 siblings, 0 replies; 11+ messages in thread
From: Richard Henderson @ 2019-11-08 10:54 UTC (permalink / raw)
To: gcc-patches
Cc: richard.earnshaw, james.greenhalgh, richard.sandiford,
marcus.shawcroft, kyrylo.tkachov
Inspired by the tests in gcc.target/i386. Testing code generation,
diagnostics, and execution.
* gcc.target/aarch64/asm-flag-1.c: New test.
* gcc.target/aarch64/asm-flag-3.c: New test.
* gcc.target/aarch64/asm-flag-5.c: New test.
* gcc.target/aarch64/asm-flag-6.c: New test.
---
gcc/testsuite/gcc.target/aarch64/asm-flag-1.c | 34 +++++++++++++++
gcc/testsuite/gcc.target/aarch64/asm-flag-3.c | 36 ++++++++++++++++
gcc/testsuite/gcc.target/aarch64/asm-flag-5.c | 30 +++++++++++++
gcc/testsuite/gcc.target/aarch64/asm-flag-6.c | 43 +++++++++++++++++++
4 files changed, 143 insertions(+)
create mode 100644 gcc/testsuite/gcc.target/aarch64/asm-flag-1.c
create mode 100644 gcc/testsuite/gcc.target/aarch64/asm-flag-3.c
create mode 100644 gcc/testsuite/gcc.target/aarch64/asm-flag-5.c
create mode 100644 gcc/testsuite/gcc.target/aarch64/asm-flag-6.c
diff --git a/gcc/testsuite/gcc.target/aarch64/asm-flag-1.c b/gcc/testsuite/gcc.target/aarch64/asm-flag-1.c
new file mode 100644
index 00000000000..e3e79c29b8f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/asm-flag-1.c
@@ -0,0 +1,34 @@
+/* Test the valid @cc<cc> asm flag outputs. */
+/* { dg-do compile } */
+/* { dg-options "-O" } */
+
+#ifndef __GCC_ASM_FLAG_OUTPUTS__
+#error "missing preprocessor define"
+#endif
+
+void f(char *out)
+{
+ asm(""
+ : "=@ccne"(out[0]), "=@cceq"(out[1]),
+ "=@cccs"(out[2]), "=@cccc"(out[3]),
+ "=@ccmi"(out[4]), "=@ccpl"(out[5]),
+ "=@ccvs"(out[6]), "=@ccvc"(out[7]),
+ "=@cchi"(out[8]), "=@ccls"(out[9]),
+ "=@ccge"(out[10]), "=@cclt"(out[11]),
+ "=@ccgt"(out[12]), "=@ccle"(out[13]));
+}
+
+/* { dg-final { scan-assembler "cset.*, ne" } } */
+/* { dg-final { scan-assembler "cset.*, eq" } } */
+/* { dg-final { scan-assembler "cset.*, cs" } } */
+/* { dg-final { scan-assembler "cset.*, cc" } } */
+/* { dg-final { scan-assembler "cset.*, mi" } } */
+/* { dg-final { scan-assembler "cset.*, pl" } } */
+/* { dg-final { scan-assembler "cset.*, vs" } } */
+/* { dg-final { scan-assembler "cset.*, vc" } } */
+/* { dg-final { scan-assembler "cset.*, hi" } } */
+/* { dg-final { scan-assembler "cset.*, ls" } } */
+/* { dg-final { scan-assembler "cset.*, ge" } } */
+/* { dg-final { scan-assembler "cset.*, ls" } } */
+/* { dg-final { scan-assembler "cset.*, gt" } } */
+/* { dg-final { scan-assembler "cset.*, le" } } */
diff --git a/gcc/testsuite/gcc.target/aarch64/asm-flag-3.c b/gcc/testsuite/gcc.target/aarch64/asm-flag-3.c
new file mode 100644
index 00000000000..8b0bd8a00f9
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/asm-flag-3.c
@@ -0,0 +1,36 @@
+/* Test some of the valid @cc<cc> asm flag outputs. */
+/* { dg-do compile } */
+/* { dg-options "-O" } */
+
+#define DO(C) \
+void f##C(void) { char x; asm("" : "=@cc"#C(x)); if (!x) asm(""); asm(""); }
+
+DO(ne)
+DO(eq)
+DO(cs)
+DO(cc)
+DO(mi)
+DO(pl)
+DO(vs)
+DO(vc)
+DO(hi)
+DO(ls)
+DO(ge)
+DO(lt)
+DO(gt)
+DO(le)
+
+/* { dg-final { scan-assembler "bne" } } */
+/* { dg-final { scan-assembler "beq" } } */
+/* { dg-final { scan-assembler "bcs" } } */
+/* { dg-final { scan-assembler "bcc" } } */
+/* { dg-final { scan-assembler "bmi" } } */
+/* { dg-final { scan-assembler "bpl" } } */
+/* { dg-final { scan-assembler "bvs" } } */
+/* { dg-final { scan-assembler "bvc" } } */
+/* { dg-final { scan-assembler "bhi" } } */
+/* { dg-final { scan-assembler "bls" } } */
+/* { dg-final { scan-assembler "bge" } } */
+/* { dg-final { scan-assembler "blt" } } */
+/* { dg-final { scan-assembler "bgt" } } */
+/* { dg-final { scan-assembler "ble" } } */
diff --git a/gcc/testsuite/gcc.target/aarch64/asm-flag-5.c b/gcc/testsuite/gcc.target/aarch64/asm-flag-5.c
new file mode 100644
index 00000000000..4d4394e1478
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/asm-flag-5.c
@@ -0,0 +1,30 @@
+/* Test error conditions of asm flag outputs. */
+/* { dg-do compile } */
+/* { dg-options "" } */
+
+void f_B(void) { _Bool x; asm("" : "=@cccc"(x)); }
+void f_c(void) { char x; asm("" : "=@cccc"(x)); }
+void f_s(void) { short x; asm("" : "=@cccc"(x)); }
+void f_i(void) { int x; asm("" : "=@cccc"(x)); }
+void f_l(void) { long x; asm("" : "=@cccc"(x)); }
+void f_ll(void) { long long x; asm("" : "=@cccc"(x)); }
+
+void f_f(void)
+{
+ float x;
+ asm("" : "=@cccc"(x)); /* { dg-error invalid type } */
+}
+
+void f_d(void)
+{
+ double x;
+ asm("" : "=@cccc"(x)); /* { dg-error invalid type } */
+}
+
+struct S { int x[3]; };
+
+void f_S(void)
+{
+ struct S x;
+ asm("" : "=@cccc"(x)); /* { dg-error invalid type } */
+}
diff --git a/gcc/testsuite/gcc.target/aarch64/asm-flag-6.c b/gcc/testsuite/gcc.target/aarch64/asm-flag-6.c
new file mode 100644
index 00000000000..d9b90b8e517
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/asm-flag-6.c
@@ -0,0 +1,43 @@
+/* Executable testcase for 'output flags.' */
+/* { dg-do run } */
+
+int test_bits (long nzcv)
+{
+ long n, z, c, v;
+
+ __asm__ ("msr nzcv, %[in]"
+ : "=@ccmi"(n), "=@cceq"(z), "=@cccs"(c), "=@ccvs"(v)
+ : [in] "r"(nzcv << 28));
+
+ return n * 8 + z * 4 + c * 2 + v == nzcv;
+}
+
+int test_cmp (long x, long y)
+{
+ long gt, lt, ge, le;
+
+ __asm__ ("cmp %[x], %[y]"
+ : "=@ccgt"(gt), "=@cclt"(lt), "=@ccge"(ge), "=@ccle"(le)
+ : [x] "r"(x), [y] "r"(y));
+
+ return (gt == (x > y)
+ && lt == (x < y)
+ && ge == (x >= y)
+ && le == (x <= y));
+}
+
+int main ()
+{
+ long i, j;
+
+ for (i = 0; i < 16; ++i)
+ if (!test_bits (i))
+ __builtin_abort ();
+
+ for (i = -1; i <= 1; ++i)
+ for (j = -1; j <= 1; ++j)
+ if (!test_cmp (i, j))
+ __builtin_abort ();
+
+ return 0;
+}
--
2.17.1
^ permalink raw reply [flat|nested] 11+ messages in thread
* [PATCH 2/6] arm: Fix the "c" constraint
2019-11-08 10:54 [PATCH 0/6] Implement asm flag outputs for arm + aarch64 Richard Henderson
` (2 preceding siblings ...)
2019-11-08 10:54 ` [PATCH 5/6] arm: Add testsuite checks for asm-flag Richard Henderson
@ 2019-11-08 10:54 ` Richard Henderson
2019-11-08 10:54 ` [PATCH 6/6] aarch64: Add testsuite checks for asm-flag Richard Henderson
` (2 subsequent siblings)
6 siblings, 0 replies; 11+ messages in thread
From: Richard Henderson @ 2019-11-08 10:54 UTC (permalink / raw)
To: gcc-patches
Cc: richard.earnshaw, james.greenhalgh, richard.sandiford,
marcus.shawcroft, kyrylo.tkachov
The existing definition using register class CC_REG does not
work because CC_REGNUM does not support normal modes, and so
fails to match register_operand. Use a non-register constraint
and the cc_register predicate instead.
* config/arm/constraints.md (c): Use cc_register predicate.
---
gcc/config/arm/constraints.md | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/gcc/config/arm/constraints.md b/gcc/config/arm/constraints.md
index b76de81b85c..e02b678d26d 100644
--- a/gcc/config/arm/constraints.md
+++ b/gcc/config/arm/constraints.md
@@ -94,8 +94,9 @@
"@internal
Thumb only. The union of the low registers and the stack register.")
-(define_register_constraint "c" "CC_REG"
- "@internal The condition code register.")
+(define_constraint "c"
+ "@internal The condition code register."
+ (match_operand 0 "cc_register"))
(define_register_constraint "Cs" "CALLER_SAVE_REGS"
"@internal The caller save registers. Useful for sibcalls.")
--
2.17.1
^ permalink raw reply [flat|nested] 11+ messages in thread
* [PATCH 0/6] Implement asm flag outputs for arm + aarch64
@ 2019-11-08 10:54 Richard Henderson
2019-11-08 10:54 ` [PATCH 3/6] arm: Rename CC_NOOVmode to CC_NZmode Richard Henderson
` (6 more replies)
0 siblings, 7 replies; 11+ messages in thread
From: Richard Henderson @ 2019-11-08 10:54 UTC (permalink / raw)
To: gcc-patches
Cc: richard.earnshaw, james.greenhalgh, richard.sandiford,
marcus.shawcroft, kyrylo.tkachov
I've put the implementation into config/arm/aarch-common.c, so
that it can be shared between the two targets. This required
a little bit of cleanup to the CC modes and constraints to get
the two targets to match up.
I really should have done more than just x86 years ago, so that
it would be done now and I could just use it in the kernel... ;-)
r~
Richard Henderson (6):
aarch64: Add "c" constraint
arm: Fix the "c" constraint
arm: Rename CC_NOOVmode to CC_NZmode
arm, aarch64: Add support for __GCC_ASM_FLAG_OUTPUTS__
arm: Add testsuite checks for asm-flag
aarch64: Add testsuite checks for asm-flag
gcc/config/arm/aarch-common-protos.h | 6 +
gcc/config/aarch64/aarch64-c.c | 2 +
gcc/config/aarch64/aarch64.c | 3 +
gcc/config/arm/aarch-common.c | 131 ++++++++++++
gcc/config/arm/arm-c.c | 1 +
gcc/config/arm/arm.c | 15 +-
gcc/testsuite/gcc.target/aarch64/asm-flag-1.c | 34 ++++
gcc/testsuite/gcc.target/aarch64/asm-flag-3.c | 36 ++++
gcc/testsuite/gcc.target/aarch64/asm-flag-5.c | 30 +++
gcc/testsuite/gcc.target/aarch64/asm-flag-6.c | 43 ++++
gcc/testsuite/gcc.target/arm/asm-flag-1.c | 35 ++++
gcc/testsuite/gcc.target/arm/asm-flag-3.c | 36 ++++
gcc/testsuite/gcc.target/arm/asm-flag-5.c | 30 +++
gcc/testsuite/gcc.target/arm/asm-flag-6.c | 43 ++++
gcc/config/aarch64/constraints.md | 4 +
gcc/config/arm/arm-modes.def | 4 +-
gcc/config/arm/arm.md | 186 +++++++++---------
gcc/config/arm/constraints.md | 5 +-
gcc/config/arm/predicates.md | 2 +-
gcc/config/arm/thumb1.md | 8 +-
gcc/config/arm/thumb2.md | 34 ++--
gcc/doc/extend.texi | 33 ++++
22 files changed, 596 insertions(+), 125 deletions(-)
create mode 100644 gcc/testsuite/gcc.target/aarch64/asm-flag-1.c
create mode 100644 gcc/testsuite/gcc.target/aarch64/asm-flag-3.c
create mode 100644 gcc/testsuite/gcc.target/aarch64/asm-flag-5.c
create mode 100644 gcc/testsuite/gcc.target/aarch64/asm-flag-6.c
create mode 100644 gcc/testsuite/gcc.target/arm/asm-flag-1.c
create mode 100644 gcc/testsuite/gcc.target/arm/asm-flag-3.c
create mode 100644 gcc/testsuite/gcc.target/arm/asm-flag-5.c
create mode 100644 gcc/testsuite/gcc.target/arm/asm-flag-6.c
--
2.17.1
^ permalink raw reply [flat|nested] 11+ messages in thread
* [PATCH 4/6] arm, aarch64: Add support for __GCC_ASM_FLAG_OUTPUTS__
2019-11-08 10:54 [PATCH 0/6] Implement asm flag outputs for arm + aarch64 Richard Henderson
2019-11-08 10:54 ` [PATCH 3/6] arm: Rename CC_NOOVmode to CC_NZmode Richard Henderson
@ 2019-11-08 10:54 ` Richard Henderson
2019-11-08 10:59 ` Richard Henderson
2019-11-08 10:54 ` [PATCH 5/6] arm: Add testsuite checks for asm-flag Richard Henderson
` (4 subsequent siblings)
6 siblings, 1 reply; 11+ messages in thread
From: Richard Henderson @ 2019-11-08 10:54 UTC (permalink / raw)
To: gcc-patches
Cc: richard.earnshaw, james.greenhalgh, richard.sandiford,
marcus.shawcroft, kyrylo.tkachov
Since all but a couple of lines is shared between the two targets,
enable them both at once.
* config/arm/aarch-common-protos.h (arm_md_asm_adjust): Declare.
* config/arm/aarch-common.c (arm_md_asm_adjust): New.
* config/arm/arm-c.c (arm_cpu_builtins): Define
__GCC_ASM_FLAG_OUTPUTS__.
* config/arm/arm.c (TARGET_MD_ASM_ADJUST): New.
* config/aarch64/aarch64-c.c (aarch64_define_unconditional_macros):
Define __GCC_ASM_FLAG_OUTPUTS__.
* config/aarch64/aarch64.c (TARGET_MD_ASM_ADJUST): New.
* doc/extend.texi (FlagOutputOperands): Add documentation
for ARM and AArch64.
---
gcc/config/arm/aarch-common-protos.h | 6 ++
gcc/config/aarch64/aarch64-c.c | 2 +
gcc/config/aarch64/aarch64.c | 3 +
gcc/config/arm/aarch-common.c | 131 +++++++++++++++++++++++++++
gcc/config/arm/arm-c.c | 1 +
gcc/config/arm/arm.c | 3 +
gcc/doc/extend.texi | 33 +++++++
7 files changed, 179 insertions(+)
diff --git a/gcc/config/arm/aarch-common-protos.h b/gcc/config/arm/aarch-common-protos.h
index 3bf38a104f6..f15cf336e9d 100644
--- a/gcc/config/arm/aarch-common-protos.h
+++ b/gcc/config/arm/aarch-common-protos.h
@@ -23,6 +23,8 @@
#ifndef GCC_AARCH_COMMON_PROTOS_H
#define GCC_AARCH_COMMON_PROTOS_H
+#include "hard-reg-set.h"
+
extern int aarch_accumulator_forwarding (rtx_insn *, rtx_insn *);
extern bool aarch_rev16_p (rtx);
extern bool aarch_rev16_shleft_mask_imm_p (rtx, machine_mode);
@@ -141,5 +143,9 @@ struct cpu_cost_table
const struct vector_cost_table vect;
};
+rtx_insn *
+arm_md_asm_adjust (vec<rtx> &outputs, vec<rtx> &/*inputs*/,
+ vec<const char *> &constraints,
+ vec<rtx> &clobbers, HARD_REG_SET &clobbered_regs);
#endif /* GCC_AARCH_COMMON_PROTOS_H */
diff --git a/gcc/config/aarch64/aarch64-c.c b/gcc/config/aarch64/aarch64-c.c
index 7c322ca0813..0af859f1c14 100644
--- a/gcc/config/aarch64/aarch64-c.c
+++ b/gcc/config/aarch64/aarch64-c.c
@@ -69,6 +69,8 @@ aarch64_define_unconditional_macros (cpp_reader *pfile)
builtin_define ("__ARM_FEATURE_UNALIGNED");
builtin_define ("__ARM_PCS_AAPCS64");
builtin_define_with_int_value ("__ARM_SIZEOF_WCHAR_T", WCHAR_TYPE_SIZE / 8);
+
+ builtin_define ("__GCC_ASM_FLAG_OUTPUTS__");
}
/* Undefine/redefine macros that depend on the current backend state and may
diff --git a/gcc/config/aarch64/aarch64.c b/gcc/config/aarch64/aarch64.c
index 1dfff331a5a..26de9879bc7 100644
--- a/gcc/config/aarch64/aarch64.c
+++ b/gcc/config/aarch64/aarch64.c
@@ -21947,6 +21947,9 @@ aarch64_libgcc_floating_mode_supported_p
#undef TARGET_STRICT_ARGUMENT_NAMING
#define TARGET_STRICT_ARGUMENT_NAMING hook_bool_CUMULATIVE_ARGS_true
+#undef TARGET_MD_ASM_ADJUST
+#define TARGET_MD_ASM_ADJUST arm_md_asm_adjust
+
struct gcc_target targetm = TARGET_INITIALIZER;
#include "gt-aarch64.h"
diff --git a/gcc/config/arm/aarch-common.c b/gcc/config/arm/aarch-common.c
index 965a07a43e3..8b98c8d3802 100644
--- a/gcc/config/arm/aarch-common.c
+++ b/gcc/config/arm/aarch-common.c
@@ -26,10 +26,16 @@
#include "config.h"
#include "system.h"
#include "coretypes.h"
+#include "insn-modes.h"
#include "tm.h"
#include "rtl.h"
#include "rtl-iter.h"
#include "memmodel.h"
+#include "errors.h"
+#include "tree.h"
+#include "expr.h"
+#include "function.h"
+#include "emit-rtl.h"
/* Return TRUE if X is either an arithmetic shift left, or
is a multiplication by a power of two. */
@@ -520,3 +526,128 @@ arm_mac_accumulator_is_mul_result (rtx producer, rtx consumer)
&& !reg_overlap_mentioned_p (mul_result, mac_op0)
&& !reg_overlap_mentioned_p (mul_result, mac_op1));
}
+
+/* Worker function for TARGET_MD_ASM_ADJUST.
+ We implement asm flag outputs. */
+
+rtx_insn *
+arm_md_asm_adjust (vec<rtx> &outputs, vec<rtx> &/*inputs*/,
+ vec<const char *> &constraints,
+ vec<rtx> &/*clobbers*/, HARD_REG_SET &/*clobbered_regs*/)
+{
+ bool saw_asm_flag = false;
+
+ start_sequence ();
+ for (unsigned i = 0, n = outputs.length (); i < n; ++i)
+ {
+ const char *con = constraints[i];
+ if (strncmp (con, "=@cc", 4) != 0)
+ continue;
+ con += 4;
+ if (strchr (con, ',') != NULL)
+ {
+ error ("alternatives not allowed in %<asm%> flag output");
+ continue;
+ }
+
+ machine_mode mode = CCmode;
+ rtx_code code = UNKNOWN;
+
+ switch (con[0])
+ {
+ case 'c':
+ if (con[1] == 'c' && con[2] == 0)
+ mode = CC_Cmode, code = GEU;
+ else if (con[1] == 's' && con[2] == 0)
+ mode = CC_Cmode, code = LTU;
+ break;
+ case 'e':
+ if (con[1] == 'q' && con[2] == 0)
+ mode = CC_NZmode, code = EQ;
+ break;
+ case 'g':
+ if (con[1] == 'e' && con[2] == 0)
+ mode = CCmode, code = GE;
+ else if (con[1] == 't' && con[2] == 0)
+ mode = CCmode, code = GT;
+ break;
+ case 'h':
+ if (con[1] == 'i' && con[2] == 0)
+ mode = CCmode, code = GTU;
+ break;
+ case 'l':
+ if (con[1] == 'e' && con[2] == 0)
+ mode = CCmode, code = LE;
+ else if (con[1] == 't' && con[2] == 0)
+ mode = CCmode, code = LT;
+ else if (con[1] == 's' && con[2] == 0)
+ mode = CCmode, code = LEU;
+ break;
+ case 'm':
+ if (con[1] == 'i' && con[2] == 0)
+ mode = CC_NZmode, code = LT;
+ break;
+ case 'n':
+ if (con[1] == 'e' && con[2] == 0)
+ mode = CC_NZmode, code = NE;
+ break;
+ case 'p':
+ if (con[1] == 'l' && con[2] == 0)
+ mode = CC_NZmode, code = GE;
+ break;
+ case 'v':
+ if (con[1] == 'c' && con[2] == 0)
+ mode = CC_Vmode, code = EQ;
+ else if (con[1] == 's' && con[2] == 0)
+ mode = CC_Vmode, code = NE;
+ break;
+ }
+ if (code == UNKNOWN)
+ {
+ error ("unknown %<asm%> flag output %qs", constraints[i]);
+ continue;
+ }
+
+ rtx dest = outputs[i];
+ machine_mode dest_mode = GET_MODE (dest);
+ if (!SCALAR_INT_MODE_P (dest_mode))
+ {
+ error ("invalid type for %<asm%> flag output");
+ continue;
+ }
+
+ if (!saw_asm_flag)
+ {
+ /* This is the first asm flag output. Here we put the flags
+ register in as the real output and adjust the condition to
+ allow it. */
+ constraints[i] = "=c";
+ outputs[i] = gen_rtx_REG (CCmode, CC_REGNUM);
+ saw_asm_flag = true;
+ }
+ else
+ {
+ /* We don't need the flags register as output twice. */
+ constraints[i] = "=X";
+ outputs[i] = gen_rtx_SCRATCH (word_mode);
+ }
+
+ rtx x = gen_rtx_REG (mode, CC_REGNUM);
+ x = gen_rtx_fmt_ee (code, word_mode, x, const0_rtx);
+
+ if (dest_mode == word_mode)
+ emit_insn (gen_rtx_SET (dest, x));
+ else
+ {
+ rtx tmp = gen_reg_rtx (word_mode);
+ emit_insn (gen_rtx_SET (tmp, x));
+
+ tmp = convert_modes (dest_mode, word_mode, tmp, true);
+ emit_move_insn (dest, tmp);
+ }
+ }
+ rtx_insn *seq = get_insns ();
+ end_sequence ();
+
+ return saw_asm_flag ? seq : NULL;
+}
diff --git a/gcc/config/arm/arm-c.c b/gcc/config/arm/arm-c.c
index 34695fa0112..c4485ce7af1 100644
--- a/gcc/config/arm/arm-c.c
+++ b/gcc/config/arm/arm-c.c
@@ -122,6 +122,7 @@ arm_cpu_builtins (struct cpp_reader* pfile)
if (arm_arch_notm)
builtin_define ("__ARM_ARCH_ISA_ARM");
builtin_define ("__APCS_32__");
+ builtin_define ("__GCC_ASM_FLAG_OUTPUTS__");
def_or_undef_macro (pfile, "__thumb__", TARGET_THUMB);
def_or_undef_macro (pfile, "__thumb2__", TARGET_THUMB2);
diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c
index b620322318b..d889e8ddc60 100644
--- a/gcc/config/arm/arm.c
+++ b/gcc/config/arm/arm.c
@@ -814,6 +814,9 @@ static const struct attribute_spec arm_attribute_table[] =
#undef TARGET_CONSTANT_ALIGNMENT
#define TARGET_CONSTANT_ALIGNMENT arm_constant_alignment
+
+#undef TARGET_MD_ASM_ADJUST
+#define TARGET_MD_ASM_ADJUST arm_md_asm_adjust
\f
/* Obstack for minipool constant handling. */
static struct obstack minipool_obstack;
diff --git a/gcc/doc/extend.texi b/gcc/doc/extend.texi
index 9db4f9b1d29..a26b8b976fa 100644
--- a/gcc/doc/extend.texi
+++ b/gcc/doc/extend.texi
@@ -9771,6 +9771,39 @@ referenced within the assembler template via @code{%0} etc, as there's
no corresponding text in the assembly language.
@table @asis
+@item ARM
+@itemx AArch64
+The flag output constraints for the ARM family are of the form
+@samp{=@@cc@var{cond}} where @var{cond} is one of the standard
+conditions defined in the ARM ARM for @code{ConditionHolds}.
+
+@table @code
+@item eq
+``equal'' or Z flag set
+@item ne
+``not equal'' or Z flag clear
+@item cs
+``carry'' or C flag set
+@item cc
+C flag clear
+@item mi
+``minus'' or N flag set
+@item pl
+``plus'' or N flag clear
+@item hi
+unsigned greater than
+@item ls
+unsigned less than or equal
+@item ge
+signed greater than or equal
+@item lt
+signed less than
+@item gt
+signed greater than
+@item le
+signed less than or equal
+@end table
+
@item x86 family
The flag output constraints for the x86 family are of the form
@samp{=@@cc@var{cond}} where @var{cond} is one of the standard
--
2.17.1
^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH 4/6] arm, aarch64: Add support for __GCC_ASM_FLAG_OUTPUTS__
2019-11-08 10:54 ` [PATCH 4/6] arm, aarch64: Add support for __GCC_ASM_FLAG_OUTPUTS__ Richard Henderson
@ 2019-11-08 10:59 ` Richard Henderson
0 siblings, 0 replies; 11+ messages in thread
From: Richard Henderson @ 2019-11-08 10:59 UTC (permalink / raw)
To: Richard Henderson, gcc-patches
Cc: richard.earnshaw, james.greenhalgh, richard.sandiford,
marcus.shawcroft, kyrylo.tkachov
On 11/8/19 11:54 AM, Richard Henderson wrote:
> +@table @code
> +@item eq
> +``equal'' or Z flag set
> +@item ne
> +``not equal'' or Z flag clear
> +@item cs
> +``carry'' or C flag set
> +@item cc
> +C flag clear
> +@item mi
> +``minus'' or N flag set
> +@item pl
> +``plus'' or N flag clear
> +@item hi
> +unsigned greater than
Dang, skipped right over vc/vs here. Will fix.
r~
^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH 0/6] Implement asm flag outputs for arm + aarch64
2019-11-08 10:54 [PATCH 0/6] Implement asm flag outputs for arm + aarch64 Richard Henderson
` (5 preceding siblings ...)
2019-11-08 10:54 ` [PATCH 1/6] aarch64: Add "c" constraint Richard Henderson
@ 2019-11-12 20:23 ` Richard Sandiford
2019-11-13 8:09 ` Richard Henderson
6 siblings, 1 reply; 11+ messages in thread
From: Richard Sandiford @ 2019-11-12 20:23 UTC (permalink / raw)
To: Richard Henderson
Cc: gcc-patches, richard.earnshaw, james.greenhalgh,
marcus.shawcroft, kyrylo.tkachov
Richard Henderson <richard.henderson@linaro.org> writes:
> I've put the implementation into config/arm/aarch-common.c, so
> that it can be shared between the two targets. This required
> a little bit of cleanup to the CC modes and constraints to get
> the two targets to match up.
>
> I really should have done more than just x86 years ago, so that
> it would be done now and I could just use it in the kernel... ;-)
Thanks for doing this, looks great.
Apart from the vc/vs thing you mentioned in the follow-up for 4/6,
it looks like 4/6, 5/6 and 6/6 are missing "hs" and "lo". OK for
aarch64 with those added.
Richard
^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH 0/6] Implement asm flag outputs for arm + aarch64
2019-11-12 20:23 ` [PATCH 0/6] Implement asm flag outputs for arm + aarch64 Richard Sandiford
@ 2019-11-13 8:09 ` Richard Henderson
2019-11-13 8:39 ` Richard Sandiford
0 siblings, 1 reply; 11+ messages in thread
From: Richard Henderson @ 2019-11-13 8:09 UTC (permalink / raw)
To: gcc-patches, richard.earnshaw, james.greenhalgh,
marcus.shawcroft, kyrylo.tkachov, richard.sandiford
On 11/12/19 9:21 PM, Richard Sandiford wrote:
> Apart from the vc/vs thing you mentioned in the follow-up for 4/6,
> it looks like 4/6, 5/6 and 6/6 are missing "hs" and "lo". OK for
> aarch64 with those added.
Are those aliases for two of the other conditions? They're not in the list
within the pseudocode for ConditionHolds in the ARM ARM. Which is what I was
documenting to support...
r~
^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH 0/6] Implement asm flag outputs for arm + aarch64
2019-11-13 8:09 ` Richard Henderson
@ 2019-11-13 8:39 ` Richard Sandiford
0 siblings, 0 replies; 11+ messages in thread
From: Richard Sandiford @ 2019-11-13 8:39 UTC (permalink / raw)
To: Richard Henderson
Cc: gcc-patches, richard.earnshaw, james.greenhalgh,
marcus.shawcroft, kyrylo.tkachov
Richard Henderson <richard.henderson@linaro.org> writes:
> On 11/12/19 9:21 PM, Richard Sandiford wrote:
>> Apart from the vc/vs thing you mentioned in the follow-up for 4/6,
>> it looks like 4/6, 5/6 and 6/6 are missing "hs" and "lo". OK for
>> aarch64 with those added.
>
> Are those aliases for two of the other conditions? They're not in the list
> within the pseudocode for ConditionHolds in the ARM ARM. Which is what I was
> documenting to support...
Yeah, hs==cs and lo==cc. But I think they're commonly used, and are the
natural choice if you're testing the result of an unsigned comparison.
Richard
^ permalink raw reply [flat|nested] 11+ messages in thread
end of thread, other threads:[~2019-11-13 8:32 UTC | newest]
Thread overview: 11+ messages (download: mbox.gz / follow: Atom feed)
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2019-11-08 10:54 [PATCH 0/6] Implement asm flag outputs for arm + aarch64 Richard Henderson
2019-11-08 10:54 ` [PATCH 3/6] arm: Rename CC_NOOVmode to CC_NZmode Richard Henderson
2019-11-08 10:54 ` [PATCH 4/6] arm, aarch64: Add support for __GCC_ASM_FLAG_OUTPUTS__ Richard Henderson
2019-11-08 10:59 ` Richard Henderson
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2019-11-08 10:54 ` [PATCH 2/6] arm: Fix the "c" constraint Richard Henderson
2019-11-08 10:54 ` [PATCH 6/6] aarch64: Add testsuite checks for asm-flag Richard Henderson
2019-11-08 10:54 ` [PATCH 1/6] aarch64: Add "c" constraint Richard Henderson
2019-11-12 20:23 ` [PATCH 0/6] Implement asm flag outputs for arm + aarch64 Richard Sandiford
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