From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 64497 invoked by alias); 3 Jun 2019 10:55:52 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Received: (qmail 64488 invoked by uid 89); 3 Jun 2019 10:55:52 -0000 Authentication-Results: sourceware.org; auth=none X-Spam-SWARE-Status: No, score=-15.1 required=5.0 tests=AWL,BAYES_00,GIT_PATCH_0,GIT_PATCH_1,GIT_PATCH_2,GIT_PATCH_3,SPF_PASS autolearn=ham version=3.3.1 spammy= X-HELO: foss.arm.com Received: from usa-sjc-mx-foss1.foss.arm.com (HELO foss.arm.com) (217.140.101.70) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Mon, 03 Jun 2019 10:55:50 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 1CBF0A78; Mon, 3 Jun 2019 03:55:49 -0700 (PDT) Received: from localhost (e121540-lin.manchester.arm.com [10.32.98.39]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 68C6B3F5AF; Mon, 3 Jun 2019 03:55:48 -0700 (PDT) From: Richard Sandiford To: Prathamesh Kulkarni Mail-Followup-To: Prathamesh Kulkarni ,gcc Patches , richard.sandiford@arm.com Cc: gcc Patches Subject: Re: [AArch64] [SVE] PR88837 - Poor vector construction code in VL-specific mode References: Date: Mon, 03 Jun 2019 10:55:00 -0000 In-Reply-To: (Prathamesh Kulkarni's message of "Mon, 3 Jun 2019 15:21:25 +0530") Message-ID: User-Agent: Gnus/5.13 (Gnus v5.13) Emacs/26.1 (gnu/linux) MIME-Version: 1.0 Content-Type: text/plain X-SW-Source: 2019-06/txt/msg00062.txt.bz2 Prathamesh Kulkarni writes: >> > diff --git a/gcc/testsuite/lib/target-supports.exp b/gcc/testsuite/lib/target-supports.exp >> > index 3bd6e815715..0ff0d8fb757 100644 >> > --- a/gcc/testsuite/lib/target-supports.exp >> > +++ b/gcc/testsuite/lib/target-supports.exp >> > @@ -3846,6 +3846,10 @@ proc add_options_for_arm_neon_softfp_fp16 { flags } { >> > return "$flags $et_arm_neon_softfp_fp16_flags" >> > } >> > >> > +proc add_options_for_arm_sve { flags } { >> > + return "$flags -march=armv8.2-a+sve" >> >> ...this I think we should avoid overriding the flags if they already >> select SVE, so probably: >> >> if { ![istarget aarch64*-*-*] || [check_effective_target_aarch64_sve] } { >> return "$flags" >> } >> >> Should be "aarch64_sve" rather than "arm_sve". >> >> > +} >> > + >> > # Return 1 if this is an ARM target supporting the FP16 alternative >> > # format. Some multilibs may be incompatible with the options needed. Also >> > # set et_arm_neon_fp16_flags to the best options to add. >> > @@ -4323,7 +4327,7 @@ proc check_effective_target_aarch64_sve_hw { } { >> > asm volatile ("ptrue p0.b"); >> > return 0; >> > } >> > - }] >> > + } [ add_options_for_arm_sve "" ]] >> > } >> > >> > # Return true if this is an AArch64 target that can run SVE code and >> > @@ -4343,7 +4347,7 @@ proc aarch64_sve_hw_bits { bits } { >> > __builtin_abort (); >> > return 0; >> > } >> > - }]] >> > + }] [add_options_for_arm_sve ""] ] >> > } >> > >> > # Return true if this is an AArch64 target that can run SVE code and >> >> Think the formatting in the second is preferred over the first (i.e. >> no spaces inside the [...]). > Does the attached patch look OK ? Yes, thanks. (With a suitable changelog of course :-)) Richard > > Thanks, > Prathamesh >> >> Thanks, >> Richard > > diff --git a/gcc/testsuite/lib/target-supports.exp b/gcc/testsuite/lib/target-supports.exp > index 3bd6e815715..2b3e5d26004 100644 > --- a/gcc/testsuite/lib/target-supports.exp > +++ b/gcc/testsuite/lib/target-supports.exp > @@ -3846,6 +3846,13 @@ proc add_options_for_arm_neon_softfp_fp16 { flags } { > return "$flags $et_arm_neon_softfp_fp16_flags" > } > > +proc add_options_for_aarch64_sve { flags } { > + if { ![istarget aarch64*-*-*] || [check_effective_target_aarch64_sve] } { > + return "$flags" > + } > + return "$flags -march=armv8.2-a+sve" > +} > + > # Return 1 if this is an ARM target supporting the FP16 alternative > # format. Some multilibs may be incompatible with the options needed. Also > # set et_arm_neon_fp16_flags to the best options to add. > @@ -4323,7 +4330,7 @@ proc check_effective_target_aarch64_sve_hw { } { > asm volatile ("ptrue p0.b"); > return 0; > } > - }] > + } [add_options_for_aarch64_sve ""]] > } > > # Return true if this is an AArch64 target that can run SVE code and > @@ -4343,7 +4350,7 @@ proc aarch64_sve_hw_bits { bits } { > __builtin_abort (); > return 0; > } > - }]] > + }] [add_options_for_aarch64_sve ""]] > } > > # Return true if this is an AArch64 target that can run SVE code and