From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by sourceware.org (Postfix) with ESMTP id 07B743858416 for ; Fri, 22 Oct 2021 15:13:04 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 07B743858416 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id A5D0F1FB; Fri, 22 Oct 2021 08:13:03 -0700 (PDT) Received: from localhost (unknown [10.32.98.88]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 134303F694; Fri, 22 Oct 2021 08:13:02 -0700 (PDT) From: Richard Sandiford To: Jonathan Wright Mail-Followup-To: Jonathan Wright , "gcc-patches\@gcc.gnu.org" , Kyrylo Tkachov , richard.sandiford@arm.com Cc: "gcc-patches\@gcc.gnu.org" , Kyrylo Tkachov Subject: Re: [PATCH 4/6] aarch64: Add machine modes for Neon vector-tuple types References: Date: Fri, 22 Oct 2021 16:13:01 +0100 In-Reply-To: (Jonathan Wright's message of "Fri, 22 Oct 2021 15:48:27 +0100") Message-ID: User-Agent: Gnus/5.13 (Gnus v5.13) Emacs/26.3 (gnu/linux) MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable X-Spam-Status: No, score=-12.4 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_DMARC_STATUS, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.4 X-Spam-Checker-Version: SpamAssassin 3.4.4 (2020-01-24) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 22 Oct 2021 15:13:05 -0000 Thanks a lot for doing this. Jonathan Wright writes: > @@ -763,9 +839,16 @@ aarch64_lookup_simd_builtin_type (machine_mode mode, > return aarch64_simd_builtin_std_type (mode, q); >=20=20 > for (i =3D 0; i < nelts; i++) > - if (aarch64_simd_types[i].mode =3D=3D mode > - && aarch64_simd_types[i].q =3D=3D q) > - return aarch64_simd_types[i].itype; > + { > + if (aarch64_simd_types[i].mode =3D=3D mode > + && aarch64_simd_types[i].q =3D=3D q) > + return aarch64_simd_types[i].itype; > + else if (aarch64_simd_tuple_types[i][0] !=3D NULL_TREE) Very minor (sorry for not noticing earlier), but: the =E2=80=9Celse=E2=80= =9D is redundant here. > + for (int j =3D 0; j < 3; j++) > + if (TYPE_MODE (aarch64_simd_tuple_types[i][j]) =3D=3D mode > + && aarch64_simd_types[i].q =3D=3D q) > + return aarch64_simd_tuple_types[i][j]; > + } >=20=20 > return NULL_TREE; > } > diff --git a/gcc/config/aarch64/aarch64-simd.md b/gcc/config/aarch64/aarc= h64-simd.md > index 48eddf64e05afe3788abfa05141f6544a9323ea1..0aa185b67ff13d40c87db0449= aec312929ff5387 100644 > --- a/gcc/config/aarch64/aarch64-simd.md > +++ b/gcc/config/aarch64/aarch64-simd.md > @@ -6636,162 +6636,165 @@ >=20=20 > ;; Patterns for vector struct loads and stores. >=20=20 > -(define_insn "aarch64_simd_ld2" > - [(set (match_operand:OI 0 "register_operand" "=3Dw") > - (unspec:OI [(match_operand:OI 1 "aarch64_simd_struct_operand" "Utv") > - (unspec:VQ [(const_int 0)] UNSPEC_VSTRUCTDUMMY)] > - UNSPEC_LD2))] > +(define_insn "aarch64_simd_ld2" > + [(set (match_operand:VSTRUCT_2Q 0 "register_operand" "=3Dw") > + (unspec:VSTRUCT_2Q [ > + (match_operand:VSTRUCT_2Q 1 "aarch64_simd_struct_operand" "Utv")] > + UNSPEC_LD2))] > "TARGET_SIMD" > "ld2\\t{%S0. - %T0.}, %1" > [(set_attr "type" "neon_load2_2reg")] > ) >=20=20 > -(define_insn "aarch64_simd_ld2r" > - [(set (match_operand:OI 0 "register_operand" "=3Dw") > - (unspec:OI [(match_operand:BLK 1 "aarch64_simd_struct_operand" "U= tv") > - (unspec:VALLDIF [(const_int 0)] UNSPEC_VSTRUCTDUMMY) ] > - UNSPEC_LD2_DUP))] > +(define_insn "aarch64_simd_ld2r" > + [(set (match_operand:VSTRUCT_2QD 0 "register_operand" "=3Dw") > + (unspec:VSTRUCT_2QD [ > + (match_operand:VSTRUCT_2QD 1 "aarch64_simd_struct_operand" "Utv")] > + UNSPEC_LD2_DUP))] Sorry again for missing this, but the ld2rs, ld3rs and ld4rs should keep their BLKmode arguments, since they only access 2, 3 or 4 scalar memory elements. > @@ -7515,10 +7605,10 @@ > ) >=20=20 > (define_insn_and_split "aarch64_combinev16qi" > - [(set (match_operand:OI 0 "register_operand" "=3Dw") > - (unspec:OI [(match_operand:V16QI 1 "register_operand" "w") > - (match_operand:V16QI 2 "register_operand" "w")] > - UNSPEC_CONCAT))] > + [(set (match_operand:V2x16QI 0 "register_operand" "=3Dw") > + (unspec:V2x16QI [(match_operand:V16QI 1 "register_operand" "w") > + (match_operand:V16QI 2 "register_operand" "w")] > + UNSPEC_CONCAT))] Just realised that we can now make this a vec_concat, since the modes are finally self-consistent. No need to do that though, either way is fine. Looks good otherwise. Richard