From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by sourceware.org (Postfix) with ESMTP id EE4563938C3A for ; Mon, 10 May 2021 09:39:45 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.3.2 sourceware.org EE4563938C3A Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 7302C13A1; Mon, 10 May 2021 02:39:45 -0700 (PDT) Received: from localhost (e121540-lin.manchester.arm.com [10.32.98.126]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id D74983F73B; Mon, 10 May 2021 02:39:44 -0700 (PDT) From: Richard Sandiford To: Richard Biener via Gcc-patches Mail-Followup-To: Richard Biener via Gcc-patches , "H.J. Lu" , Richard Biener , richard.sandiford@arm.com Subject: Re: [PATCH 02/12] Allow generating pseudo register with specific alignment References: <20210429125415.1634118-1-hjl.tools@gmail.com> <20210429125415.1634118-3-hjl.tools@gmail.com> Date: Mon, 10 May 2021 10:39:43 +0100 In-Reply-To: (Richard Biener via Gcc-patches's message of "Mon, 3 May 2021 10:18:52 +0200") Message-ID: User-Agent: Gnus/5.13 (Gnus v5.13) Emacs/26.3 (gnu/linux) MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable X-Spam-Status: No, score=-6.6 required=5.0 tests=BAYES_00, KAM_DMARC_STATUS, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.2 X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 10 May 2021 09:39:47 -0000 Richard Biener via Gcc-patches writes: > On Fri, Apr 30, 2021 at 8:30 PM Richard Sandiford via Gcc-patches > wrote: >> >> "H.J. Lu via Gcc-patches" writes: >> > On Fri, Apr 30, 2021 at 5:49 AM H.J. Lu wrote: >> >> >> >> On Fri, Apr 30, 2021 at 5:42 AM Richard Sandiford >> >> wrote: >> >> > >> >> > "H.J. Lu via Gcc-patches" writes: >> >> > > On Fri, Apr 30, 2021 at 2:06 AM Richard Sandiford >> >> > > wrote: >> >> > >> >> >> > >> "H.J. Lu via Gcc-patches" writes: >> >> > >> > gen_reg_rtx tracks stack alignment needed for pseudo registers= so that >> >> > >> > associated hard registers can be properly spilled onto stack. = But there >> >> > >> > are cases where associated hard registers will never be spille= d onto >> >> > >> > stack. gen_reg_rtx is changed to take an argument for registe= r alignment >> >> > >> > so that stack realignment can be avoided when not needed. >> >> > >> >> >> > >> How is it guaranteed that they will never be spilled though? >> >> > >> I don't think that that guarantee exists for any kind of pseudo, >> >> > >> except perhaps for the temporary pseudos that the RA creates to >> >> > >> replace (match_scratch =E2=80=A6)es. >> >> > >> >> >> > > >> >> > > The caller of creating pseudo registers with specific alignment m= ust >> >> > > guarantee that they will never be spilled. I am only using it in >> >> > > >> >> > > /* Make operand1 a register if it isn't already. */ >> >> > > if (can_create_pseudo_p () >> >> > > && !register_operand (op0, mode) >> >> > > && !register_operand (op1, mode)) >> >> > > { >> >> > > /* NB: Don't increase stack alignment requirement when forc= ing >> >> > > operand1 into a pseudo register to copy data from one me= mory >> >> > > location to another since it doesn't require a spill. */ >> >> > > emit_move_insn (op0, >> >> > > force_reg (GET_MODE (op0), op1, >> >> > > (UNITS_PER_WORD * BITS_PER_UNIT)= )); >> >> > > return; >> >> > > } >> >> > > >> >> > > for vector moves. RA shouldn't spill it. >> >> > >> >> > But this is the point: it's a case of hoping that the RA won't spil= l it, >> >> > rather than having a guarantee that it won't. >> >> > >> >> > Even if the moves start out adjacent, they could be separated by la= ter >> >> > RTL optimisations, particularly scheduling. (I realise pre-RA sche= duling >> >> > isn't enabled by default for x86, but it can still be enabled expli= citly.) >> >> > Or if the same data is being copied to two locations, we might reuse >> >> > values loaded by the first copy for the second copy as well. >> > >> > There are cases where pseudo vector registers are created as pure >> > temporary registers in the backend and they shouldn't ever be spilled >> > to stack. They will be spilled to stack only if there are other non-= temporary >> > vector register usage in which case stack will be properly re-aligned. >> > Caller of creating pseudo registers with specific alignment guarantees >> > that they are used only as pure temporary registers. >> >> I don't think there's really a distinct category of pure temporary >> registers though. The things I mentioned above can happen for any >> kind of pseudo register. > > I wonder if for the cases HJ thinks of it is appropriate to use hardregs? > Do we generally handle those well? That is, are they again subject > to be allocated by RA when no longer live? Yeah, using hard registers should work. Of course, any given fixed choice of hard register has the potential to be suboptimal in some situation, but it should be safe. Thanks, Richard