* [arm][aarch64] Make no_insn issue to nothing
@ 2019-09-17 14:57 Richard Sandiford
2019-09-17 15:38 ` Richard Earnshaw (lists)
0 siblings, 1 reply; 3+ messages in thread
From: Richard Sandiford @ 2019-09-17 14:57 UTC (permalink / raw)
To: gcc-patches
Cc: richard.earnshaw, james.greenhalgh, marcus.shawcroft, nickc,
ramana.radhakrishnan, kyrylo.tkachov
no_insn is documented as:
an insn which does not represent an instruction in the final output,
thus having no impact on scheduling.
and is used in that way by the arm port (e.g. for define_insns that
expand to comments). However, most scheduling descriptions instead
assigned units to no_insn patterns, in some cases treating them as more
expensive than a plain move.
This patch removes the no_insn handling from individual scheduling
descriptions and uses a common define_insn_reservation for all CPUs.
Tested on aarch64-linux-gnu and armeab-none-eabi. OK to install?
Richard
2019-09-17 Richard Sandiford <richard.sandiford@arm.com>
gcc/
* config/arm/types.md (no_reservation): New reservation.
* config/aarch64/falkor.md (falkor_other_0_nothing): Don't handle
no_insn here.
* config/aarch64/saphira.md (saphira_other_0_nothing): Likewise.
* config/aarch64/thunderx2t99.md (thunderx2t99_nothing): Likewise.
* config/aarch64/tsv110.md (tsv110_alu): Likewise.
* config/arm/arm1020e.md (1020alu_op): Likewise.
* config/arm/arm1026ejs.md (alu_op): Likewise.
* config/arm/arm1136jfs.md (11_alu_op): Likewise.
* config/arm/arm926ejs.md (9_alu_op): Likewise.
* config/arm/cortex-a15.md (cortex_a15_alu): Likewise.
* config/arm/cortex-a17.md (cortex_a17_alu): Likewise.
* config/arm/cortex-a5.md (cortex_a5_alu): Likewise.
* config/arm/cortex-a53.md (cortex_a53_alu): Likewise.
* config/arm/cortex-a57.md (cortex_a57_alu): Likewise.
* config/arm/cortex-a7.md (cortex_a7_alu_shift): Likewise.
* config/arm/cortex-a8.md (cortex_a8_alu): Likewise.
* config/arm/cortex-a9.md (cortex_a9_dp): Likewise.
* config/arm/cortex-m4.md (cortex_m4_alu): Likewise.
* config/arm/cortex-m7.md (cortex_m7_alu_simple): Likewise.
* config/arm/cortex-r4.md (cortex_r4_alu_shift_reg): Likewise.
* config/arm/fa526.md (526_alu_op): Likewise.
* config/arm/fa606te.md (606te_alu_op): Likewise.
* config/arm/fa626te.md (626te_alu_op): Likewise.
* config/arm/fa726te.md (726te_alu_op): Likewise.
* config/arm/xgene1.md (xgene1_nop): Likewise.
Index: gcc/config/arm/types.md
===================================================================
--- gcc/config/arm/types.md 2019-08-05 17:46:20.845722643 +0100
+++ gcc/config/arm/types.md 2019-09-17 15:54:23.574013006 +0100
@@ -1220,3 +1220,7 @@ (define_attr "is_neon_type" "yes,no"
crypto_sha256_fast, crypto_sha256_slow")
(const_string "yes")
(const_string "no")))
+
+(define_insn_reservation "no_reservation" 0
+ (eq_attr "type" "no_insn")
+ "nothing")
Index: gcc/config/aarch64/falkor.md
===================================================================
--- gcc/config/aarch64/falkor.md 2019-03-08 18:15:38.220734572 +0000
+++ gcc/config/aarch64/falkor.md 2019-09-17 15:54:23.566013066 +0100
@@ -648,7 +648,7 @@ (define_insn_reservation "falkor_mvs_1_x
(define_insn_reservation "falkor_other_0_nothing" 0
(and (eq_attr "tune" "falkor")
- (eq_attr "type" "no_insn,trap,block"))
+ (eq_attr "type" "trap,block"))
"nothing")
(define_insn_reservation "falkor_other_2_z" 2
Index: gcc/config/aarch64/saphira.md
===================================================================
--- gcc/config/aarch64/saphira.md 2019-03-08 18:15:38.224734558 +0000
+++ gcc/config/aarch64/saphira.md 2019-09-17 15:54:23.566013066 +0100
@@ -520,7 +520,7 @@ (define_insn_reservation "saphira_mvs_1_
(define_insn_reservation "saphira_other_0_nothing" 0
(and (eq_attr "tune" "saphira")
- (eq_attr "type" "no_insn,trap,block"))
+ (eq_attr "type" "trap,block"))
"nothing")
(define_insn_reservation "saphira_other_2_ld" 2
Index: gcc/config/aarch64/thunderx2t99.md
===================================================================
--- gcc/config/aarch64/thunderx2t99.md 2019-03-08 18:15:38.224734558 +0000
+++ gcc/config/aarch64/thunderx2t99.md 2019-09-17 15:54:23.570013036 +0100
@@ -74,7 +74,7 @@ (define_insn_reservation "thunderx2t99_b
(define_insn_reservation "thunderx2t99_nothing" 0
(and (eq_attr "tune" "thunderx2t99")
- (eq_attr "type" "no_insn,block"))
+ (eq_attr "type" "block"))
"nothing")
(define_insn_reservation "thunderx2t99_mrs" 0
Index: gcc/config/aarch64/tsv110.md
===================================================================
--- gcc/config/aarch64/tsv110.md 2019-04-08 21:55:28.290369445 +0100
+++ gcc/config/aarch64/tsv110.md 2019-09-17 15:54:23.570013036 +0100
@@ -281,7 +281,7 @@ (define_insn_reservation "tsv110_alu" 1
shift_imm,shift_reg,\
mov_imm,mov_reg,\
mvn_imm,mvn_reg,\
- mrs,multiple,no_insn"))
+ mrs,multiple"))
"tsv110_alu1|tsv110_alu2|tsv110_alu3")
(define_insn_reservation "tsv110_alus" 1
Index: gcc/config/arm/arm1020e.md
===================================================================
--- gcc/config/arm/arm1020e.md 2019-03-08 18:15:38.764732504 +0000
+++ gcc/config/arm/arm1020e.md 2019-09-17 15:54:23.570013036 +0100
@@ -72,7 +72,7 @@ (define_insn_reservation "1020alu_op" 1
adr,bfm,rev,\
shift_imm,shift_reg,\
mov_imm,mov_reg,mvn_imm,mvn_reg,\
- multiple,no_insn"))
+ multiple"))
"1020a_e,1020a_m,1020a_w")
;; ALU operations with a shift-by-constant operand
Index: gcc/config/arm/arm1026ejs.md
===================================================================
--- gcc/config/arm/arm1026ejs.md 2019-03-08 18:15:38.764732504 +0000
+++ gcc/config/arm/arm1026ejs.md 2019-09-17 15:54:23.570013036 +0100
@@ -72,7 +72,7 @@ (define_insn_reservation "alu_op" 1
adr,bfm,rev,\
shift_imm,shift_reg,\
mov_imm,mov_reg,mvn_imm,mvn_reg,\
- multiple,no_insn"))
+ multiple"))
"a_e,a_m,a_w")
;; ALU operations with a shift-by-constant operand
Index: gcc/config/arm/arm1136jfs.md
===================================================================
--- gcc/config/arm/arm1136jfs.md 2019-03-08 18:15:38.764732504 +0000
+++ gcc/config/arm/arm1136jfs.md 2019-09-17 15:54:23.570013036 +0100
@@ -81,7 +81,7 @@ (define_insn_reservation "11_alu_op" 2
adr,bfm,rev,\
shift_imm,shift_reg,\
mov_imm,mov_reg,mvn_imm,mvn_reg,\
- multiple,no_insn"))
+ multiple"))
"e_1,e_2,e_3,e_wb")
;; ALU operations with a shift-by-constant operand
Index: gcc/config/arm/arm926ejs.md
===================================================================
--- gcc/config/arm/arm926ejs.md 2019-03-08 18:15:38.772732474 +0000
+++ gcc/config/arm/arm926ejs.md 2019-09-17 15:54:23.570013036 +0100
@@ -67,7 +67,7 @@ (define_insn_reservation "9_alu_op" 1
shift_imm,shift_reg,extend,\
mov_imm,mov_reg,mov_shift,\
mvn_imm,mvn_reg,mvn_shift,\
- multiple,no_insn"))
+ multiple"))
"e,m,w")
;; ALU operations with a shift-by-register operand
Index: gcc/config/arm/cortex-a15.md
===================================================================
--- gcc/config/arm/cortex-a15.md 2019-03-08 18:15:38.764732504 +0000
+++ gcc/config/arm/cortex-a15.md 2019-09-17 15:54:23.570013036 +0100
@@ -68,7 +68,7 @@ (define_insn_reservation "cortex_a15_alu
shift_imm,shift_reg,\
mov_imm,mov_reg,\
mvn_imm,mvn_reg,\
- mrs,multiple,no_insn"))
+ mrs,multiple"))
"ca15_issue1,(ca15_sx1,ca15_sx1_alu)|(ca15_sx2,ca15_sx2_alu)")
;; ALU ops with immediate shift
Index: gcc/config/arm/cortex-a17.md
===================================================================
--- gcc/config/arm/cortex-a17.md 2019-03-08 18:15:38.772732474 +0000
+++ gcc/config/arm/cortex-a17.md 2019-09-17 15:54:23.570013036 +0100
@@ -42,7 +42,7 @@ (define_insn_reservation "cortex_a17_alu
adc_imm,adcs_imm,adc_reg,adcs_reg,\
adr, mov_imm,mov_reg,\
mvn_imm,mvn_reg,extend,\
- mrs,multiple,no_insn"))
+ mrs,multiple"))
"ca17_alu")
(define_insn_reservation "cortex_a17_alu_shiftimm" 2
Index: gcc/config/arm/cortex-a5.md
===================================================================
--- gcc/config/arm/cortex-a5.md 2019-03-08 18:15:38.776732461 +0000
+++ gcc/config/arm/cortex-a5.md 2019-09-17 15:54:23.574013006 +0100
@@ -64,7 +64,7 @@ (define_insn_reservation "cortex_a5_alu"
adr,bfm,clz,rbit,rev,alu_dsp_reg,\
shift_imm,shift_reg,\
mov_imm,mov_reg,mvn_imm,mvn_reg,\
- mrs,multiple,no_insn"))
+ mrs,multiple"))
"cortex_a5_ex1")
(define_insn_reservation "cortex_a5_alu_shift" 2
Index: gcc/config/arm/cortex-a53.md
===================================================================
--- gcc/config/arm/cortex-a53.md 2019-07-10 19:41:19.731951398 +0100
+++ gcc/config/arm/cortex-a53.md 2019-09-17 15:54:23.574013006 +0100
@@ -86,7 +86,7 @@ (define_insn_reservation "cortex_a53_alu
alu_sreg,alus_sreg,logic_reg,logics_reg,
adc_imm,adcs_imm,adc_reg,adcs_reg,
csel,clz,rbit,rev,alu_dsp_reg,
- mov_reg,mvn_reg,mrs,multiple,no_insn"))
+ mov_reg,mvn_reg,mrs,multiple"))
"cortex_a53_slot_any")
(define_insn_reservation "cortex_a53_alu_shift" 3
Index: gcc/config/arm/cortex-a57.md
===================================================================
--- gcc/config/arm/cortex-a57.md 2019-07-10 19:41:19.731951398 +0100
+++ gcc/config/arm/cortex-a57.md 2019-09-17 15:54:23.574013006 +0100
@@ -306,7 +306,7 @@ (define_insn_reservation "cortex_a57_alu
rotate_imm,shift_imm,shift_reg,\
mov_imm,mov_reg,\
mvn_imm,mvn_reg,\
- mrs,multiple,no_insn"))
+ mrs,multiple"))
"ca57_sx1|ca57_sx2")
;; ALU ops with immediate shift
Index: gcc/config/arm/cortex-a7.md
===================================================================
--- gcc/config/arm/cortex-a7.md 2019-03-08 18:15:38.772732474 +0000
+++ gcc/config/arm/cortex-a7.md 2019-09-17 15:54:23.574013006 +0100
@@ -149,7 +149,7 @@ (define_insn_reservation "cortex_a7_alu_
logic_shift_reg,logics_shift_reg,\
mov_shift,mov_shift_reg,\
mvn_shift,mvn_shift_reg,\
- mrs,multiple,no_insn"))
+ mrs,multiple"))
"cortex_a7_ex1")
;; Forwarding path for unshifted operands.
Index: gcc/config/arm/cortex-a8.md
===================================================================
--- gcc/config/arm/cortex-a8.md 2019-03-08 18:15:38.768732491 +0000
+++ gcc/config/arm/cortex-a8.md 2019-09-17 15:54:23.574013006 +0100
@@ -90,7 +90,7 @@ (define_insn_reservation "cortex_a8_alu"
adc_imm,adcs_imm,adc_reg,adcs_reg,\
adr,bfm,clz,rbit,rev,alu_dsp_reg,\
shift_imm,shift_reg,\
- multiple,no_insn"))
+ multiple"))
"cortex_a8_default")
(define_insn_reservation "cortex_a8_alu_shift" 2
Index: gcc/config/arm/cortex-a9.md
===================================================================
--- gcc/config/arm/cortex-a9.md 2019-03-08 18:15:38.776732461 +0000
+++ gcc/config/arm/cortex-a9.md 2019-09-17 15:54:23.574013006 +0100
@@ -87,7 +87,7 @@ (define_insn_reservation "cortex_a9_dp"
shift_imm,shift_reg,\
mov_imm,mov_reg,mvn_imm,mvn_reg,\
mov_shift_reg,mov_shift,\
- mrs,multiple,no_insn"))
+ mrs,multiple"))
"cortex_a9_p0_default|cortex_a9_p1_default")
;; An instruction using the shifter will go down E1.
Index: gcc/config/arm/cortex-m4.md
===================================================================
--- gcc/config/arm/cortex-m4.md 2019-03-08 18:15:38.768732491 +0000
+++ gcc/config/arm/cortex-m4.md 2019-09-17 15:54:23.574013006 +0100
@@ -42,7 +42,7 @@ (define_insn_reservation "cortex_m4_alu"
logic_shift_reg,logics_shift_reg,\
mov_imm,mov_reg,mov_shift,mov_shift_reg,\
mvn_imm,mvn_reg,mvn_shift,mvn_shift_reg,\
- mrs,multiple,no_insn")
+ mrs,multiple")
(ior (eq_attr "mul32" "yes")
(eq_attr "widen_mul64" "yes"))))
"cortex_m4_ex")
Index: gcc/config/arm/cortex-m7.md
===================================================================
--- gcc/config/arm/cortex-m7.md 2019-03-08 18:15:38.772732474 +0000
+++ gcc/config/arm/cortex-m7.md 2019-09-17 15:54:23.574013006 +0100
@@ -48,7 +48,7 @@ (define_insn_reservation "cortex_m7_alu_
logic_shift_imm,logics_shift_imm,\
alu_shift_reg,alus_shift_reg,\
logic_shift_reg,logics_shift_reg,\
- mrs,clz,f_mcr,f_mrc,multiple,no_insn"))
+ mrs,clz,f_mcr,f_mrc,multiple"))
"cm7_i0|cm7_i1,cm7_a0|cm7_a1")
;; Simple alu with inline shift operation.
Index: gcc/config/arm/cortex-r4.md
===================================================================
--- gcc/config/arm/cortex-r4.md 2019-03-08 18:15:38.768732491 +0000
+++ gcc/config/arm/cortex-r4.md 2019-09-17 15:54:23.574013006 +0100
@@ -102,7 +102,7 @@ (define_insn_reservation "cortex_r4_alu_
(eq_attr "type" "alu_shift_reg,alus_shift_reg,\
logic_shift_reg,logics_shift_reg,\
mov_shift_reg,mvn_shift_reg,\
- mrs,multiple,no_insn"))
+ mrs,multiple"))
"cortex_r4_alu_shift_reg")
;; An ALU instruction followed by an ALU instruction with no early dep.
Index: gcc/config/arm/fa526.md
===================================================================
--- gcc/config/arm/fa526.md 2019-03-08 18:15:38.776732461 +0000
+++ gcc/config/arm/fa526.md 2019-09-17 15:54:23.574013006 +0100
@@ -68,7 +68,7 @@ (define_insn_reservation "526_alu_op" 1
adr,bfm,rev,\
shift_imm,shift_reg,\
mov_imm,mov_reg,mvn_imm,mvn_reg,\
- mrs,multiple,no_insn"))
+ mrs,multiple"))
"fa526_core")
(define_insn_reservation "526_alu_shift_op" 2
Index: gcc/config/arm/fa606te.md
===================================================================
--- gcc/config/arm/fa606te.md 2019-03-08 18:15:38.776732461 +0000
+++ gcc/config/arm/fa606te.md 2019-09-17 15:54:23.574013006 +0100
@@ -73,7 +73,7 @@ (define_insn_reservation "606te_alu_op"
logic_shift_reg,logics_shift_reg,\
mov_imm,mov_reg,mov_shift,mov_shift_reg,\
mvn_imm,mvn_reg,mvn_shift,mvn_shift_reg,\
- mrs,multiple,no_insn"))
+ mrs,multiple"))
"fa606te_core")
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
Index: gcc/config/arm/fa626te.md
===================================================================
--- gcc/config/arm/fa626te.md 2019-03-08 18:15:38.776732461 +0000
+++ gcc/config/arm/fa626te.md 2019-09-17 15:54:23.574013006 +0100
@@ -74,7 +74,7 @@ (define_insn_reservation "626te_alu_op"
adr,bfm,rev,\
shift_imm,shift_reg,\
mov_imm,mov_reg,mvn_imm,mvn_reg,\
- mrs,multiple,no_insn"))
+ mrs,multiple"))
"fa626te_core")
(define_insn_reservation "626te_alu_shift_op" 2
Index: gcc/config/arm/fa726te.md
===================================================================
--- gcc/config/arm/fa726te.md 2019-03-08 18:15:38.772732474 +0000
+++ gcc/config/arm/fa726te.md 2019-09-17 15:54:23.574013006 +0100
@@ -91,7 +91,7 @@ (define_insn_reservation "726te_alu_op"
adc_imm,adcs_imm,adc_reg,adcs_reg,\
adr,bfm,rev,\
shift_imm,shift_reg,\
- mrs,multiple,no_insn"))
+ mrs,multiple"))
"fa726te_issue+(fa726te_alu0_pipe|fa726te_alu1_pipe)")
;; ALU operations with a shift-by-register operand.
Index: gcc/config/arm/xgene1.md
===================================================================
--- gcc/config/arm/xgene1.md 2019-03-08 18:15:38.776732461 +0000
+++ gcc/config/arm/xgene1.md 2019-09-17 15:54:23.574013006 +0100
@@ -64,11 +64,6 @@ (define_insn_reservation "xgene1_branch"
(eq_attr "type" "branch"))
"xgene1_decode1op")
-(define_insn_reservation "xgene1_nop" 1
- (and (eq_attr "tune" "xgene1")
- (eq_attr "type" "no_insn"))
- "xgene1_decode1op")
-
(define_insn_reservation "xgene1_call" 1
(and (eq_attr "tune" "xgene1")
(eq_attr "type" "call"))
^ permalink raw reply [flat|nested] 3+ messages in thread
* Re: [arm][aarch64] Make no_insn issue to nothing
2019-09-17 14:57 [arm][aarch64] Make no_insn issue to nothing Richard Sandiford
@ 2019-09-17 15:38 ` Richard Earnshaw (lists)
2019-09-17 16:58 ` Richard Sandiford
0 siblings, 1 reply; 3+ messages in thread
From: Richard Earnshaw (lists) @ 2019-09-17 15:38 UTC (permalink / raw)
To: gcc-patches, james.greenhalgh, marcus.shawcroft, nickc,
ramana.radhakrishnan, kyrylo.tkachov, richard.sandiford
On 17/09/2019 15:57, Richard Sandiford wrote:
> no_insn is documented as:
>
> an insn which does not represent an instruction in the final output,
> thus having no impact on scheduling.
>
> and is used in that way by the arm port (e.g. for define_insns that
> expand to comments). However, most scheduling descriptions instead
> assigned units to no_insn patterns, in some cases treating them as more
> expensive than a plain move.
>
> This patch removes the no_insn handling from individual scheduling
> descriptions and uses a common define_insn_reservation for all CPUs.
>
> Tested on aarch64-linux-gnu and armeab-none-eabi. OK to install?
>
OK.
Out of interest, does this affect the number of atomata states
significantly?
R.
> Richard
>
>
> 2019-09-17 Richard Sandiford <richard.sandiford@arm.com>
>
> gcc/
> * config/arm/types.md (no_reservation): New reservation.
> * config/aarch64/falkor.md (falkor_other_0_nothing): Don't handle
> no_insn here.
> * config/aarch64/saphira.md (saphira_other_0_nothing): Likewise.
> * config/aarch64/thunderx2t99.md (thunderx2t99_nothing): Likewise.
> * config/aarch64/tsv110.md (tsv110_alu): Likewise.
> * config/arm/arm1020e.md (1020alu_op): Likewise.
> * config/arm/arm1026ejs.md (alu_op): Likewise.
> * config/arm/arm1136jfs.md (11_alu_op): Likewise.
> * config/arm/arm926ejs.md (9_alu_op): Likewise.
> * config/arm/cortex-a15.md (cortex_a15_alu): Likewise.
> * config/arm/cortex-a17.md (cortex_a17_alu): Likewise.
> * config/arm/cortex-a5.md (cortex_a5_alu): Likewise.
> * config/arm/cortex-a53.md (cortex_a53_alu): Likewise.
> * config/arm/cortex-a57.md (cortex_a57_alu): Likewise.
> * config/arm/cortex-a7.md (cortex_a7_alu_shift): Likewise.
> * config/arm/cortex-a8.md (cortex_a8_alu): Likewise.
> * config/arm/cortex-a9.md (cortex_a9_dp): Likewise.
> * config/arm/cortex-m4.md (cortex_m4_alu): Likewise.
> * config/arm/cortex-m7.md (cortex_m7_alu_simple): Likewise.
> * config/arm/cortex-r4.md (cortex_r4_alu_shift_reg): Likewise.
> * config/arm/fa526.md (526_alu_op): Likewise.
> * config/arm/fa606te.md (606te_alu_op): Likewise.
> * config/arm/fa626te.md (626te_alu_op): Likewise.
> * config/arm/fa726te.md (726te_alu_op): Likewise.
> * config/arm/xgene1.md (xgene1_nop): Likewise.
>
> Index: gcc/config/arm/types.md
> ===================================================================
> --- gcc/config/arm/types.md 2019-08-05 17:46:20.845722643 +0100
> +++ gcc/config/arm/types.md 2019-09-17 15:54:23.574013006 +0100
> @@ -1220,3 +1220,7 @@ (define_attr "is_neon_type" "yes,no"
> crypto_sha256_fast, crypto_sha256_slow")
> (const_string "yes")
> (const_string "no")))
> +
> +(define_insn_reservation "no_reservation" 0
> + (eq_attr "type" "no_insn")
> + "nothing")
> Index: gcc/config/aarch64/falkor.md
> ===================================================================
> --- gcc/config/aarch64/falkor.md 2019-03-08 18:15:38.220734572 +0000
> +++ gcc/config/aarch64/falkor.md 2019-09-17 15:54:23.566013066 +0100
> @@ -648,7 +648,7 @@ (define_insn_reservation "falkor_mvs_1_x
>
> (define_insn_reservation "falkor_other_0_nothing" 0
> (and (eq_attr "tune" "falkor")
> - (eq_attr "type" "no_insn,trap,block"))
> + (eq_attr "type" "trap,block"))
> "nothing")
>
> (define_insn_reservation "falkor_other_2_z" 2
> Index: gcc/config/aarch64/saphira.md
> ===================================================================
> --- gcc/config/aarch64/saphira.md 2019-03-08 18:15:38.224734558 +0000
> +++ gcc/config/aarch64/saphira.md 2019-09-17 15:54:23.566013066 +0100
> @@ -520,7 +520,7 @@ (define_insn_reservation "saphira_mvs_1_
>
> (define_insn_reservation "saphira_other_0_nothing" 0
> (and (eq_attr "tune" "saphira")
> - (eq_attr "type" "no_insn,trap,block"))
> + (eq_attr "type" "trap,block"))
> "nothing")
>
> (define_insn_reservation "saphira_other_2_ld" 2
> Index: gcc/config/aarch64/thunderx2t99.md
> ===================================================================
> --- gcc/config/aarch64/thunderx2t99.md 2019-03-08 18:15:38.224734558 +0000
> +++ gcc/config/aarch64/thunderx2t99.md 2019-09-17 15:54:23.570013036 +0100
> @@ -74,7 +74,7 @@ (define_insn_reservation "thunderx2t99_b
>
> (define_insn_reservation "thunderx2t99_nothing" 0
> (and (eq_attr "tune" "thunderx2t99")
> - (eq_attr "type" "no_insn,block"))
> + (eq_attr "type" "block"))
> "nothing")
>
> (define_insn_reservation "thunderx2t99_mrs" 0
> Index: gcc/config/aarch64/tsv110.md
> ===================================================================
> --- gcc/config/aarch64/tsv110.md 2019-04-08 21:55:28.290369445 +0100
> +++ gcc/config/aarch64/tsv110.md 2019-09-17 15:54:23.570013036 +0100
> @@ -281,7 +281,7 @@ (define_insn_reservation "tsv110_alu" 1
> shift_imm,shift_reg,\
> mov_imm,mov_reg,\
> mvn_imm,mvn_reg,\
> - mrs,multiple,no_insn"))
> + mrs,multiple"))
> "tsv110_alu1|tsv110_alu2|tsv110_alu3")
>
> (define_insn_reservation "tsv110_alus" 1
> Index: gcc/config/arm/arm1020e.md
> ===================================================================
> --- gcc/config/arm/arm1020e.md 2019-03-08 18:15:38.764732504 +0000
> +++ gcc/config/arm/arm1020e.md 2019-09-17 15:54:23.570013036 +0100
> @@ -72,7 +72,7 @@ (define_insn_reservation "1020alu_op" 1
> adr,bfm,rev,\
> shift_imm,shift_reg,\
> mov_imm,mov_reg,mvn_imm,mvn_reg,\
> - multiple,no_insn"))
> + multiple"))
> "1020a_e,1020a_m,1020a_w")
>
> ;; ALU operations with a shift-by-constant operand
> Index: gcc/config/arm/arm1026ejs.md
> ===================================================================
> --- gcc/config/arm/arm1026ejs.md 2019-03-08 18:15:38.764732504 +0000
> +++ gcc/config/arm/arm1026ejs.md 2019-09-17 15:54:23.570013036 +0100
> @@ -72,7 +72,7 @@ (define_insn_reservation "alu_op" 1
> adr,bfm,rev,\
> shift_imm,shift_reg,\
> mov_imm,mov_reg,mvn_imm,mvn_reg,\
> - multiple,no_insn"))
> + multiple"))
> "a_e,a_m,a_w")
>
> ;; ALU operations with a shift-by-constant operand
> Index: gcc/config/arm/arm1136jfs.md
> ===================================================================
> --- gcc/config/arm/arm1136jfs.md 2019-03-08 18:15:38.764732504 +0000
> +++ gcc/config/arm/arm1136jfs.md 2019-09-17 15:54:23.570013036 +0100
> @@ -81,7 +81,7 @@ (define_insn_reservation "11_alu_op" 2
> adr,bfm,rev,\
> shift_imm,shift_reg,\
> mov_imm,mov_reg,mvn_imm,mvn_reg,\
> - multiple,no_insn"))
> + multiple"))
> "e_1,e_2,e_3,e_wb")
>
> ;; ALU operations with a shift-by-constant operand
> Index: gcc/config/arm/arm926ejs.md
> ===================================================================
> --- gcc/config/arm/arm926ejs.md 2019-03-08 18:15:38.772732474 +0000
> +++ gcc/config/arm/arm926ejs.md 2019-09-17 15:54:23.570013036 +0100
> @@ -67,7 +67,7 @@ (define_insn_reservation "9_alu_op" 1
> shift_imm,shift_reg,extend,\
> mov_imm,mov_reg,mov_shift,\
> mvn_imm,mvn_reg,mvn_shift,\
> - multiple,no_insn"))
> + multiple"))
> "e,m,w")
>
> ;; ALU operations with a shift-by-register operand
> Index: gcc/config/arm/cortex-a15.md
> ===================================================================
> --- gcc/config/arm/cortex-a15.md 2019-03-08 18:15:38.764732504 +0000
> +++ gcc/config/arm/cortex-a15.md 2019-09-17 15:54:23.570013036 +0100
> @@ -68,7 +68,7 @@ (define_insn_reservation "cortex_a15_alu
> shift_imm,shift_reg,\
> mov_imm,mov_reg,\
> mvn_imm,mvn_reg,\
> - mrs,multiple,no_insn"))
> + mrs,multiple"))
> "ca15_issue1,(ca15_sx1,ca15_sx1_alu)|(ca15_sx2,ca15_sx2_alu)")
>
> ;; ALU ops with immediate shift
> Index: gcc/config/arm/cortex-a17.md
> ===================================================================
> --- gcc/config/arm/cortex-a17.md 2019-03-08 18:15:38.772732474 +0000
> +++ gcc/config/arm/cortex-a17.md 2019-09-17 15:54:23.570013036 +0100
> @@ -42,7 +42,7 @@ (define_insn_reservation "cortex_a17_alu
> adc_imm,adcs_imm,adc_reg,adcs_reg,\
> adr, mov_imm,mov_reg,\
> mvn_imm,mvn_reg,extend,\
> - mrs,multiple,no_insn"))
> + mrs,multiple"))
> "ca17_alu")
>
> (define_insn_reservation "cortex_a17_alu_shiftimm" 2
> Index: gcc/config/arm/cortex-a5.md
> ===================================================================
> --- gcc/config/arm/cortex-a5.md 2019-03-08 18:15:38.776732461 +0000
> +++ gcc/config/arm/cortex-a5.md 2019-09-17 15:54:23.574013006 +0100
> @@ -64,7 +64,7 @@ (define_insn_reservation "cortex_a5_alu"
> adr,bfm,clz,rbit,rev,alu_dsp_reg,\
> shift_imm,shift_reg,\
> mov_imm,mov_reg,mvn_imm,mvn_reg,\
> - mrs,multiple,no_insn"))
> + mrs,multiple"))
> "cortex_a5_ex1")
>
> (define_insn_reservation "cortex_a5_alu_shift" 2
> Index: gcc/config/arm/cortex-a53.md
> ===================================================================
> --- gcc/config/arm/cortex-a53.md 2019-07-10 19:41:19.731951398 +0100
> +++ gcc/config/arm/cortex-a53.md 2019-09-17 15:54:23.574013006 +0100
> @@ -86,7 +86,7 @@ (define_insn_reservation "cortex_a53_alu
> alu_sreg,alus_sreg,logic_reg,logics_reg,
> adc_imm,adcs_imm,adc_reg,adcs_reg,
> csel,clz,rbit,rev,alu_dsp_reg,
> - mov_reg,mvn_reg,mrs,multiple,no_insn"))
> + mov_reg,mvn_reg,mrs,multiple"))
> "cortex_a53_slot_any")
>
> (define_insn_reservation "cortex_a53_alu_shift" 3
> Index: gcc/config/arm/cortex-a57.md
> ===================================================================
> --- gcc/config/arm/cortex-a57.md 2019-07-10 19:41:19.731951398 +0100
> +++ gcc/config/arm/cortex-a57.md 2019-09-17 15:54:23.574013006 +0100
> @@ -306,7 +306,7 @@ (define_insn_reservation "cortex_a57_alu
> rotate_imm,shift_imm,shift_reg,\
> mov_imm,mov_reg,\
> mvn_imm,mvn_reg,\
> - mrs,multiple,no_insn"))
> + mrs,multiple"))
> "ca57_sx1|ca57_sx2")
>
> ;; ALU ops with immediate shift
> Index: gcc/config/arm/cortex-a7.md
> ===================================================================
> --- gcc/config/arm/cortex-a7.md 2019-03-08 18:15:38.772732474 +0000
> +++ gcc/config/arm/cortex-a7.md 2019-09-17 15:54:23.574013006 +0100
> @@ -149,7 +149,7 @@ (define_insn_reservation "cortex_a7_alu_
> logic_shift_reg,logics_shift_reg,\
> mov_shift,mov_shift_reg,\
> mvn_shift,mvn_shift_reg,\
> - mrs,multiple,no_insn"))
> + mrs,multiple"))
> "cortex_a7_ex1")
>
> ;; Forwarding path for unshifted operands.
> Index: gcc/config/arm/cortex-a8.md
> ===================================================================
> --- gcc/config/arm/cortex-a8.md 2019-03-08 18:15:38.768732491 +0000
> +++ gcc/config/arm/cortex-a8.md 2019-09-17 15:54:23.574013006 +0100
> @@ -90,7 +90,7 @@ (define_insn_reservation "cortex_a8_alu"
> adc_imm,adcs_imm,adc_reg,adcs_reg,\
> adr,bfm,clz,rbit,rev,alu_dsp_reg,\
> shift_imm,shift_reg,\
> - multiple,no_insn"))
> + multiple"))
> "cortex_a8_default")
>
> (define_insn_reservation "cortex_a8_alu_shift" 2
> Index: gcc/config/arm/cortex-a9.md
> ===================================================================
> --- gcc/config/arm/cortex-a9.md 2019-03-08 18:15:38.776732461 +0000
> +++ gcc/config/arm/cortex-a9.md 2019-09-17 15:54:23.574013006 +0100
> @@ -87,7 +87,7 @@ (define_insn_reservation "cortex_a9_dp"
> shift_imm,shift_reg,\
> mov_imm,mov_reg,mvn_imm,mvn_reg,\
> mov_shift_reg,mov_shift,\
> - mrs,multiple,no_insn"))
> + mrs,multiple"))
> "cortex_a9_p0_default|cortex_a9_p1_default")
>
> ;; An instruction using the shifter will go down E1.
> Index: gcc/config/arm/cortex-m4.md
> ===================================================================
> --- gcc/config/arm/cortex-m4.md 2019-03-08 18:15:38.768732491 +0000
> +++ gcc/config/arm/cortex-m4.md 2019-09-17 15:54:23.574013006 +0100
> @@ -42,7 +42,7 @@ (define_insn_reservation "cortex_m4_alu"
> logic_shift_reg,logics_shift_reg,\
> mov_imm,mov_reg,mov_shift,mov_shift_reg,\
> mvn_imm,mvn_reg,mvn_shift,mvn_shift_reg,\
> - mrs,multiple,no_insn")
> + mrs,multiple")
> (ior (eq_attr "mul32" "yes")
> (eq_attr "widen_mul64" "yes"))))
> "cortex_m4_ex")
> Index: gcc/config/arm/cortex-m7.md
> ===================================================================
> --- gcc/config/arm/cortex-m7.md 2019-03-08 18:15:38.772732474 +0000
> +++ gcc/config/arm/cortex-m7.md 2019-09-17 15:54:23.574013006 +0100
> @@ -48,7 +48,7 @@ (define_insn_reservation "cortex_m7_alu_
> logic_shift_imm,logics_shift_imm,\
> alu_shift_reg,alus_shift_reg,\
> logic_shift_reg,logics_shift_reg,\
> - mrs,clz,f_mcr,f_mrc,multiple,no_insn"))
> + mrs,clz,f_mcr,f_mrc,multiple"))
> "cm7_i0|cm7_i1,cm7_a0|cm7_a1")
>
> ;; Simple alu with inline shift operation.
> Index: gcc/config/arm/cortex-r4.md
> ===================================================================
> --- gcc/config/arm/cortex-r4.md 2019-03-08 18:15:38.768732491 +0000
> +++ gcc/config/arm/cortex-r4.md 2019-09-17 15:54:23.574013006 +0100
> @@ -102,7 +102,7 @@ (define_insn_reservation "cortex_r4_alu_
> (eq_attr "type" "alu_shift_reg,alus_shift_reg,\
> logic_shift_reg,logics_shift_reg,\
> mov_shift_reg,mvn_shift_reg,\
> - mrs,multiple,no_insn"))
> + mrs,multiple"))
> "cortex_r4_alu_shift_reg")
>
> ;; An ALU instruction followed by an ALU instruction with no early dep.
> Index: gcc/config/arm/fa526.md
> ===================================================================
> --- gcc/config/arm/fa526.md 2019-03-08 18:15:38.776732461 +0000
> +++ gcc/config/arm/fa526.md 2019-09-17 15:54:23.574013006 +0100
> @@ -68,7 +68,7 @@ (define_insn_reservation "526_alu_op" 1
> adr,bfm,rev,\
> shift_imm,shift_reg,\
> mov_imm,mov_reg,mvn_imm,mvn_reg,\
> - mrs,multiple,no_insn"))
> + mrs,multiple"))
> "fa526_core")
>
> (define_insn_reservation "526_alu_shift_op" 2
> Index: gcc/config/arm/fa606te.md
> ===================================================================
> --- gcc/config/arm/fa606te.md 2019-03-08 18:15:38.776732461 +0000
> +++ gcc/config/arm/fa606te.md 2019-09-17 15:54:23.574013006 +0100
> @@ -73,7 +73,7 @@ (define_insn_reservation "606te_alu_op"
> logic_shift_reg,logics_shift_reg,\
> mov_imm,mov_reg,mov_shift,mov_shift_reg,\
> mvn_imm,mvn_reg,mvn_shift,mvn_shift_reg,\
> - mrs,multiple,no_insn"))
> + mrs,multiple"))
> "fa606te_core")
>
> ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
> Index: gcc/config/arm/fa626te.md
> ===================================================================
> --- gcc/config/arm/fa626te.md 2019-03-08 18:15:38.776732461 +0000
> +++ gcc/config/arm/fa626te.md 2019-09-17 15:54:23.574013006 +0100
> @@ -74,7 +74,7 @@ (define_insn_reservation "626te_alu_op"
> adr,bfm,rev,\
> shift_imm,shift_reg,\
> mov_imm,mov_reg,mvn_imm,mvn_reg,\
> - mrs,multiple,no_insn"))
> + mrs,multiple"))
> "fa626te_core")
>
> (define_insn_reservation "626te_alu_shift_op" 2
> Index: gcc/config/arm/fa726te.md
> ===================================================================
> --- gcc/config/arm/fa726te.md 2019-03-08 18:15:38.772732474 +0000
> +++ gcc/config/arm/fa726te.md 2019-09-17 15:54:23.574013006 +0100
> @@ -91,7 +91,7 @@ (define_insn_reservation "726te_alu_op"
> adc_imm,adcs_imm,adc_reg,adcs_reg,\
> adr,bfm,rev,\
> shift_imm,shift_reg,\
> - mrs,multiple,no_insn"))
> + mrs,multiple"))
> "fa726te_issue+(fa726te_alu0_pipe|fa726te_alu1_pipe)")
>
> ;; ALU operations with a shift-by-register operand.
> Index: gcc/config/arm/xgene1.md
> ===================================================================
> --- gcc/config/arm/xgene1.md 2019-03-08 18:15:38.776732461 +0000
> +++ gcc/config/arm/xgene1.md 2019-09-17 15:54:23.574013006 +0100
> @@ -64,11 +64,6 @@ (define_insn_reservation "xgene1_branch"
> (eq_attr "type" "branch"))
> "xgene1_decode1op")
>
> -(define_insn_reservation "xgene1_nop" 1
> - (and (eq_attr "tune" "xgene1")
> - (eq_attr "type" "no_insn"))
> - "xgene1_decode1op")
> -
> (define_insn_reservation "xgene1_call" 1
> (and (eq_attr "tune" "xgene1")
> (eq_attr "type" "call"))
>
^ permalink raw reply [flat|nested] 3+ messages in thread
* Re: [arm][aarch64] Make no_insn issue to nothing
2019-09-17 15:38 ` Richard Earnshaw (lists)
@ 2019-09-17 16:58 ` Richard Sandiford
0 siblings, 0 replies; 3+ messages in thread
From: Richard Sandiford @ 2019-09-17 16:58 UTC (permalink / raw)
To: Richard Earnshaw (lists)
Cc: gcc-patches, james.greenhalgh, marcus.shawcroft, nickc,
ramana.radhakrishnan, kyrylo.tkachov
"Richard Earnshaw (lists)" <Richard.Earnshaw@arm.com> writes:
> On 17/09/2019 15:57, Richard Sandiford wrote:
>> no_insn is documented as:
>>
>> an insn which does not represent an instruction in the final output,
>> thus having no impact on scheduling.
>>
>> and is used in that way by the arm port (e.g. for define_insns that
>> expand to comments). However, most scheduling descriptions instead
>> assigned units to no_insn patterns, in some cases treating them as more
>> expensive than a plain move.
>>
>> This patch removes the no_insn handling from individual scheduling
>> descriptions and uses a common define_insn_reservation for all CPUs.
>>
>> Tested on aarch64-linux-gnu and armeab-none-eabi. OK to install?
>>
>
> OK.
>
> Out of interest, does this affect the number of atomata states
> significantly?
No, it's a very minor improvement, but not one we'll notice:
@@ -5,7 +5,7 @@
15 minimal DFA states, 113 minimal DFA arcs
629 all insns 14 insn equivalence classes
0 locked states
- 145 transition comb vector els, 210 trans table els: use simple vect
+ 142 transition comb vector els, 210 trans table els: use simple vect
210 min delay table els, compression factor 4
Automaton `cortex_a53_advsimd'
@@ -243,7 +243,7 @@
35 min delay table els, compression factor 4
13689 all allocated states, 38825 all allocated arcs
-43554 all allocated alternative states
-45768 all transition comb vector els, 91862 all trans table els
+43473 all allocated alternative states
+45765 all transition comb vector els, 91862 all trans table els
91862 all min delay table els
0 all locked states
Thanks,
Richard
^ permalink raw reply [flat|nested] 3+ messages in thread
end of thread, other threads:[~2019-09-17 16:58 UTC | newest]
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2019-09-17 14:57 [arm][aarch64] Make no_insn issue to nothing Richard Sandiford
2019-09-17 15:38 ` Richard Earnshaw (lists)
2019-09-17 16:58 ` Richard Sandiford
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