From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by sourceware.org (Postfix) with ESMTP id B5A923858D28 for ; Fri, 24 Nov 2023 11:38:40 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org B5A923858D28 Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=arm.com ARC-Filter: OpenARC Filter v1.0.0 sourceware.org B5A923858D28 Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1700825922; cv=none; b=kSFpnbVnip7i5Sxl4ktNlGkOKun2RSchulmkB4Z82Sljmy6j21GTsykUdnRSbNJqBBKZXeGYphcKWFnqGoK/jKnQsXvzqzh/sz9Uf1cB38/+dhoUGd6/1TilUJjhHqYhRoR9ocIwjrSXSg7bmGXZn4+HIqxfVvmdPBVmau5FTPc= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1700825922; c=relaxed/simple; bh=qsrORoC4QUoGnfpf5V3pPM2qV17s8gK5QBDSx50Hubw=; h=From:To:Subject:Date:Message-ID:MIME-Version; b=wr+epRgKwxw0lMZdgItJ9kKmlmpBMa2E34Jz8QVw8HUsr7OFkpHtOj4uy6E5wXVQ1LGqcWKOHB58Tp+5ShRInxXab7aCN8is5sbX2WKS6iEmI3fvJGSallMr/fijyddXt1pFttHiILj7dBBcbe+T/kSDE0DnH6n7pxtyeXXCuXs= ARC-Authentication-Results: i=1; server2.sourceware.org Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id E00A11063; Fri, 24 Nov 2023 03:39:26 -0800 (PST) Received: from localhost (e121540-lin.manchester.arm.com [10.32.110.72]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id BDF263F7A6; Fri, 24 Nov 2023 03:38:39 -0800 (PST) From: Richard Sandiford To: Victor Do Nascimento Mail-Followup-To: Victor Do Nascimento ,, , , richard.sandiford@arm.com Cc: , , Subject: Re: [PATCH 3/5] aarch64: rcpc3: Add Neon ACLE intrinsics References: <20231109141300.3542453-1-victor.donascimento@arm.com> <20231109141300.3542453-4-victor.donascimento@arm.com> Date: Fri, 24 Nov 2023 11:38:38 +0000 In-Reply-To: <20231109141300.3542453-4-victor.donascimento@arm.com> (Victor Do Nascimento's message of "Thu, 9 Nov 2023 14:12:46 +0000") Message-ID: User-Agent: Gnus/5.13 (Gnus v5.13) Emacs/26.3 (gnu/linux) MIME-Version: 1.0 Content-Type: text/plain X-Spam-Status: No, score=-22.6 required=5.0 tests=BAYES_00,GIT_PATCH_0,KAM_DMARC_NONE,KAM_DMARC_STATUS,KAM_LAZY_DOMAIN_SECURITY,SPF_HELO_NONE,SPF_NONE,TXREP,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: Victor Do Nascimento writes: > Register the target specific builtins in `aarch64-simd-builtins.def' > and implement their associated backend patterns in `aarch64-simd.md'. > > gcc/ChangeLog: > > * config/aarch64/aarch64-simd-builtins.def > (vec_ldap1_lane): New. > (vec_stl1_lane): Likewise. > * config/aarch64/aarch64-simd.md > (aarch64_vec_stl1_lanes_lane): New. > (aarch64_vec_stl1_lane): Likewise. > (aarch64_vec_ldap1_lanes_lane): Likewise. > (aarch64_vec_ldap1_lane): Likewise. OK, thanks. Richard > --- > gcc/config/aarch64/aarch64-simd-builtins.def | 7 +++ > gcc/config/aarch64/aarch64-simd.md | 65 ++++++++++++++++++++ > gcc/config/aarch64/aarch64.md | 2 + > 3 files changed, 74 insertions(+) > > diff --git a/gcc/config/aarch64/aarch64-simd-builtins.def b/gcc/config/aarch64/aarch64-simd-builtins.def > index e2b94ad8247..0ae6c4ad41a 100644 > --- a/gcc/config/aarch64/aarch64-simd-builtins.def > +++ b/gcc/config/aarch64/aarch64-simd-builtins.def > @@ -43,6 +43,13 @@ > help describe the attributes (for example, pure) for the intrinsic > function. */ > > + BUILTIN_V12DIF (LOADSTRUCT_LANE, vec_ldap1_lane, 0, ALL) > + BUILTIN_V12DIUP (LOADSTRUCT_LANE_U, vec_ldap1_lane, 0, ALL) > + BUILTIN_V12DIUP (LOADSTRUCT_LANE_P, vec_ldap1_lane, 0, ALL) > + BUILTIN_V12DIF (STORESTRUCT_LANE, vec_stl1_lane, 0, ALL) > + BUILTIN_V12DIUP (STORESTRUCT_LANE_U, vec_stl1_lane, 0, ALL) > + BUILTIN_V12DIUP (STORESTRUCT_LANE_P, vec_stl1_lane, 0, ALL) > + > BUILTIN_VDC (BINOP, combine, 0, AUTO_FP) > BUILTIN_VD_I (BINOPU, combine, 0, NONE) > BUILTIN_VDC_P (BINOPP, combine, 0, NONE) > diff --git a/gcc/config/aarch64/aarch64-simd.md b/gcc/config/aarch64/aarch64-simd.md > index 81ff5bad03d..79697336f61 100644 > --- a/gcc/config/aarch64/aarch64-simd.md > +++ b/gcc/config/aarch64/aarch64-simd.md > @@ -7697,6 +7697,71 @@ > DONE; > }) > > +;; Patterns for rcpc3 vector lane loads and stores. > + > +(define_insn "aarch64_vec_stl1_lanes_lane" > + [(set (match_operand:BLK 0 "aarch64_simd_struct_operand" "=Q") > + (unspec:BLK [(match_operand:V12DIF 1 "register_operand" "w") > + (match_operand:SI 2 "immediate_operand" "i")] > + UNSPEC_STL1_LANE))] > + "TARGET_RCPC3" > + { > + operands[2] = aarch64_endian_lane_rtx (mode, > + INTVAL (operands[2])); > + return "stl1\\t{%S1.}[%2], %0"; > + } > + [(set_attr "type" "neon_store2_one_lane")] > +) > + > +(define_expand "aarch64_vec_stl1_lane" > + [(match_operand:DI 0 "register_operand") > + (match_operand:V12DIF 1 "register_operand") > + (match_operand:SI 2 "immediate_operand")] > + "TARGET_RCPC3" > +{ > + rtx mem = gen_rtx_MEM (BLKmode, operands[0]); > + set_mem_size (mem, GET_MODE_SIZE (GET_MODE_INNER (mode))); > + > + aarch64_simd_lane_bounds (operands[2], 0, > + GET_MODE_NUNITS (mode).to_constant (), NULL); > + emit_insn (gen_aarch64_vec_stl1_lanes_lane (mem, > + operands[1], operands[2])); > + DONE; > +}) > + > +(define_insn "aarch64_vec_ldap1_lanes_lane" > + [(set (match_operand:V12DIF 0 "register_operand" "=w") > + (unspec:V12DIF [ > + (match_operand:BLK 1 "aarch64_simd_struct_operand" "Q") > + (match_operand:V12DIF 2 "register_operand" "0") > + (match_operand:SI 3 "immediate_operand" "i")] > + UNSPEC_LDAP1_LANE))] > + "TARGET_RCPC3" > + { > + operands[3] = aarch64_endian_lane_rtx (mode, > + INTVAL (operands[3])); > + return "ldap1\\t{%S0.}[%3], %1"; > + } > + [(set_attr "type" "neon_load2_one_lane")] > +) > + > +(define_expand "aarch64_vec_ldap1_lane" > + [(match_operand:V12DIF 0 "register_operand") > + (match_operand:DI 1 "register_operand") > + (match_operand:V12DIF 2 "register_operand") > + (match_operand:SI 3 "immediate_operand")] > + "TARGET_RCPC3" > +{ > + rtx mem = gen_rtx_MEM (BLKmode, operands[1]); > + set_mem_size (mem, GET_MODE_SIZE (GET_MODE_INNER (mode))); > + > + aarch64_simd_lane_bounds (operands[3], 0, > + GET_MODE_NUNITS (mode).to_constant (), NULL); > + emit_insn (gen_aarch64_vec_ldap1_lanes_lane (operands[0], > + mem, operands[2], operands[3])); > + DONE; > +}) > + > (define_insn_and_split "aarch64_rev_reglist" > [(set (match_operand:VSTRUCT_QD 0 "register_operand" "=&w") > (unspec:VSTRUCT_QD > diff --git a/gcc/config/aarch64/aarch64.md b/gcc/config/aarch64/aarch64.md > index 5bb8c772be8..fb6de3b1fbf 100644 > --- a/gcc/config/aarch64/aarch64.md > +++ b/gcc/config/aarch64/aarch64.md > @@ -295,6 +295,8 @@ > UNSPEC_LD1RO > UNSPEC_SALT_ADDR > UNSPECV_PATCHABLE_AREA > + UNSPEC_LDAP1_LANE > + UNSPEC_STL1_LANE > ]) > > (define_c_enum "unspecv" [