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From: Richard Sandiford <richard.sandiford@arm.com>
To: =?utf-8?B?6ZKf5bGF5ZOy?= <juzhe.zhong@rivai.ai>
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Subject: Re: [PATCH] RISC-V: Add opaque integer modes to fix ICE on DSE[PR111590]
References: <20230926024507.3076723-1-juzhe.zhong@rivai.ai>
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Date: Tue, 26 Sep 2023 19:59:42 +0100
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=E9=92=9F=E5=B1=85=E5=93=B2 <juzhe.zhong@rivai.ai> writes:
> Thanks Richard.
>
> Is it correct as follows ?
>
> diff --git a/gcc/dse.cc b/gcc/dse.cc
> index 8b07be17674..c58d3bf4e1b 100644
> --- a/gcc/dse.cc
> +++ b/gcc/dse.cc
> @@ -1733,7 +1733,7 @@ find_shift_sequence (poly_int64 access_size,
>    /* If a constant was stored into memory, try to simplify it here,
>       otherwise the cost of the shift might preclude this optimization
>       e.g. at -Os, even when no actual shift will be needed.  */
> -  if (store_info->const_rhs)
> +  if (store_info->const_rhs && known_le (access_size, GET_MODE_SIZE (MAX=
_MODE_INT)))

Yes, but the "&& ..." needs to be on a new line because of the 80-character
limit.

> I failed to find native_encode_rtx and native_decode_rtx.

See simplify-rtx.cc.

Richard