From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by sourceware.org (Postfix) with ESMTP id 445953854543 for ; Mon, 5 Dec 2022 10:52:32 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 445953854543 Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 8D68123A; Mon, 5 Dec 2022 02:52:38 -0800 (PST) Received: from localhost (e121540-lin.manchester.arm.com [10.32.98.62]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 645133F73D; Mon, 5 Dec 2022 02:52:31 -0800 (PST) From: Richard Sandiford To: Prathamesh Kulkarni Mail-Followup-To: Prathamesh Kulkarni ,gcc Patches , richard.sandiford@arm.com Cc: gcc Patches Subject: Re: [aarch64] Use dup and zip1 for interleaving elements in initializing vector References: Date: Mon, 05 Dec 2022 10:52:30 +0000 In-Reply-To: (Prathamesh Kulkarni's message of "Tue, 29 Nov 2022 20:09:07 +0530") Message-ID: User-Agent: Gnus/5.13 (Gnus v5.13) Emacs/26.3 (gnu/linux) MIME-Version: 1.0 Content-Type: text/plain X-Spam-Status: No, score=-39.3 required=5.0 tests=BAYES_00,GIT_PATCH_0,KAM_DMARC_NONE,KAM_DMARC_STATUS,KAM_LAZY_DOMAIN_SECURITY,KAM_SHORT,SPF_HELO_NONE,SPF_NONE,TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: Prathamesh Kulkarni writes: > Hi, > For the following test-case: > > int16x8_t foo(int16_t x, int16_t y) > { > return (int16x8_t) { x, y, x, y, x, y, x, y }; > } > > Code gen at -O3: > foo: > dup v0.8h, w0 > ins v0.h[1], w1 > ins v0.h[3], w1 > ins v0.h[5], w1 > ins v0.h[7], w1 > ret > > For 16 elements, it results in 8 ins instructions which might not be > optimal perhaps. > I guess, the above code-gen would be equivalent to the following ? > dup v0.8h, w0 > dup v1.8h, w1 > zip1 v0.8h, v0.8h, v1.8h > > I have attached patch to do the same, if number of elements >= 8, > which should be possibly better compared to current code-gen ? > Patch passes bootstrap+test on aarch64-linux-gnu. > Does the patch look OK ? > > Thanks, > Prathamesh > > diff --git a/gcc/config/aarch64/aarch64.cc b/gcc/config/aarch64/aarch64.cc > index c91df6f5006..e5dea70e363 100644 > --- a/gcc/config/aarch64/aarch64.cc > +++ b/gcc/config/aarch64/aarch64.cc > @@ -22028,6 +22028,39 @@ aarch64_expand_vector_init (rtx target, rtx vals) > return; > } > > + /* Check for interleaving case. > + For eg if initializer is (int16x8_t) {x, y, x, y, x, y, x, y}. > + Generate following code: > + dup v0.h, x > + dup v1.h, y > + zip1 v0.h, v0.h, v1.h > + for "large enough" initializer. */ > + > + if (n_elts >= 8) > + { > + int i; > + for (i = 2; i < n_elts; i++) > + if (!rtx_equal_p (XVECEXP (vals, 0, i), XVECEXP (vals, 0, i % 2))) > + break; > + > + if (i == n_elts) > + { > + machine_mode mode = GET_MODE (target); > + rtx dest[2]; > + > + for (int i = 0; i < 2; i++) > + { > + rtx x = copy_to_mode_reg (GET_MODE_INNER (mode), XVECEXP (vals, 0, i)); Formatting nit: long line. > + dest[i] = gen_reg_rtx (mode); > + aarch64_emit_move (dest[i], gen_vec_duplicate (mode, x)); > + } This could probably be written: for (int i = 0; i < 2; i++) { rtx x = expand_vector_broadcast (mode, XVECEXP (vals, 0, i)); dest[i] = force_reg (GET_MODE_INNER (mode), x); } which avoids forcing constant elements into a register before the duplication. OK with that change if it works. Thanks, Richard > + > + rtvec v = gen_rtvec (2, dest[0], dest[1]); > + emit_set_insn (target, gen_rtx_UNSPEC (mode, v, UNSPEC_ZIP1)); > + return; > + } > + } > + > enum insn_code icode = optab_handler (vec_set_optab, mode); > gcc_assert (icode != CODE_FOR_nothing); > > diff --git a/gcc/testsuite/gcc.target/aarch64/interleave-init-1.c b/gcc/testsuite/gcc.target/aarch64/interleave-init-1.c > new file mode 100644 > index 00000000000..ee775048589 > --- /dev/null > +++ b/gcc/testsuite/gcc.target/aarch64/interleave-init-1.c > @@ -0,0 +1,37 @@ > +/* { dg-do compile } */ > +/* { dg-options "-O3" } */ > +/* { dg-final { check-function-bodies "**" "" "" } } */ > + > +#include > + > +/* > +** foo: > +** ... > +** dup v[0-9]+\.8h, w[0-9]+ > +** dup v[0-9]+\.8h, w[0-9]+ > +** zip1 v[0-9]+\.8h, v[0-9]+\.8h, v[0-9]+\.8h > +** ... > +** ret > +*/ > + > +int16x8_t foo(int16_t x, int y) > +{ > + int16x8_t v = (int16x8_t) {x, y, x, y, x, y, x, y}; > + return v; > +} > + > +/* > +** foo2: > +** ... > +** dup v[0-9]+\.8h, w[0-9]+ > +** movi v[0-9]+\.8h, 0x1 > +** zip1 v[0-9]+\.8h, v[0-9]+\.8h, v[0-9]+\.8h > +** ... > +** ret > +*/ > + > +int16x8_t foo2(int16_t x) > +{ > + int16x8_t v = (int16x8_t) {x, 1, x, 1, x, 1, x, 1}; > + return v; > +}