From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by sourceware.org (Postfix) with ESMTP id 032B33858D32 for ; Tue, 5 Sep 2023 14:58:45 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 032B33858D32 Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id BED4D11FB; Tue, 5 Sep 2023 07:59:22 -0700 (PDT) Received: from localhost (e121540-lin.manchester.arm.com [10.32.110.72]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 0C6343F64C; Tue, 5 Sep 2023 07:58:43 -0700 (PDT) From: Richard Sandiford To: Szabolcs Nagy Mail-Followup-To: Szabolcs Nagy ,, , , richard.sandiford@arm.com Cc: , , Subject: Re: [PATCH 07/11] aarch64: Disable branch-protection for pcs tests References: Date: Tue, 05 Sep 2023 15:58:42 +0100 In-Reply-To: (Szabolcs Nagy's message of "Tue, 22 Aug 2023 11:38:55 +0100") Message-ID: User-Agent: Gnus/5.13 (Gnus v5.13) Emacs/26.3 (gnu/linux) MIME-Version: 1.0 Content-Type: text/plain X-Spam-Status: No, score=-25.2 required=5.0 tests=BAYES_00,GIT_PATCH_0,KAM_DMARC_NONE,KAM_DMARC_STATUS,KAM_LAZY_DOMAIN_SECURITY,KAM_SHORT,SPF_HELO_NONE,SPF_NONE,TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: Szabolcs Nagy writes: > The tests manipulate the return address in abitest-2.h and thus not > compatible with -mbranch-protection=pac-ret+leaf or > -mbranch-protection=gcs. > > gcc/testsuite/ChangeLog: > > * gcc.target/aarch64/aapcs64/func-ret-1.c: Disable branch-protection. > * gcc.target/aarch64/aapcs64/func-ret-2.c: Likewise. > * gcc.target/aarch64/aapcs64/func-ret-3.c: Likewise. > * gcc.target/aarch64/aapcs64/func-ret-4.c: Likewise. > * gcc.target/aarch64/aapcs64/func-ret-64x1_1.c: Likewise. OK, thanks. Richard > --- > gcc/testsuite/gcc.target/aarch64/aapcs64/func-ret-1.c | 1 + > gcc/testsuite/gcc.target/aarch64/aapcs64/func-ret-2.c | 1 + > gcc/testsuite/gcc.target/aarch64/aapcs64/func-ret-3.c | 1 + > gcc/testsuite/gcc.target/aarch64/aapcs64/func-ret-4.c | 1 + > gcc/testsuite/gcc.target/aarch64/aapcs64/func-ret-64x1_1.c | 1 + > 5 files changed, 5 insertions(+) > > diff --git a/gcc/testsuite/gcc.target/aarch64/aapcs64/func-ret-1.c b/gcc/testsuite/gcc.target/aarch64/aapcs64/func-ret-1.c > index 5405e1e4920..7bd7757efe6 100644 > --- a/gcc/testsuite/gcc.target/aarch64/aapcs64/func-ret-1.c > +++ b/gcc/testsuite/gcc.target/aarch64/aapcs64/func-ret-1.c > @@ -4,6 +4,7 @@ > AAPCS64 \S 4.1. */ > > /* { dg-do run { target aarch64*-*-* } } */ > +/* { dg-additional-options "-mbranch-protection=none" } */ > /* { dg-additional-sources "abitest.S" } */ > > #ifndef IN_FRAMEWORK > diff --git a/gcc/testsuite/gcc.target/aarch64/aapcs64/func-ret-2.c b/gcc/testsuite/gcc.target/aarch64/aapcs64/func-ret-2.c > index 6b171c46fbb..85a822ace4a 100644 > --- a/gcc/testsuite/gcc.target/aarch64/aapcs64/func-ret-2.c > +++ b/gcc/testsuite/gcc.target/aarch64/aapcs64/func-ret-2.c > @@ -4,6 +4,7 @@ > Homogeneous floating-point aggregate types are covered in func-ret-3.c. */ > > /* { dg-do run { target aarch64*-*-* } } */ > +/* { dg-additional-options "-mbranch-protection=none" } */ > /* { dg-additional-sources "abitest.S" } */ > > #ifndef IN_FRAMEWORK > diff --git a/gcc/testsuite/gcc.target/aarch64/aapcs64/func-ret-3.c b/gcc/testsuite/gcc.target/aarch64/aapcs64/func-ret-3.c > index ad312b675b9..1d35ebf14b4 100644 > --- a/gcc/testsuite/gcc.target/aarch64/aapcs64/func-ret-3.c > +++ b/gcc/testsuite/gcc.target/aarch64/aapcs64/func-ret-3.c > @@ -4,6 +4,7 @@ > in AAPCS64 \S 4.3.5. */ > > /* { dg-do run { target aarch64-*-* } } */ > +/* { dg-additional-options "-mbranch-protection=none" } */ > /* { dg-additional-sources "abitest.S" } */ > /* { dg-require-effective-target aarch64_big_endian } */ > > diff --git a/gcc/testsuite/gcc.target/aarch64/aapcs64/func-ret-4.c b/gcc/testsuite/gcc.target/aarch64/aapcs64/func-ret-4.c > index af05fbe9fdf..15e1408c62d 100644 > --- a/gcc/testsuite/gcc.target/aarch64/aapcs64/func-ret-4.c > +++ b/gcc/testsuite/gcc.target/aarch64/aapcs64/func-ret-4.c > @@ -5,6 +5,7 @@ > are treated as general composite types. */ > > /* { dg-do run { target aarch64*-*-* } } */ > +/* { dg-additional-options "-mbranch-protection=none" } */ > /* { dg-additional-sources "abitest.S" } */ > /* { dg-require-effective-target aarch64_big_endian } */ > > diff --git a/gcc/testsuite/gcc.target/aarch64/aapcs64/func-ret-64x1_1.c b/gcc/testsuite/gcc.target/aarch64/aapcs64/func-ret-64x1_1.c > index 05957e2dcae..fe7bbb6a835 100644 > --- a/gcc/testsuite/gcc.target/aarch64/aapcs64/func-ret-64x1_1.c > +++ b/gcc/testsuite/gcc.target/aarch64/aapcs64/func-ret-64x1_1.c > @@ -3,6 +3,7 @@ > Test 64-bit singleton vector types which should be in FP/SIMD registers. */ > > /* { dg-do run { target aarch64*-*-* } } */ > +/* { dg-additional-options "-mbranch-protection=none" } */ > /* { dg-additional-sources "abitest.S" } */ > > #ifndef IN_FRAMEWORK