From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by sourceware.org (Postfix) with ESMTP id 901FB388E824 for ; Wed, 16 Mar 2022 17:12:19 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 901FB388E824 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 3FDE11476; Wed, 16 Mar 2022 10:12:19 -0700 (PDT) Received: from localhost (e121540-lin.manchester.arm.com [10.32.98.88]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id A74753F7D7; Wed, 16 Mar 2022 10:12:18 -0700 (PDT) From: Richard Sandiford To: "Andre Vieira \(lists\)" Mail-Followup-To: "Andre Vieira \(lists\)" , "gcc-patches\@gcc.gnu.org" , Kyrylo Tkachov , richard.sandiford@arm.com Cc: "gcc-patches\@gcc.gnu.org" , Kyrylo Tkachov Subject: Re: [aarch64] Update regmove costs for neoverse-v1 and neoverse-512tvb tunings References: <2c189f25-f37d-9ff1-130a-93a00f1c1cd0@arm.com> Date: Wed, 16 Mar 2022 17:12:17 +0000 In-Reply-To: <2c189f25-f37d-9ff1-130a-93a00f1c1cd0@arm.com> (Andre Vieira's message of "Wed, 16 Mar 2022 14:51:51 +0000") Message-ID: User-Agent: Gnus/5.13 (Gnus v5.13) Emacs/26.3 (gnu/linux) MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable X-Spam-Status: No, score=-10.9 required=5.0 tests=BAYES_00, BODY_8BITS, GIT_PATCH_0, KAM_DMARC_STATUS, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.4 X-Spam-Checker-Version: SpamAssassin 3.4.4 (2020-01-24) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 16 Mar 2022 17:12:21 -0000 "Andre Vieira (lists)" writes: > Hi, > > This patch updates the register move tunings for=20 > -mcpu/-mtune=3D{neoverse-v1,neoverse-512tvb}. > > 2022-03-16=C2=A0 Tamar Christina=C2=A0 > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0= =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 Andre Vieira <= andre.simoesdiasvieira@arm.com> > > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 * config/aarch64/aarch64.cc (= neoversev1_regmove_cost): New=20 > tuning struct. > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 (neoversev1_tunings): Use neo= versev1_regmove_cost and update=20 > store_int cost. > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 (neoverse512tvb_tunings): Lik= ewise. > > diff --git a/gcc/config/aarch64/aarch64.cc b/gcc/config/aarch64/aarch64.cc > index 9b6f67dc592d8a447d6b28390c90abe5dcfa5f08..f0485574528c47221e17a3aa5= aee70a56508f61e 100644 > --- a/gcc/config/aarch64/aarch64.cc > +++ b/gcc/config/aarch64/aarch64.cc > @@ -670,6 +670,16 @@ static const struct cpu_regmove_cost neoversen2_regm= ove_cost =3D > 2 /* FP2FP */ > }; >=20=20 > +static const struct cpu_regmove_cost neoversev1_regmove_cost =3D > +{ > + 1, /* GP2GP */ > + /* Spilling to int<->fp instead of memory is recommended so set > + realistic costs compared to memmv_cost. */ s/memmv_cost/memmov_cost/ Same for the earlier patches, I just didn't see it till now :-) OK with that change on the basis that it forms a pair with the follow-on memmov patch. Thanks, Richard > + 3, /* GP2FP */ > + 2, /* FP2GP */ > + 2 /* FP2FP */ > +}; > + > static const struct cpu_regmove_cost demeter_regmove_cost =3D > { > 1, /* GP2GP */ > @@ -2063,13 +2073,13 @@ static const struct tune_params neoversev1_tuning= s =3D > { > &cortexa76_extra_costs, > &neoversev1_addrcost_table, > - &generic_regmove_cost, > + &neoversev1_regmove_cost, > &neoversev1_vector_cost, > &generic_branch_cost, > &generic_approx_modes, > SVE_256, /* sve_width */ > { 4, /* load_int. */ > - 1, /* store_int. */ > + 2, /* store_int. */ > 6, /* load_fp. */ > 2, /* store_fp. */ > 6, /* load_pred. */ > @@ -2200,13 +2210,13 @@ static const struct tune_params neoverse512tvb_tu= nings =3D > { > &cortexa76_extra_costs, > &neoversev1_addrcost_table, > - &generic_regmove_cost, > + &neoversev1_regmove_cost, > &neoverse512tvb_vector_cost, > &generic_branch_cost, > &generic_approx_modes, > SVE_128 | SVE_256, /* sve_width */ > { 4, /* load_int. */ > - 1, /* store_int. */ > + 2, /* store_int. */ > 6, /* load_fp. */ > 2, /* store_fp. */ > 6, /* load_pred. */