Re: [PATCH V7] VECT: Add decrement IV support in Loop Vectorizer

[Richard Sandiford <richard.sandiford@arm.com>]

"juzhe.zhong@rivai.ai" <juzhe.zhong@rivai.ai> writes:
> Hi, Richard.
>
> RVV infrastructure in RISC-V backend status:
> 1. All RVV instructions pattern related to intrinsics are all finished (They will be called not only by intrinsics but also autovec in the future).
> 2. In case of autovec, we finished len_load/len_store (They are temporary used and will be removed after I support len_mask_load/len_mask_store in the middle-end).
>    binary integer autovec patterns.
>    vec_init pattern.
>    That's all we have so far.

Thanks.

> In case of testing of this patch, I have multiple rgroup testcases in local, you mean you want me to post them together with this patch?
> Since I am gonna to put them in RISC-V backend testsuite, I was planning to post them after this patch is finished and merged into trunk.
> What do you suggest ?

It would be useful to include the tests with the patch itself (as a patch
to the testsuite).  It doesn't matter that the tests are riscv-specific.

Obviously it would be more appropriate for the riscv maintainers to
review the riscv tests.  But keeping the tests with the patch helps when
reviewing the code, and also ensures that code is committed and never
later tested.

Richard