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From: Richard Sandiford <richard.sandiford@arm.com>
To: Prathamesh Kulkarni <prathamesh.kulkarni@linaro.org>
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 gcc Patches <gcc-patches@gcc.gnu.org>, richard.sandiford@arm.com
Cc: gcc Patches <gcc-patches@gcc.gnu.org>
Subject: Re: Missed lowering to ld1rq from svld1rq for memory operand
References: <CAAgBjM=5ELyC+e3McMiaS--hiaR1yqxzKqvT3466XGBQjC_jig@mail.gmail.com>
Date: Fri, 05 Aug 2022 13:19:03 +0100
In-Reply-To: <CAAgBjM=5ELyC+e3McMiaS--hiaR1yqxzKqvT3466XGBQjC_jig@mail.gmail.com>
 (Prathamesh Kulkarni's message of "Fri, 5 Aug 2022 17:02:22 +0530")
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Prathamesh Kulkarni <prathamesh.kulkarni@linaro.org> writes:
> Hi Richard,
> Following from off-list discussion, in the attached patch, I wrote pattern
> similar to vec_duplicate<mode>_reg, which seems to work for the svld1rq tests.
> Does it look OK ?
>
> Sorry, I didn't fully understand your suggestion on integrating with
> vec_duplicate<mode>_reg
> pattern. For vec_duplicate<mode>_reg, the operand to vec_duplicate expects
> mode to be <VEL>, while the pattern in patch expects operand of
> vec_duplicate to have mode <V128>.
> How do we write a pattern so an operand can accept either of the 2 modes ?

I quoted the wrong one, sorry, should have been
aarch64_vec_duplicate_vq<mode>_le.

> Also it seems <V128> cannot be used with SVE_ALL ?

Yeah, these would be SVE_FULL only.

Richard