From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by sourceware.org (Postfix) with ESMTP id 83E263858C74 for ; Thu, 12 Jan 2023 21:03:30 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 83E263858C74 Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 3D749FEC; Thu, 12 Jan 2023 13:04:12 -0800 (PST) Received: from localhost (e121540-lin.manchester.arm.com [10.32.99.50]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 343103F67D; Thu, 12 Jan 2023 13:03:29 -0800 (PST) From: Richard Sandiford To: Jakub Jelinek Mail-Followup-To: Jakub Jelinek ,gcc-patches@gcc.gnu.org, Florian Weimer , Andre Vieira , Andrew Pinski , Jeff Law , richard.sandiford@arm.com Cc: gcc-patches@gcc.gnu.org, Florian Weimer , Andre Vieira , Andrew Pinski , Jeff Law Subject: Re: [PATCH] Various fixes for DWARF register size computation References: <87pmbvx41g.fsf@oldenburg.str.redhat.com> <878rijwy0u.fsf@oldenburg.str.redhat.com> Date: Thu, 12 Jan 2023 21:03:27 +0000 In-Reply-To: (Jakub Jelinek's message of "Thu, 12 Jan 2023 18:07:37 +0100") Message-ID: User-Agent: Gnus/5.13 (Gnus v5.13) Emacs/26.3 (gnu/linux) MIME-Version: 1.0 Content-Type: text/plain X-Spam-Status: No, score=-31.6 required=5.0 tests=BAYES_00,KAM_DMARC_NONE,KAM_DMARC_STATUS,KAM_LAZY_DOMAIN_SECURITY,SPF_HELO_NONE,SPF_NONE,TXREP autolearn=no autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: Jakub Jelinek writes: > On Thu, Jan 12, 2023 at 04:50:07PM +0000, Richard Sandiford wrote: >> I'm jumping in here without fully understanding the context, so maybe this >> is exactly your point, but: the SIMD/FP DWARF registers are supposed to be >> size 8 regardless of which features are enabled. That's already only half >> of the hardware register size for base Armv8-A, since Advanced SIMD registers >> are 16 bytes in size. >> >> So yeah, if we're using the hardware register size then something is wrong. > > I'm talking about what the following compiles to > static unsigned char dwarf_reg_size_table[__LIBGCC_DWARF_FRAME_REGISTERS__+1]; > > void > foo (void) > { > __builtin_init_dwarf_reg_size_table (dwarf_reg_size_table); > } > (and therefore what libgcc/unwind-dw2.c (init_dwarf_reg_size_table) as well) > with -O2 -fbuilding-libgcc -march=armv8-a vs. -O2 -fbuilding-libgcc -march=armv8-a+sve > The former is setting I think [0..31, 46, 48..63, 72..79, 96]=8, [64..71, 80..95]=0 > (and leaving others untouched, which keeps them 0). > While the latter is setting [0..31, 46, 72..79, 96]=8, [64..71, 80..95]=0 > and [48..63]=cntd Ah, interesting. So the SIMD/FP registers are OK, but the predicate registers are causing a problem. I think we should set the predicates to size 0 too, like we do for call-clobbered FP registers. Predicate registers should never need to be represented in CFI. Thanks, Richard