From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by sourceware.org (Postfix) with ESMTP id 264A038582B7 for ; Fri, 24 Nov 2023 11:31:55 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 264A038582B7 Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=arm.com ARC-Filter: OpenARC Filter v1.0.0 sourceware.org 264A038582B7 Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1700825516; cv=none; b=nlGOtsfePIYcyuyQcmhFabB+svp3VqTnsF9X6S1ob+sjhqCA6br+2UXZPI7HgEGI95XJ4Og/yQ8T695lYMnsE06atz7yE87B2Y/952oKNaxhZKTBZO7iTC7NFxR4b5j5ogYVbVZIC7D6/aSHFef+dYrk7wQQEkbmgRItUhEGF58= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1700825516; c=relaxed/simple; bh=xQJ6Li37IM1WieT2xQ9etf1FRze0vgEy+B/MvTvqHk0=; h=From:To:Subject:Date:Message-ID:MIME-Version; b=ElZrgOay1HwEmbVQ07AtzYYnVwH0L0yZlM6hNBDRMowZ7amRHkiwcvOaIZ7CF/vY6W5htobetjp+rF+BRUIC1v4bBFyn+cj4AXoEalon4f5sxoUkhgXNR1rxJzEnRoR21gDyyv52p3s2nDMfwXFyZ6L2sQ6gMFLELdjefDV3u6o= ARC-Authentication-Results: i=1; server2.sourceware.org Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id ECDD01063; Fri, 24 Nov 2023 03:32:40 -0800 (PST) Received: from localhost (e121540-lin.manchester.arm.com [10.32.110.72]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id CACEB3F7A6; Fri, 24 Nov 2023 03:31:53 -0800 (PST) From: Richard Sandiford To: Victor Do Nascimento Mail-Followup-To: Victor Do Nascimento ,, , , richard.sandiford@arm.com Cc: , , Subject: Re: [PATCH 2/5] aarch64: rcpc3: Add relevant iterators to handle Neon intrinsics References: <20231109141300.3542453-1-victor.donascimento@arm.com> <20231109141300.3542453-3-victor.donascimento@arm.com> Date: Fri, 24 Nov 2023 11:31:52 +0000 In-Reply-To: <20231109141300.3542453-3-victor.donascimento@arm.com> (Victor Do Nascimento's message of "Thu, 9 Nov 2023 14:12:45 +0000") Message-ID: User-Agent: Gnus/5.13 (Gnus v5.13) Emacs/26.3 (gnu/linux) MIME-Version: 1.0 Content-Type: text/plain X-Spam-Status: No, score=-22.6 required=5.0 tests=BAYES_00,GIT_PATCH_0,KAM_DMARC_NONE,KAM_DMARC_STATUS,KAM_LAZY_DOMAIN_SECURITY,SPF_HELO_NONE,SPF_NONE,TXREP,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: Victor Do Nascimento writes: > The LDAP1 and STL1 Neon ACLE intrinsics, operating on 64-bit data > values, operate on single-lane (Vt.1D) or twin-lane (Vt.2D) SIMD > register configurations, either in the DI or DF modes. This leads to > the need for a mode iterator accounting for the V1DI, V1DF, V2DI and > V2DF modes. > > This patch therefore introduces the new V12DIF mode iterator with > which to generate functions operating on signed 64-bit integer and > float values and V12DIUP for generating the unsigned and > polynomial-type counterparts. Along with this, we modify the > associated mode attributes accordingly in order to allow for the > implementation of the relevant backend patterns for the intrinsics. > > gcc/ChangeLog: > > * config/aarch64/iterators.md (V12DIF): New. > (V12DUP): Likewise. > (VEL): Add support for all V12DIF-associated modes. > (Vetype): Add support for V1DI and V1DF. > (Vel): Likewise. > --- > gcc/config/aarch64/iterators.md | 25 +++++++++++++++++-------- > 1 file changed, 17 insertions(+), 8 deletions(-) > > diff --git a/gcc/config/aarch64/iterators.md b/gcc/config/aarch64/iterators.md > index f9e2210095e..471438e27be 100644 > --- a/gcc/config/aarch64/iterators.md > +++ b/gcc/config/aarch64/iterators.md > @@ -314,6 +314,12 @@ > ;; All byte modes. > (define_mode_iterator VB [V8QI V16QI]) > > +;; 1 and 2 lane DI and DF modes. > +(define_mode_iterator V12DIF [V1DI V1DF V2DI V2DF]) > + > +;; 1 and 2 lane DI mode for unsigned and poly types. > +(define_mode_iterator V12DIUP [V1DI V2DI]) Probably easiest just to call it V12DI, without the UP. The same iterator could be useful in other situations. > + > ;; 2 and 4 lane SI modes. > (define_mode_iterator VS [V2SI V4SI]) > > @@ -1195,10 +1201,10 @@ > (define_mode_attr Vetype [(V8QI "b") (V16QI "b") > (V4HI "h") (V8HI "h") > (V2SI "s") (V4SI "s") > - (V2DI "d") > + (V2DI "d") (V1DI "d") > (V4HF "h") (V8HF "h") > (V2SF "s") (V4SF "s") > - (V2DF "d") > + (V2DF "d") (V1DF "d") > (V2x8QI "b") (V2x4HI "h") > (V2x2SI "s") (V2x1DI "d") > (V2x4HF "h") (V2x2SF "s") > @@ -1358,10 +1364,12 @@ > (define_mode_attr VEL [(V8QI "QI") (V16QI "QI") > (V4HI "HI") (V8HI "HI") > (V2SI "SI") (V4SI "SI") > - (DI "DI") (V2DI "DI") > + (DI "DI") (V1DI "DI") > + (V2DI "DI") Very, very minor, but: would be good to have one fewer space before "DI", so that the quotes line up. > (V4HF "HF") (V8HF "HF") > (V2SF "SF") (V4SF "SF") > - (DF "DF") (V2DF "DF") > + (DF "DF") (V1DF "DF") > + (V2DF "DF") Same here. OK for trunk with those changes, thanks. Richard > (SI "SI") (HI "HI") > (QI "QI") > (V4BF "BF") (V8BF "BF") > @@ -1378,12 +1386,13 @@ > (define_mode_attr Vel [(V8QI "qi") (V16QI "qi") > (V4HI "hi") (V8HI "hi") > (V2SI "si") (V4SI "si") > - (DI "di") (V2DI "di") > + (DI "di") (V1DI "si") > + (V2DI "di") > (V4HF "hf") (V8HF "hf") > (V2SF "sf") (V4SF "sf") > - (V2DF "df") (DF "df") > - (SI "si") (HI "hi") > - (QI "qi") > + (V1DF "df") (V2DF "df") > + (DF "df") (SI "si") > + (HI "hi") (QI "qi") > (V4BF "bf") (V8BF "bf") > (VNx16QI "qi") (VNx8QI "qi") (VNx4QI "qi") (VNx2QI "qi") > (VNx8HI "hi") (VNx4HI "hi") (VNx2HI "hi")